JPH03165121A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce power noise by providing a transit period output control means applying cut-off control on a load transistor(TR) and a driving TR being constituting an output circuit in the complementary push-pull form at a transit period when the output is changed. CONSTITUTION:A transit period output control means is provided, which applies cut-off control to a load transistor(TR) and a driving TR constituting the output circuit in the complementary push-pull form at the transit period when the output is changed. That is, an output control circuit (transit period output control circuit) 14 at output transient response applying cut-off control to both MOSFETs Q1, Q2 at the transit period when an output of a CMOS inverter 11 is changed is provided between a pre-buffer 12 and a tri-state output control circuit 13. The transit period output control means 14 acts like controlling the output circuit 10 into a high output impedance state for the transient response period of the output waveform. Thus, power noise or through-current caused in the output circuit is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit and to a technique for reducing power supply noise during output operation thereof.

For example, the present invention relates to a technique that is effective when applied to a 0MO8 type semiconductor integrated circuit or a hybrid integrated circuit including a bipolar transistor and a CMOS circuit.

[Prior art]

Complementary push-pull circuit e.g. CMOS
The inverter is an n-channel MO8FE with different conductivity types.
Since the T and p-channel type MO5FETs are switch controlled in a complementary manner to the input, even if a through current flows temporarily during a transient response, no through current will occur for fixed inputs of high level and low level. , and the entire power supply voltage can be used as the output signal amplitude. By the way, when such a CMO8 circuit is used for an output circuit such as an output buffer, a relatively large driving capacity is required due to its nature, and the transistor size is accordingly increased. Furthermore, logic LSIs and memory LSIs such as microcomputers are designed to output multiple bits or multiple bits simultaneously. Therefore, depending on the bit pattern in which multiple bits are output simultaneously, a large current flows through the power supply wiring at the same time, causing an undesirable increase in the ground potential or an undesirable decrease in the power supply potential.

Such voltage fluctuations are applied as undesired noise to the input circuit of the semiconductor integrated circuit, causing malfunctions. In particular, when the device is interfaced with the outside at a relatively low level of input noise mask on the ground potential side, such as at the TTL (transistor-transistor-logic) level, the influence of power supply noise on the ground potential side becomes significant.

In order to reduce power supply noise, which is conventionally rejected, the output node is discharged in advance by the circuit before the output stage.

It is possible to soften the transient response of the output waveform by relaxing changes in the input signal to the output circuit, or to connect two external terminals that perform multi-bit synchronous output operation, such as the data output terminal group.
It is also conceivable to divide it into groups and shift the output timing of each group.

An example of a document describing power supply noise in semiconductor integrated circuits is Nikkei Electronics, No. 462 (December 12, 1988), published by Nikkei McGraw-Hill, No. 2.
Pages 86 to 288, No. 453 (August 8, 1988), Pages 224 to 227, No. 455 (September 1988)
May 5th) There are pages 119 to 136.

[Problem to be solved by the invention]

However, with the technique of slowing down the transient response of the output waveform, it is not possible to make it extremely slow due to the relationship with the output operation speed, and therefore it is not possible to reduce the power supply noise as much as expected. Moreover, the slower the transient response, the more the through current will increase. In addition, the inventor investigated a technique for dividing external terminals that perform multi-bit synchronous output operations into several groups and staggers the output timing of each group, and found that when external terminals that perform simultaneous output operations are adjacent to each other, It was found that the effect of reducing power supply noise could not be obtained.

An object of the present invention is to provide a semiconductor integrated circuit that can reduce power supply noise generated in an output circuit during a transient response of an output waveform. Another object of the present invention is to provide a semiconductor integrated circuit that can substantially eliminate through current generated in an output circuit during a transient response of an output waveform.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, in order to suppress power supply noise and through current due to the configuration of the output circuit, cut-off control is performed on the load transistor and drive transistor that make up the output circuit in a complementary push-pull configuration during the transition period when the output changes. A transition period output control means is provided. Or,
When the output is changed from a low level to a low level, the turn-on operation of the drive transistor is delayed compared to the turn-off of the load transistor, and when the output is changed from a low level to a high level, the turn-on operation of the drive transistor is delayed. A transition period output control means for delaying the turn-on operation of the load transistor is provided.

In addition, in order to reduce power supply noise from the viewpoint of the operation timing of the output circuit, a timing adjustment means for alternately shifting the output operation timing of a plurality of output circuits that operate during the output operation for each output terminal or several output terminals. It is intended to provide Alternatively, external terminals that are outputted at the same timing via the output circuit are arranged every single or every few external terminals.

[For production]

According to the above means, the transition period output control means acts to control the output circuit to a high output impedance state during the transient response period of the output waveform, thereby suppressing power supply noise and through current generated in the output circuit. The goal is to achieve the following.

In addition, the operation timing of output circuits that operate synchronously in output operation may be alternately shifted for each output terminal or several output terminals using a timing adjustment means, or external terminals that operate at the same timing may be arranged every other or every few output terminals. The important thing to keep in mind is to reduce the absolute amount of charge/discharge current to external output terminals that changes simultaneously during output operation, and to supply current to individual output circuits at mutually distributed locations on the power supply wiring. Thus, it is possible to reduce the power supply noise generated in the output circuit during a transient response of the output waveform.

〔Example〕

FIG. 8 schematically shows an entire semiconductor integrated circuit according to an embodiment of the present invention. Although not particularly limited, this semiconductor integrated circuit is an LSI for serial communication control formed on one semiconductor substrate 1 such as silicon by semiconductor integrated circuit manufacturing technology, and on the semiconductor substrate 1, two MSCI (Multi-Protocol Serial Communication Interface) Unit 2, D
MAC (direct memory access control) unit 3, timer unit 4. It also includes a control unit 5, and various peripheral circuits 6 including input circuits, output circuits, etc. are arranged around it.

FIG. 1 shows an example of an output circuit included in the peripheral circuit 6, and FIG. 2 shows an operational truth diagram of the output circuit.

The output circuit 10 shown in the figure has a P-channel type load M
O8FETQI and n-channel drive MO8FETQ2
A final output stage (hereinafter also simply referred to as a CMOS inverter) 11 consisting of a complementary push-pull connection of
The pre-buffer 12 has a tri-state output control circuit 13, and between the pre-buffer 12 and the tri-state output control circuit 13, both MO8FET QI
, Q2 are provided with an output control circuit (hereinafter simply referred to as a transition period output control circuit) 14 during an output transient response.

The size of the transistors constituting the CMOS inverter 11 is made larger than that of a MOSFET which performs an output operation to the outside and performs other logic operations, so that it has a relatively large current driving ability. The MO3FE
The source electrode of the TQI is supplied with a power supply voltage Vdd from a power supply wiring, and the source electrode of the MO3FETQ2 is supplied with a ground potential Vss from a ground wiring. and.

The output terminal of CMOS inverter 11 is coupled to output pad 19. The pre-buffer 12 is composed of, for example, two CMOS inverters 12A and 12B, the output terminals of which are individually connected to the gate electrodes of MOSAFETs QI and Q2.

The tri-state output control circuit 13 includes, but is not particularly limited to, a two-man operated Nantes gate 15 and a Noah gate 1.
6. It also includes an inverter 17.

This tri-state output control circuit 13 includes an output circuit 10
Control signal GA for selecting/deselecting the output operation of
A signal SIG is provided which is transmitted via TE and internal logic. The control signal GATE is set to a high level when the output circuit 1o is in a non-selected state or activated, thereby causing the output of the NOR gate 16 to be set to a low level and the output of the NAND gate 15 to be set to a high level. This output level is finally given to the pre-buffer 12 through a transition period output control circuit 14, the details of which will be explained later. Therefore, in this state, both MO3FETs QI and Q2 are cut off, and the CMOS inverter 11 is controlled to a high output impedance state. The control signal GAT
When E is set to low level, the Nant gate 15 and the NOR gate 16 output the inverted level of the signal SIG, and this output level is finally given to the pre-buffer 12 through the transition period output control circuit 14. Therefore, the CMOS inverter 11 outputs a high level in response to the low level of the signal SIG, and the CMOS inverter 11 outputs a low level in response to the high level of the signal SIG.

The transition period output control circuit 14 includes a two-manpower type AND gate 20 and a two-manpower type OR gate 21, and both gates 2
Delay circuits 22 and 23 are installed on one input terminal side of 0.21, respectively.
is constructed by intervening.

Incidentally, the delay circuits 22 and 23 are constituted by an even number of stages of inverters or circuit elements having a resistance component or a capacitance component to obtain a required CR time constant.

As shown in FIG. 3, the delay circuit 22 is configured to delay the timing at which the output of the AND gate 2o changes from low level to high level when the output of NOR gate 16 changes from low level to high level. acts,
Further, the delay circuit 23 acts to delay the timing at which the output of the OR gate 21 changes from high level to low level when the output of the Nant gate 15 changes from high level to low level. That is, this transition period output control circuit 14 controls the CM as shown in (■) in FIG.
When the output of the OS inverter 11 is changed from high level to low level, the turn-on operation of MO8FETQ2 is delayed from the turn-off of MO8FETQI, and the CMOS inverter 11 is kept in a high output impedance state (Hi −Z). In addition, as shown in Figure 3, the CMOS inverter 1
When the output of MO8FE1 is changed from low level to high level, MO8FE is turned off more than MO5FETQ2 is turned off.
The turn-on operation of the TQI is delayed, and the CMOS inverter 11 is controlled to a high output impedance state (Hi-Z) during the period indicated by .

Therefore, during the transient response period when the output of the CMOS inverter 11 is inverted, the P-channel type MO3FETQ
Since both the I and N channel type MO8FETQ2 are prevented from being turned on even temporarily, no through current flows through the CMOS inverter 11 during output inversion operation, thereby reducing power consumption. Power supply noise can be suppressed.

An example of another output circuit is shown in FIG.

The output circuit 30 shown in the figure has a configuration in which its output level is determined to be high level or low level according to the level of signal SIG, and has a P-channel type load MO5FET.
A final output stage (hereinafter also referred to as a CMOS inverter) 31 consisting of a complementary push-pull connection of Q3 and an N-channel drive MO3FET Q4, a pre-buffer 32, and the Both MO8FETQ3. An output control circuit during an output transient response (hereinafter simply referred to as a transition period output control circuit) 33 is provided to cut off Q4.

The size of the transistors constituting the CMOS inverter 31 is made larger than that of MOSFETs that perform other logic operations because of the nature of outputting to the outside, so that the CMOS inverter 31 has a relatively large current driving capability. Said MO8FE
The source electrode of TQ3 is supplied with a power supply voltage Vdd from a power supply wiring, and the source electrode of the MO5FETQ4 is supplied with a ground potential Vss from a ground wiring. and,
The output terminal of CMOS inverter 31 is coupled to output pad 34. The pre-buffer 32 is composed of, for example, two CMOS inverters 32A and 32I3, and the output terminals thereof are individually connected to MO8FETQ3. Connected to the gate electrode of Q4.

The transition period output control circuit 33 is a two-man powered Noah gate 3.
5.36 is cross-coupled to the other output terminal, and the output terminal of each NOR gate 35.36 is provided with a delay circuit 37.38. A signal SIG is applied to the other input terminal of the NOR gate 35, and a signal obtained by inverting the signal SIG by a CMOS inverter 39 is applied to the other input terminal of the NOR gate 36. The output terminal of the delay circuit 37 is coupled to the input terminal of the CMOS inverter 32A, and the output terminal of the delay circuit 38 is coupled via the CMOS inverter 40 to the input terminal of the CMOS inverter 32B.

Similarly to the output circuit 10, this transition period output side m circuit 33 is also controlled so that the input signal levels of MO8FETQ3 and MO8FETQ4 do not overlap. Therefore, in this output circuit 30 as well, during the transient response period in which the output of the CMOS inverter 31 is inverted, the P-channel type MO8F
This is because both ETQ3 and N-channel type MO8FETQ4 are prevented from being turned on even temporarily.

During the output inversion operation, no through current flows through the CMOS inverter 31, thereby reducing power consumption and suppressing power supply noise.

FIG. 5 shows an embodiment for reducing power supply noise by shifting the output operation timing between a large number of output circuits.

FIG. 5 shows, for example, eight output circuits 51 to 58 and eight output pads 61 to 68 coupled to their output terminals, which are included in the peripheral circuit 6 of FIG. . Although the respective output circuits 51 to 58 are not particularly limited,
It has a circuit similar to that shown in FIG. 1, or a tri-state output type circuit configuration in which the transition period output control circuit 14 is omitted in the circuit configuration shown in FIG.
Used for synchronous output of 5IG8. Tri-state output control for each of the output circuits 51 to 58 is performed by the first
It is controlled by the control signal GATE, which has the same meaning as explained in the figure. Although the eight output circuits 51 to 58 perform output operations synchronously due to the operation of the semiconductor integrated circuit, the output operation timing of each output circuit is alternately shifted every other output circuit within the permissible range. , output circuit 52
, 54.56.58 have two CMOS connected in series.
Control signal GATE is applied via inverter 70.71, and control signal GATE is applied directly to other output circuits 51, 53, 55.57. The two CMOS inverters 70 and 71 function as delay circuits, and can be replaced with other delay elements. Furthermore, the number of output circuits whose output timings are alternately shifted is not limited to one, but may be every several, such as two. Such a configuration is functionally equivalent to a configuration in which external terminals such as output pads, which are outputted at the same timing via an output circuit, are arranged every other or several external terminals.

FIG. 6 shows an example of the output waveforms when the outputs of the output circuits 51 to 58 are all changed synchronously. As is clear from the figure, the output change timing is changed at mutually shifted timing in four output circuits. Furthermore, the outputs of adjacent output circuits are changed at mutually shifted timings.

Output circuits 51 to 58 that operate synchronously in output operation in this way
By alternately shifting the operation timing of every one or every few external terminals, or by arranging every one or every few external terminals that output at the same timing, eight output circuits 51 to 58 can be used. During synchronous output operation, the absolute amount of charging and discharging current to the output pads whose outputs change simultaneously is reduced, and current can be supplied to individual output circuits at mutually distributed locations on the power supply wiring. , power supply noise generated in the output circuit during transient response of the output waveform can be reduced.

In the explanation of FIGS. 5 and 6, the output change timing is shifted in two steps, but it may be shifted in three or more steps to further reduce power supply noise.

FIG. 7 shows an example of an output waveform when the output timing is shifted in four steps, for example. To do this,
The control signal GATE is applied to the output circuits 51 and 55 in FIG.
is supplied as is, and a 4-stage CMO
A delayed control signal GATE is supplied via an S inverter, a delayed control signal GATE is supplied via a two-stage CMOS inverter to an output circuit 53.57, and a six-stage CMOS inverter is supplied to an output circuit 54.58. It is sufficient to supply the delayed control signal GATE via the .

In particular, mm power supply noise can be reduced by increasing the difference in output timing between adjacent devices as shown in FIG.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, the complementary push-pull type output stage was explained as a CMOS inverter, but the present invention is not limited thereto, and can also be applied to a circuit using an N-channel MO3FET as a load transistor and a drive transistor. , and the logic of the tristate output control circuit is changed accordingly. Further, the semiconductor integrated circuit to which the present invention is applied is not limited to the configuration shown in FIG.
Furthermore, it can be applied to memory LSIs and the like.

In the above description, the invention made by the present inventor was mainly applied to a CMO3 type semiconductor integrated circuit, which is the background field of application, but the present invention is not limited thereto. It can be widely applied to CMO5 type semiconductor integrated circuits as well as bipolar type semiconductor integrated circuits. The present invention can be applied to conditions including an output circuit in which at least a load transistor and a drive transistor are connected in a complementary push-pull manner.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, during the transition period when the output is changed, there is a transition period output control means that performs cut-off control on the load transistor and the drive transistor that constitute the output circuit in a complementary push-pull configuration, or when the output changes from a high level to a low level. When the output is changed from low level to high level, the turn-on operation of the drive transistor is delayed compared to the turn-off operation of the load transistor, and when the output is changed from low level to high level, the turn-on operation of the load transistor is delayed rather than the turn-off operation of the drive transistor. By providing a transition period output control means that delays the operation, it acts to control the output circuit to a high output impedance state during the transient response period of the output waveform, thereby suppressing power supply noise and shoot-through current generated in the output circuit. It has the effect of being able to achieve the following.

In addition, the operation timing of output circuits that operate synchronously in output operation may be alternately shifted for each output terminal or several output terminals using a timing adjustment means, or external terminals that operate at the same timing may be arranged every other or every few output terminals. By doing so, there is an effect that power supply noise generated in the output circuit during a transient response of the output waveform can be reduced from the viewpoint of the operation timing of the output circuit to be operated synchronously.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram of an example of an output circuit applied to a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is an explanatory diagram of the operation truth values taken by the output circuit of FIG. 1, FIG. 3 is a diagram of m operation timing charts in the output circuit of FIG. 1, and FIG. 4 is another logic circuit diagram of the output circuit. Fig. 5 is a circuit diagram of an embodiment for reducing power supply noise by shifting the output operation timing between a large number of output circuits, Fig. 6 is a chart of the m operation timings of Fig. 5, and Fig. 7 is FIG. 8 is an overall block diagram of a semiconductor integrated circuit according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 6...Peripheral circuit, 1o...Output circuit, 11...CMOS inverter, Ql...P
Channel type load MO8FET, Q2... N-channel type drive MO8FET, 12... Pre-buffer, 13
... Tri-state output control circuit, 14... Transition period output control circuit, 19... Output pad, 22.23...
・Delay circuit, 30... Output circuit, 31... CMOS
Inverter, Q3...P channel type load MO3FE
T, Q4...N-channel type drive MO3FET, 32
... pre-buffer, 33... transition period output control circuit,
34... Output pad, 51-58 output circuit, 61-6
8...Output pad, 70.71...CMOS inverter. Figure Figure Figure 5 Figure Figure Figure Figure 5

Claims (1)

[Claims] 1. In a semiconductor integrated circuit including an output circuit in which a load transistor and a drive transistor are connected in a complementary push-pull manner, a transition in which both transistors are controlled to cut off during a transition period in which the output is changed. A semiconductor integrated circuit characterized by being provided with a periodic output control means. 2. In a semiconductor integrated circuit including an output circuit in which a load transistor and a drive transistor are connected in a complementary push-pull manner, when the output is changed from a high level to a low level, the drive transistor turns off more than the load transistor turns off. A semiconductor characterized in that it is provided with a transition period output control means that delays the on operation and delays the turn on operation of the load transistor than the turn off of the drive transistor when the output is changed from a low level to a high level. integrated circuit. 3. In a semiconductor integrated circuit in which a plurality of external terminals individually coupled to output circuits are arranged in parallel on a semiconductor substrate, the output operation timing of the plurality of output circuits that operate synchronously in the output operation can be determined in a single or a number. 1. A semiconductor integrated circuit comprising timing adjustment means for alternately shifting each output terminal. 4. In a semiconductor integrated circuit in which a plurality of external terminals individually coupled to an output circuit are arranged in parallel on a semiconductor substrate, one or more external terminals are operated to output at the same timing via the output circuit. A semiconductor integrated circuit characterized by being arranged at intervals.