JPH0316436A - Error correction device - Google Patents

Abstract

PURPOSE:To improve the error correction capability to a frame length by selecting a frame length shorter than a frame length calculated from an added parity length in the case of error correction by using a BCH code. CONSTITUTION:A serial data is inputted via an input terminal (a) and the data is sectioned by 187 bits each and a 16-bit parity is calculated by a BCH code parity arithmetic circuit 1, a parity and a synchronizing signal are inserted to the data by a BCH code frame generating circuit 2 to constitute the frame, which is sent to a transmission line 4. An error correction circuit 7 inverts the data of a location having an error to apply error correction and the synchronous signal and the parity of the BCH code are eliminated and only the data is sent from an output terminal (g). Thus, the capability of error correction up to 2-bit in 255 bits is improved to the error correction up to 2-bit in 203 bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction device using a BCH code. B C H code is Bose-Chaudhur i-
It is a Hocquenghem code and is a cyclic code.

〔overview〕

In an error correction means using a BCH code, the present invention can perform error correction if there is a one-to-one correspondence between the result of division by a raw polynomial, the remainder of 1, and the error position. By delimiting and encoding the frame length within the specified frame length, the error correction ability can be improved.

[Conventional technology]

In the conventional example, when performing error correction using a BCH code, a code with a frame length calculated from the added parity length was used.

[Problem that the invention seeks to solve]

In such a conventional example, since the frame length calculated from the parity length was used, there was a drawback that when the parity length was determined, the frame length was also determined, and the error correction capability was also determined.

The present invention aims to eliminate such drawbacks and to provide an error correction device using a BCH code that can improve error correction capability.

[Failure to solve the problem]

The present invention provides parity calculation means for dividing incoming serial data into code lengths of k bits and calculating n-bit parity for the divided data; code creation means for creating a BCH code including; decoding calculation means for dividing the delimited data by a generator or polynomial; and error position determining means for determining the positions of the m error bits based on the remainder obtained by the calculation means. In an error correction device comprising a determining means and an error correcting means for correcting the bit at the position determined by the error position determining means, the number of bits of the divided data has a base of 2 and a power of n. t from a number that is the value divided by m
is smaller than the value obtained by subtracting , and the combination of remainders obtained by the arithmetic means has a number smaller than a value whose base is 2 and whose power is n-i.

[Operation,] BC}I encoding is performed so that when the parity obtained by calculating the transmitted data and the raw polynomial is added to the transmitted data, the remainder becomes "0" by division with the raw polynomial. , during BCHtl encoding, the remainder is obtained by division with the received data, and the error position is determined from this remainder value. Errors can be corrected if the parity length is corrected, so error correction can be performed if the frame length is within the frame length calculated from the parity length.

That is, even if the frame length is shortened, the number of bits that can be corrected remains the same, and the error correction ability is improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. The figure is a block diagram showing the structure of this embodiment.

As shown in the figure, this embodiment includes a transmitting circuit 1-1 and a receiving circuit 1-2, where the transmitting circuit 1-1 is
The receiving side circuit 1-2 includes a BCH code parity calculation circuit 1, a BCH code frame creation circuit 2, and an encoder timing generation circuit 3. and an error correction circuit 7.

That is, in this embodiment, incoming serial data is divided into code lengths of k bits, and n
B, which is a parity calculation means that calculates bit parity;
a CH code parity calculation circuit 1; a BCH code frame creation circuit 2 which is a code creation means for creating a BCH code including the delimited data and n-bit parity;
The date separated above? The BCH code decoding calculation circuit 5 is a decoding calculation means for dividing by a generator polynomial, and the error detection circuit 5 is an error position determination means for determining the position of m error bits based on the remainder obtained by this calculation means. The above-mentioned system is equipped with a position calculation circuit 6 and an error correction circuit 7 which is an error/TLF means for correcting the bit at the position determined by the error position determination means. 1 fixed number of bits of separated data has a base of 2, and F is divided by m. Group-7) The combination is bottom 2, top power is n- 1
The number is smaller than the value.

Next, the operation of this embodiment will be explained. B C } {Ladle number used in this example is (255, 239) B C
H code <203, 1. ．． ．． 87) This is an example transformed into a BCH code. , where the generator polynomial is g (:
x ) 1x I 6→χl 4 +Xl 10X
”→x 1.0-x 9-+1y B +xli↓X5
→−χ+1 is used, and from this encoding 1;゛, 1 frame l・
．． Error correction of 2 bits per bit is possible, and the code length e, the number of bits m that can correct errors, and the parity length n are l
Since there is a relationship of 2'''-1, the parity length is 1 (if it is possible to correct 2 bits of error with i bits, the code length l is 255
In this example, the code length is 255 bits.
This is the case when the bits are shortened to 203 bits.

The serial data is input manually through the manual terminal a, and the data is
The BCH code parity calculation circuit 1 calculates 16-bit parity by dividing the data into 87-bit units, and the BCH code frame creation circuit 2 inserts parity and synchronization signals into the data to form a frame, and sends it to the transmission line 3. . In the receiving side circuit 1-2, the received data d is sent to the BCH code decoding unit 5.
The calculation result e is input to the error position calculation circuit 6 to determine the position where the error has occurred, and a signal f indicating the position where the error has occurred is sent out.

The error correction circuit 7 performs error correction by inverting the data at the position where the error has occurred, removes the synchronization signal and the parity of the BCH code, and sends only the data from the output terminal g.

In the code shown in this embodiment, the ability to correct errors up to 2 bits out of 255 bits is improved to the point where errors can be corrected up to 2 out of 203 bits.

〔Effect of the invention〕

As explained above, when performing error correction using a BCH code, the present invention improves the error correction ability for the frame length by selecting a frame length shorter than the frame length calculated from the parity length to be added. There is an effect that can be used.

[Brief explanation of the drawing]

The figure is a block diagram showing the structure of an embodiment of the present invention. 1...BCH code parity calculation circuit, 2...BCH
Code frame creation circuit, 3... Encoder timing generation circuit, 4... Transmission path, 5... BCH code decoding calculation circuit, 6... Error position calculation circuit, 7... Error correction Circuit, 1-1...Sending side circuit, 1-2...Receiving side circuit.

Claims (1)

[Claims] 1. Divide the incoming serial data into code lengths of k bits,
parity calculating means for calculating n-bit parity for this delimited data; code creation means for creating a BCH code including this delimited data and n-bit parity; and a generating polynomial for generating the delimited data. a decoding calculation means for dividing by , an error position determination means for determining the positions of the m error bits based on the remainder obtained by this calculation means, and a correction for the bits at the positions determined by the error position determination means. an error correction device comprising an error correction means, wherein the number of bits of the delimited data is smaller than a value obtained by subtracting 1 from a value having a base of 2 and a power of n divided by m, and the above calculation means; The combination of remainders obtained is 2
An error correction device characterized in that the number is smaller than a number whose base is n-1.