JPH03163884A - Epitaxial wafer and manufacture thereof - Google Patents

Epitaxial wafer and manufacture thereof

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Publication number
JPH03163884A
JPH03163884A JP1303677A JP30367789A JPH03163884A JP H03163884 A JPH03163884 A JP H03163884A JP 1303677 A JP1303677 A JP 1303677A JP 30367789 A JP30367789 A JP 30367789A JP H03163884 A JPH03163884 A JP H03163884A
Authority
JP
Japan
Prior art keywords
layer
composition
epitaxial wafer
constant
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1303677A
Other languages
Japanese (ja)
Other versions
JPH0760903B2 (en
Inventor
Tadashige Sato
忠重 佐藤
Hisanori Fujita
尚徳 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Kasei Polytec Co
Mitsubishi Kasei Corp
Original Assignee
Mitsubishi Kasei Polytec Co
Mitsubishi Kasei Corp
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Filing date
Publication date
Application filed by Mitsubishi Kasei Polytec Co, Mitsubishi Kasei Corp filed Critical Mitsubishi Kasei Polytec Co
Priority to JP30367789A priority Critical patent/JPH0760903B2/en
Priority to KR1019900018946A priority patent/KR100210758B1/en
Priority to DE4037198A priority patent/DE4037198B4/en
Publication of JPH03163884A publication Critical patent/JPH03163884A/en
Priority to US08/069,672 priority patent/US5445897A/en
Publication of JPH0760903B2 publication Critical patent/JPH0760903B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02392—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
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    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Crystallography & Structural Chemistry (AREA)
  • Led Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＧａＡｓ又はＧａＰ単結晶基板上にＧａＡｓ＋
−ｘＰ’＋単結晶層を成長させたエピタキシャルウェハ
において、単結晶基板とＧ　ａ　Ａ　ｓ　ｌ−ｘＰ．，
層の間に組成をｘ＝０から徐々に変化させた後一定のＸ
をもつＧ’ａ　Ａ　ｓ　ｌ−ｘ　Ｐ．層を成長させたエ
ピタキシャルウェハとその製法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a method for forming GaAs+ on a GaAs or GaP single crystal substrate.
In the epitaxial wafer on which the -xP'+ single crystal layer is grown, the single crystal substrate and the Ga As l-xP. ，
Constant X after gradually changing the composition from x = 0 between layers
G'a A s l-x P. This invention relates to an epitaxial wafer on which layers are grown and its manufacturing method.

〔従来の技術〕[Conventional technology]

ＧａＰ単結晶基板上にＧａＡｓ＋−ｘＰｘ単結晶膜をエ
ピタキシャル成長させたウエハは、後にＺｎを拡散して
ＰＮ接合を形成し、発光ダイオードとして広く用いられ
ている。ＧａＡｓ，−、Ｐ．層には、通常アイソエレク
トリックトラップとして窒素（Ｎ）をドーピングして発
光効率を上げている。発光ダイオードの発光波長は組成
Ｘによって決定され、黄色発光用はｘ＝０．９、橙色発
光用はｘ＝０．７５、赤色用はｘ＝０、６５を用いる。A wafer in which a GaAs+-xPx single crystal film is epitaxially grown on a GaP single crystal substrate is later diffused with Zn to form a PN junction, and is widely used as a light emitting diode. GaAs,-,P. The layer is usually doped with nitrogen (N) as an isoelectric trap to increase luminous efficiency. The emission wavelength of the light emitting diode is determined by the composition X, and x=0.9 is used for yellow light emission, x=0.75 is used for orange light emission, and x=0.65 is used for red light emission.

発光ダイオードとして用いる時、このＧａＡｓ１−ｘＰ
ｘの結晶は良質のものでなければ非発光センターを発生
させ、高輝度の発光ダイオードは得られない。例えば第
８図のようにＧａＰ基板１２上に一定の組成ｘ＝０．７
５を持つ組成一定層ｌ１を直接エピタキシャル成長させ
ると、格子定数が違うため、格子緩和が不完全となり、
界面ｌ３からミスフィット転位が組成一定層１１内に伝
播し、組成一定層１１の結晶性は著しく悪化する。When used as a light emitting diode, this GaAs1-xP
If the x crystal is not of good quality, it will generate non-light emitting centers and a high brightness light emitting diode will not be obtained. For example, as shown in FIG. 8, a constant composition x=0.7 is formed on the GaP substrate 12.
If the constant composition layer l1 with 5 is directly epitaxially grown, the lattice relaxation will be incomplete due to the difference in lattice constant.
Misfit dislocations propagate into the constant composition layer 11 from the interface l3, and the crystallinity of the constant composition layer 11 deteriorates significantly.

これを回避するために、通常は第９図のようにＧａＰ基
板２３と組成一定層２１の間に組成Ｘを徐々に変化させ
た組成変化層２２を形成してＧａＰ基板２３と組成一定
層２２との格子不整合を緩和させる手法がとられている
。これによって、一定の組成を持つＧａＡｓ＋−ｘＰｘ
組成一定層２１には、ＧａＰ基板２３とエビタキシャル
層の界面２５に生じるミスフィット転位を抑制でき、良
質の結晶性を得ることができる。In order to avoid this, normally a composition change layer 22 in which the composition X is gradually changed is formed between the GaP substrate 23 and the constant composition layer 21 as shown in FIG. Techniques are being taken to alleviate the lattice mismatch between the two. This allows GaAs+-xPx with a certain composition to be
In the constant composition layer 21, misfit dislocations occurring at the interface 25 between the GaP substrate 23 and the epitaxial layer can be suppressed, and good crystallinity can be obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、これまでは第９図の構造のものにおいては、
組成変化層２２における組成変化率は成長方向に対して
、■μｍ当たり０．０２以下とすることが一般的であっ
た。急激な組成変化は組成変化層２２の後に形成する組
成一定層２１の結晶性を低下するばかりでなく、組成一
定層２１の表面にヒルロックなどの表面結晶欠陥を生ず
ることが知られている。By the way, up until now, in the structure shown in Figure 9,
The composition change rate in the composition change layer 22 was generally set to 0.02 or less per μm in the growth direction. It is known that a rapid composition change not only reduces the crystallinity of the constant composition layer 21 formed after the composition change layer 22, but also causes surface crystal defects such as hillocks on the surface of the constant composition layer 21.

しかし、組成変化層２２を介して組成一定層２１を形成
しても組成一定層２１とＧａＰ基板２３との間に格子不
整合は存在し、組成変化層２２による格子不整合の緩和
が不完全なものとなることは避けられないことであった
。組成変化層２２の作或の手法で組成一定層２１の結晶
性は著しく変化し、結果としてこれを用いて作成した発
光ダイオードの輝度（光出力）は大きく変動し、組成変
化層２２の組成変化率を小さくすると組成変化層２２の
層厚の増加が避けられず、原料コストが高くなったり、
また単純には組成一定層２１の結晶性の向上は見られな
かった。However, even if the constant composition layer 21 is formed through the composition change layer 22, a lattice mismatch still exists between the constant composition layer 21 and the GaP substrate 23, and the relaxation of the lattice mismatch by the composition change layer 22 is incomplete. It was inevitable that it would become a thing. The crystallinity of the constant composition layer 21 changes significantly depending on the method used to create the composition change layer 22, and as a result, the brightness (light output) of a light emitting diode created using this changes greatly. If the ratio is decreased, an increase in the layer thickness of the composition-change layer 22 is unavoidable, resulting in an increase in raw material cost,
Furthermore, no improvement in the crystallinity of the constant composition layer 21 was simply observed.

本発明は上記課題を解決するためのもので、ＧａＡｓ＋
−ｘＰｘエピタキシャルウエハの成長において、単結晶
基板と組成一定層Ｇ　ａ　Ａ　ｓ　＋　−ｘ　Ｐ　ｘと
の間に組戒変化層を形成し、該組成変化層に少なくとも
１つの組成一定層と、少なくとも２つ以上の組成変化層
とを形成することにより高輝度の発光ダイオードを得る
ことができるエピタキシャルウェハ及びその製造方法を
提供することを目的とする。The present invention is intended to solve the above-mentioned problems.
-xPx epitaxial wafer growth, a composition change layer is formed between the single crystal substrate and the constant composition layer GaAs + -xPx, and the composition change layer includes at least one constant composition layer and at least It is an object of the present invention to provide an epitaxial wafer and a method for manufacturing the same, which can obtain a high-brightness light emitting diode by forming two or more compositionally changed layers.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、第１図に示すようにＧａＡｓまたはＧａＰ単
結晶基板１上に所定の組成Ｘをもつ良質のＧ　ａ　Ａ　
Ｓ　１−ｘ　Ｐう組成一定層３を成長するため、単結晶
基板１と組成一定層３の間に形成される組成変化層２を
、組成変化層部分２ａ，２ｃ，２ｅと組成一定層部分２
ｂ，２ｄとから形成したもので、組成一定層部分は少な
くとも１層形成してその層厚を１μｍ以上とし、また組
成変化層部分は少なくとも２層以上形成し、そのうちの
少なくとも１層は１μｍ当たりの組成変化率Δｘが、約
０．０２≦Δｘ≦約０．０８ となるように階段状に組成を変化させるようにしたもの
である。In the present invention, as shown in FIG. 1, high-quality GaA having a predetermined composition
In order to grow the constant composition layer 3 containing S1-xP, the composition change layer 2 formed between the single crystal substrate 1 and the constant composition layer 3 is separated from the composition change layer portions 2a, 2c, 2e and the constant composition layer portion. 2
b, 2d, at least one constant composition layer is formed with a layer thickness of 1 μm or more, and the composition variable layer is formed with at least two layers, at least one of which has a thickness of 1 μm or more. The composition is changed stepwise so that the composition change rate Δx satisfies approximately 0.02≦Δx≦0.08.

〔作用〕[Effect]

本発明は、ＧａＡｓまたはＧａＰ単結晶基板上に所定の
組成ｘをもつ良質のＧａＡｓ，−．Ｐ．組成一定層を威
長ずるため、単結晶基板と前記組成一定層の間に形成さ
れる組成変化層を２回以上に分けて組成変化を行い、さ
らにこの組成変化層部分の間に少なくとも所定の厚さを
持った組成一定層部分を１層以上形成させることで、Ｇ
ａＰ基板との格子不整合によって生じた転位を組成変化
層部分で固着させ、かつ組成変化部分の間の組成一定部
分で転位の回復を図ることにより転位を少なくし、所定
の組成Ｘをもつ組成一定な良質の結晶性を得ることが可
能となる。The present invention provides high quality GaAs having a predetermined composition x on a GaAs or GaP single crystal substrate. P. In order to enhance the constant composition layer, the composition change layer formed between the single crystal substrate and the constant composition layer is changed in composition twice or more, and at least a predetermined layer is added between the composition change layer portions. By forming one or more layers of constant composition with a certain thickness, G
Dislocations generated due to lattice mismatch with the aP substrate are fixed in the composition-change layer portion, and dislocations are recovered in the constant-composition portion between the composition-change portions, thereby reducing dislocations and creating a composition with a predetermined composition X. It becomes possible to obtain constant high-quality crystallinity.

〔実施例〕〔Example〕

以下、実施例を説明する。 Examples will be described below.

〔実施例１〕 本発明に従い（尖頭発光波長約６１００ｍ±２　ｎｍ）
橙色発光ダイオード用リン化ひ素ガリウムエピタキシャ
ル膜ＧａＡｓ＋−ｘＰ’＋　　（ｘ″−．０．７５）を
ＧａＰ単結晶基板上に以下の如く形成した。[Example 1] According to the present invention (peak emission wavelength approximately 6100 m±2 nm)
A gallium arsenide phosphide epitaxial film GaAs+-xP'+ (x''-.0.75) for an orange light emitting diode was formed on a GaP single crystal substrate as follows.

まず、ｎ型不純物として硫黄（Ｓ）が５×１０１７原子
個／　ｃｎｆ添加され、結晶学的面方位が〈１００〉面
より０　１　０＞方向に約６゜偏位した面を有するＧａ
Ｐ単結晶基板を用意した。ＧａＰ単結晶基板は、初め約
３７０μｍの厚さであったが有機溶媒による脱脂工程に
引き続いた機械一化学的研磨（Ｍｅｃｈａｎｉｃａｌ−
Ｃｈｅｍｉｃａｌｐｏｌｉｓｈｉｎｇ）処理により、３
００μｍの厚さとなった。First, 5 x 1017 atoms/cnf of sulfur (S) was added as an n-type impurity, and Ga was formed with a crystallographic plane deviated from the <100> plane by about 6° in the 0 1 0> direction.
A P single crystal substrate was prepared. The GaP single-crystal substrate was initially about 370 μm thick, but was subjected to a degreasing process using an organic solvent followed by mechanical-chemical polishing.
By chemical polishing) treatment, 3
The thickness was 00 μm.

次に内径７０ｍｍ，長さ１００ｃｍの水平型石英エビタ
キシャル・リアクター内の所定の場所にそれぞれ前記研
磨済みＧａＰ単結晶基板並びに高純度Ｇａ入り石英ボー
トをセットした。Next, the polished GaP single crystal substrate and the high-purity Ga-containing quartz boat were set at predetermined locations in a horizontal quartz epitaxial reactor with an inner diameter of 70 mm and a length of 100 cm.

エビタキシャル・リアクター内に窒素〈Ｎ２）を導入し
て空気を充分に置換除去し、次にキャリャーガスとして
水素ガス（Ｈ２）を３０００ｍｆ／分導入し、Ｎ２の流
れを止め昇温工程に入った。Nitrogen (N2) was introduced into the epitaxial reactor to sufficiently replace and remove air, then hydrogen gas (H2) was introduced as a carrier gas at 3000 mf/min, the flow of N2 was stopped, and a temperature raising step was started.

前記Ｇａ入り石英ポートセット領域並びにＧａＰ単結晶
基板セット領域の温度がそれぞれ８３０℃並びに９３０
℃に保持されていることを確認後橙色発光ダイオード用
エビタキシャル膜ＧａＡｓ＋−ｘｐｘの気相成長を開始
した。The temperatures of the Ga-containing quartz port set region and the GaP single crystal substrate set region are 830°C and 930°C, respectively.
After confirming that the temperature was maintained at .degree. C., vapor phase growth of an epitaxial film GaAs+-xpx for an orange light emitting diode was started.

気相成長開始時より濃度１０ｐｐｍに水素ガスで希釈し
たｎ型不純物である硫化水素（Ｈ２　Ｓ）を６．　　３
ｍｆ／分導入し、一方■族或分として高純度塩化水素ガ
ス（ＨＣｊ！＞を６３一導入し、Ｇａと反応させること
によりほぼ１００％ＧａＣ１に変換生或させ、他方Ｈ２
で希釈された濃度１０％のＰＨａを２９１−／分導入し
、初めの１０分間は、成長温度（基板温度に相当）を９
３０℃に保持しつつ、ＧａＰ単結晶基板上に第１のＧａ
Ｐエピタヰシャル層を形成した。6. Hydrogen sulfide (H2S), an n-type impurity, diluted with hydrogen gas to a concentration of 10 ppm from the start of vapor phase growth. 3
mf/min, and on the other hand, high purity hydrogen chloride gas (HCj!) was introduced as a part of the group III, and was converted to almost 100% GaCl by reacting with Ga, and on the other hand, H2
PHa with a concentration of 10% diluted with
A first Ga layer was deposited on the GaP single crystal substrate while maintaining the temperature at 30°C.
A P epitaxial layer was formed.

第２の組戒変化層は以下の通りに形成した。The second group precept change layer was formed as follows.

次の５分間は、成長温度を徐々に９３０℃から９１８℃
まで下げ、同時にＡ　ｓ　Ｈ　ｓをＯｒｎＩｌ／分から
２４．３ｒｄ／分に変化させた。このとき形成した層を
第２−１層とする。For the next 5 minutes, the growth temperature was gradually increased from 930°C to 918°C.
At the same time, A s H s was changed from OrnIl/min to 24.3rd/min. The layer formed at this time is referred to as the 2-1 layer.

次の２０分間は成長温度を９１８℃一定、ＡｓＨ３の流
量を２４、３−／分一定とした。この時形成した層を第
２−２層とする。For the next 20 minutes, the growth temperature was kept constant at 918 DEG C. and the AsH3 flow rate was kept constant at 24.3-/min. The layer formed at this time will be referred to as the 2-2nd layer.

次の５分間は成長温度を徐々に９１８℃から９０５℃ま
で下げ、同時にＡ　ｓ　Ｈ　ｓの流量を２４．３ｗｄｌ
／分から４８．５ｍＮ／分変化させた。この時形成した
層を第２−３層とする。During the next 5 minutes, the growth temperature was gradually lowered from 918°C to 905°C, and at the same time the flow rate of A s H s was increased to 24.3 wdl.
/min to 48.5mN/min. The layer formed at this time will be referred to as the 2nd-3rd layer.

次の２０分間は成長温度を９０５℃一定、ＡｓＨ，の流
量を４８．５ｒｎｌ／分一定とした。この時形成した層
を第２−４層とする。For the next 20 minutes, the growth temperature was kept constant at 905° C., and the flow rate of AsH was kept constant at 48.5 rnl/min. The layer formed at this time will be referred to as the 2nd-4th layer.

次の５分間は成長温度を徐々に９０５℃から８９３℃ま
で下げ、同時にＡ　ｓ　Ｈ　ａの流量を４８。During the next 5 minutes, the growth temperature was gradually lowered from 905 °C to 893 °C, and at the same time the flow rate of AsH a was increased to 48 °C.

５ｍｌ！／分から７２．８−／分に変化させた。この時
形成した層を第２−５層とする。5ml! /min to 72.8-/min. The layer formed at this time will be referred to as layer 2-5.

次の２０分間は成長温度を８９３℃一定、ＡｓＨ３の流
量を７２．８ｔｒｆ／分一定とした。この時形成した層
を第２−６層とする。For the next 20 minutes, the growth temperature was kept constant at 893° C. and the flow rate of AsH3 was kept constant at 72.8 trf/min. The layer formed at this time will be referred to as layer 2-6.

次の５分間は成長温度を８９３℃から８８０℃まで下げ
、同時にＡＳＨ３の流量を７２．８ｍｆ／分から９７ｍ
ｊ！／分に変化させた。この時形成した層を第２−７層
とする。During the next 5 minutes, the growth temperature was lowered from 893°C to 880°C, while the ASH3 flow rate was increased from 72.8 mf/min to 97 mf/min.
j! / minute. The layer formed at this time will be referred to as layer 2-7.

このようにして第２−Ｌ　　２−２、２−３、２一４、
２−５、２−６、２−７層からなる第２の層を形成した
。In this way, the second-L 2-2, 2-3, 2-4,
A second layer consisting of layers 2-5, 2-6, and 2-7 was formed.

次の３０分間は各ガスの流量を変えることなく、すなわ
ちＨ２、Ｈ２Ｓ，ＨＣｊ２ＳＰＨ３並びにＡｓ　Ｈ　３
をそれぞれ３０００ｒｄ／分、６．　　３ｍ！！／分、
６３−／分、２９１ｍｌ２／分並びに９７−／分導入し
て第３のＧａΔ８１−＞ＩＰＸエビタヰシャル層を成長
させた。For the next 30 minutes, the flow rates of each gas remained unchanged, i.e. H2, H2S, HCj2SPH3 and As H3.
3000rd/min, respectively, 6. 3m! ! / minute,
A third GaΔ81−>IPX epitaxial layer was grown at 63 −/min, 291 ml 2 /min, and 97 −/min.

次ノ最終の６０分間は、第３のエビタキシャル層形成条
件に加え、新たに高純度ＮＨ．ガスを３０５ｒｎｐ．／
分導入し、窒素（Ｎ）をアイソ・エレクトロニックトラ
ップとしてドープした第４　Ｇ　ａ　ＡＳ　Ｉ　−ｗ　
Ｐ　Ｘエビタキシャル層を形成し、エビタキシャル多層
膜の全形成工程を終了した。During the next and final 60 minutes, in addition to the third epitaxial layer formation conditions, high purity NH. Gas at 305rnp. /
4th Ga AS I-w doped with nitrogen (N) as an isoelectronic trap.
A PX epitaxial layer was formed to complete the entire formation process of the epitaxial multilayer film.

取出し後のエビタキシャル・ウエハの表面状態は極めて
良好で突起物その他の表面欠陥は見られなかった。The surface condition of the epitaxial wafer after removal was extremely good, with no protrusions or other surface defects observed.

以上の如くして得られたエビタキシャル多層膜に対し各
種物性測定並びに解析を実施した結果、表１の結果を得
た。Various physical property measurements and analyzes were performed on the epitaxial multilayer film obtained as described above, and the results shown in Table 1 were obtained.

表１において、第２層の中の第２−１、２−３、 ｌ１ ２−５、２−７層は組成変化率は０．０５４、０．０４
７、０．０３８、０．０３２（組成／μｍ）であり、第
２−２、２−４、２−６層の層厚は５．２、５．８、６
．３μｍであった。このときの組成の断面構造は第２図
に示すようなものである。In Table 1, the composition change rates of layers 2-1, 2-3, l1 2-5, and 2-7 in the second layer are 0.054 and 0.04.
7, 0.038, 0.032 (composition/μm), and the layer thicknesses of the 2-2, 2-4, and 2-6 layers are 5.2, 5.8, 6
．． It was 3 μm. The cross-sectional structure of the composition at this time is as shown in FIG.

図において横軸は基板とエビタキシャル層界面からの距
離、縦軸は組成Ｘを表して５）る。なお、組ｅｘはＸ線
マイクロアナライザによって特性Ｘ線を測定し、ＺＡＦ
補正法によって求めたものである。In the figure, the horizontal axis represents the distance from the interface between the substrate and the epitaxial layer, and the vertical axis represents the composition X5). In addition, for group ex, characteristic X-rays were measured using an X-ray microanalyzer, and ZAF
This was determined using the correction method.

次に本実施例により得られたエビタキシャル膜を有する
エビタキシャル・ウエハを用い、橙色発光ダイオードを
作成し、輝度値（光出力）を実測した。Next, an orange light emitting diode was created using the epitaxial wafer having the epitaxial film obtained in this example, and the brightness value (light output) was actually measured.

即ち、該エビタキシャル・ウエハを、Ｐ型不純物として
ＺｎＡｓ２２５ｍｇと共に高純度石英アンプル中に真空
封入し、温度７２０℃で不純物熱拡散を行って得られた
Ｐ−ｎ接合深さは、表面より４．４μｍであった。That is, the epitaxial wafer was vacuum-sealed in a high-purity quartz ampoule with 225 mg of ZnAs as a P-type impurity, and the impurity was thermally diffused at a temperature of 720°C. The P-n junction depth obtained was 4 mm from the surface. It was 4 μm.

以上の如くして得られたエビタキシャル・ウ工１２ ハを、裏面（基板）研磨工程、電極形成工程、ワイヤー
・ボンディング工程等一連のデバイス製作ラインに投入
し、橙色発光ダイオード・チップを作威した。The epitaxial substrate 12 obtained as described above is put into a series of device manufacturing lines including a backside (substrate) polishing process, an electrode forming process, and a wire bonding process to produce an orange light emitting diode chip. did.

次に該発光ダイオード・チップ（チップ寸法及びＰ　／
　ｎ接合寸法は、共に５００μｍＸ５００μｍ角）に対
し直流電流密度２ＯＡ／ｃｎｌの電流を通電し、該チッ
プにエポキシ樹脂コート無しの条件下で輝度値（光出力
）を測定した。その結果、尖頭発波長６１０ｎｍ±２ｎ
ｍ，輝度値が４１４０〜４３２０Ｆｔ−Ｌ平均４２６０
Ｆｔ−Ｌであった。Next, the light emitting diode chip (chip size and P/
A current with a DC current density of 2 OA/cnl was applied to the n-junction (both dimensions are 500 μm x 500 μm square), and the brightness value (light output) was measured under the condition that the chip was not coated with an epoxy resin. As a result, the peak emission wavelength is 610nm±2n
m, brightness value is 4140-4320Ft-L average 4260
It was Ft-L.

〔実施例２〕 第２−５層、第２−７層の成長時間を１５分とした以外
は〔実施例１］と全く同様にしてエピタキシャルウェハ
を作或し、同様の方法で物性測定及び解析を実施したと
ころ表２の結果が得られた。[Example 2] An epitaxial wafer was prepared in the same manner as [Example 1] except that the growth time of the 2-5th layer and the 2-7th layer was changed to 15 minutes, and the physical properties were measured and carried out in the same manner. When the analysis was performed, the results shown in Table 2 were obtained.

表２ （実施例２のデータ） このときの組成の断面構造は第３図に示すようなもので
ある。Table 2 (Data of Example 2) The cross-sectional structure of the composition at this time is as shown in FIG.

次に、〔実施例１〕と全く同様にしてダイオードチップ
を作或して同一条件で測定したところ、尖頭発光波長６
１０ｎｍ±２ｎｍ、輝度値が３９４０〜４４２０Ｆｔ−
Ｌ，平均４１９０Ｆｔ−Ｌであった。Next, a diode chip was manufactured in exactly the same manner as in [Example 1] and measured under the same conditions, and the peak emission wavelength was 6.
10nm±2nm, brightness value 3940~4420Ft-
L, average 4190 Ft-L.

〔比較例１〕 本発明に従い（尖頭発光波長約６１０ｎｍ±２ｎｍ）橙
色発光ダイオード用リン化ひ化ガリウムエピタキシャル
膜ＧａＡｓ１−，Ｐ．（ｘ！＝＝０．７５〉を、ＧａＰ
単結晶基板上に辺下の如くして形成した。[Comparative Example 1] According to the present invention, a gallium arsenide phosphide epitaxial film GaAs1-,P. (x!==0.75〉, GaP
It was formed on a single crystal substrate as shown below.

まず、ｎ型不純物として硫黄（Ｓ）が５×１０１７原子
個／ｃＩＩ１添加され、結晶学的面方位が＜１００〉面
より＜１　１　０＞方向に約６゜偏位した面を有するＧ
ａＰ単結晶基板を用意した。ＧａＰ単結晶基板は、初め
約３７０μｍの厚さであったが有機溶媒による脱脂工程
に引き続いた機械一化学的研磨処理により、３００μｍ
の厚さとなった。First, 5 x 1017 atoms/cII1 of sulfur (S) is added as an n-type impurity, and a G
An aP single crystal substrate was prepared. The GaP single crystal substrate was initially about 370 μm thick, but was reduced to 300 μm by mechanical and chemical polishing following a degreasing process using an organic solvent.
The thickness became .

次に内径７０ｍｍ，長さ１００ｃｍの水平型石英エビタ
キシャル・リアクター内の所定の場所にそれぞれ前記研
磨済みＧａＰ単結晶基板並びに高純度Ｇａ入り石英ボー
トをセットした。Next, the polished GaP single crystal substrate and the high-purity Ga-containing quartz boat were set at predetermined locations in a horizontal quartz epitaxial reactor with an inner diameter of 70 mm and a length of 100 cm.

エビタキシャル・リアクター内に窒素（Ｎ２）を導入し
て空気を充分に置換除去し、次にキャリャーガスとして
水素ガス（Ｈ２）を３０００−／分導入し、Ｎ２の流れ
を止め昇温工程に入った。Nitrogen (N2) was introduced into the epitaxial reactor to sufficiently replace and remove air, then hydrogen gas (H2) was introduced as a carrier gas at a rate of 3000/min, and the flow of N2 was stopped and the temperature raising process started. .

前記Ｇａ入り石英ポートセット領域並びにＧａ１５ Ｐ単結晶基板セット領域の温度がそれぞれ８３０℃並び
に９３０℃に保持されていることを確認後、橙色発光ダ
イオード用エビタキシャル膜ＧａＡｓｐＭの気相成長を
開始した。After confirming that the temperatures of the Ga-containing quartz port set region and the Ga15P single crystal substrate set region were maintained at 830° C. and 930° C., respectively, vapor phase growth of GaAspM, an epitaxial film for an orange light emitting diode, was started.

気相成長開始時より濃度１０ｐｐｍに水素ガスで希釈し
たｎ型不純物である硫化水素（Ｈ２Ｓ）を６．３ｄ／分
導入し、一方■族或分として高純度塩化水素ガス（Ｈ．
Ｃ　．１！　）を６３−／分導入し、Ｇａと反応させる
ことによりほぼ１００％ＧａＣｌに変換生威させ、他方
Ｈ２で希釈された濃度ｌＯ％のＰＨ．を２９１ｍｅ／分
導入し、初めの１０分間は、成長温度（基板温度に相当
）を９３０℃に保持しつつ、ＧａＰ単結晶基板上に第１
のＧａＰエピタキシャル層を形成した。From the start of vapor phase growth, hydrogen sulfide (H2S), an n-type impurity diluted with hydrogen gas to a concentration of 10 ppm, was introduced at 6.3 d/min, while high-purity hydrogen chloride gas (H2S) was introduced as a group III component.
C. 1! ) at a concentration of 10% diluted with H2 and converted to almost 100% GaCl by reaction with Ga. was introduced at 291 me/min, and for the first 10 minutes, the first layer was deposited on the GaP single crystal substrate while maintaining the growth temperature (corresponding to the substrate temperature) at 930°C.
A GaP epitaxial layer was formed.

次の１００分間で成長温度を徐々に８８０℃まで下げ、
同時にＡ　ｓ　Ｈ　３をＯｄ／分から９７ｍｉ！／分に
変化させて第２のエビタキシャル層を形成した。Over the next 100 minutes, the growth temperature was gradually lowered to 880°C.
At the same time, A s H 3 from Od/min to 97mi! /min to form a second epitaxial layer.

次の３０分間は、各ガスの流量を変えることなく、即ち
Ｈ２、Ｈ２ＳＳＨＣＣ　ＰＨ３並びにＡ１６ ｓＨ３をそれぞれ３０００ａｌｌ！／分、６．３７／分
、６３−／分、２９１ｍｆｆ／分並びに９７−／分導入
して第３のＧａＡｓ，−．Ｐエエピタヰシャル層を成長
させた。For the next 30 minutes, the flow rates of each gas remained unchanged, i.e. 3000all each of H2, H2SSHCC PH3 and A16 sH3! /min, 6.37/min, 63-/min, 291 mff/min and 97-/min to introduce the third GaAs,-. A P epitaxial layer was grown.

次の最終の６０分間は、第３のエビタキシャル層形成条
件に加え、新たに高純度ＮＨ．ガスを３０５−／分導入
し、窒素（Ｎ）をアイソ・エレクトロニックトラップと
してドープした第４のＧａＡ　Ｓ　＋　−ｗ　Ｐ　）Ｉ
エビタキシャル層を形成し、エビタキシャル多層膜の全
形成工程を終了した。During the next and final 60 minutes, in addition to the third epitaxial layer formation conditions, high-purity NH. A fourth GaA S + -w P )I doped with nitrogen (N) as an isoelectronic trap with gas introduced at 305 −/min
An epitaxial layer was formed, and the entire formation process of the epitaxial multilayer film was completed.

取出し後のエビタキシャル・ウエハの表面状態は極めて
良好で突起物その他の表面欠陥は見られなかった。The surface condition of the epitaxial wafer after removal was extremely good, with no protrusions or other surface defects observed.

以上の如くして得られたエビタキシャル多層膜に対し各
種物性測定並びに解析を実施した結果、表３の結果を得
た。Various physical property measurements and analyzes were performed on the epitaxial multilayer film obtained as described above, and the results shown in Table 3 were obtained.

（以下余白〉 表３ （比較例１のデータ） 表３において、第２層の組成＊■、＊■、＊■は、それ
ぞれＧａＰ基板とエビ層界面から９μｍ１１５μｍ１２
０μｍの３点において測定したものである。表３から分
かるように、第２層における組成変化率は０．０２ＪＪ
．下であり、また層厚は２２．４μｍであった。このと
きの組成の断面構造を第４図に示す。(The following is a blank space) Table 3 (Data of Comparative Example 1) In Table 3, the composition of the second layer *■, *■, *■ is 9μm115μm12 from the GaP substrate and shrimp layer interface, respectively.
Measurements were taken at three points of 0 μm. As can be seen from Table 3, the composition change rate in the second layer is 0.02JJ
．． The layer thickness was 22.4 μm. The cross-sectional structure of the composition at this time is shown in FIG.

次に比較例ｌにより得られたエビタキシャル膜を有した
エビタキシャル・ウェハーを用い、橙色発光ダイオード
を作或し、輝度値（光出力）を実測した。Next, an orange light emitting diode was fabricated using the epitaxial wafer having the epitaxial film obtained in Comparative Example 1, and the brightness value (light output) was actually measured.

即ち、該エビタキシャル・ウエハを、Ｐ型不純物として
ＺＴＩＡ８２　２５■と共に高純度石英アンプル中に真
空封入し、温度７２０℃で不純物熱拡散を行い得られた
Ｐ−ｎ接合深さは、表面より４．５μｍであった。That is, the epitaxial wafer was vacuum-sealed in a high-purity quartz ampoule with ZTIA82 25■ as a P-type impurity, and the impurity was thermally diffused at a temperature of 720°C. The resulting P-n junction depth was 4 mm from the surface. It was .5 μm.

以上の如くして得られたエビタキシャル・ウエハを、裏
面（基板）研磨工程、電極形成工程、ワイヤー・ボンデ
ィング工程等一連のデバイス製作ラインに投入し、橙色
発光ダイオード・チップを作或し、次に該発光ダイオー
ド・チップ（チップ寸法及びＰ　／　ｎ接合寸法は、共
に５００μｒｌｘ５００μｍ角）に対し直流電流密度２
０Ａ／ｃｌの電流を通電し、該チップにエポキシ樹脂コ
ート無しの条件下で輝度値（光出力〉を測定した。その
結果、尖頭発波長６１０ｎｍ±２ｎｍ，輝度値が３３３
０〜３５２ＱＦｔ−Ｌ平均３４１ＱＦｔ−Ｌであった。The epitaxial wafer obtained as described above is put into a device manufacturing line that includes a backside (substrate) polishing process, an electrode forming process, and a wire bonding process to produce an orange light emitting diode chip. A DC current density of 2 is applied to the light emitting diode chip (chip dimensions and P/n junction dimensions are both 500 μrl x 500 μm square).
A current of 0 A/cl was applied and the brightness value (light output) was measured under the condition that the chip was not coated with epoxy resin.As a result, the peak emission wavelength was 610 nm±2 nm, and the brightness value was 333.
The average was 341 QFt-L from 0 to 352 QFt-L.

〔実施例３〕 単結晶基板として、直径５０ｍｍの円形で、厚さ１９ が３５０μｍのＧａＡｓ単結晶基板を用いた。この基板
の表面は、鏡面に研磨されており、その面方位は、（０
０１＞面から０　　１　　０＞方向へ２，０゜傾いた面
であった。このＧａＡｓ単結晶基板は、シリコンがドー
プされており、ｎ型キャリア濃度が７．　　Ｏ　Ｘ　Ｉ
　Ｑ　”ｃｍ−３であった。[Example 3] As a single crystal substrate, a circular GaAs single crystal substrate with a diameter of 50 mm and a thickness of 350 μm was used. The surface of this substrate is mirror-polished, and its surface orientation is (0
The surface was inclined by 2.0 degrees from the 01> direction toward the 0 1 0> direction. This GaAs single crystal substrate is doped with silicon and has an n-type carrier concentration of 7. OXI
Q" cm-3.

上記単結晶基板を、内径７０ｍｍ、長さｌ０００ｍｍの
石英製水平型エビタキシャルリアクター内に設置した。The single-crystal substrate was placed in a horizontal quartz epitaxial reactor with an inner diameter of 70 mm and a length of 1000 mm.

続いて、金属ガリウムを収容した石英製ボートを上記り
了クター内に設置した。Next, a quartz boat containing metallic gallium was placed inside the tank.

リアクターにアルゴンを流して、空気を置換した後、ア
ルゴンの供給を停止して、高純度の水素ガスを２８００
ｒｄ／分の流量で上記リアクターに流しながら昇温した
。After flowing argon into the reactor to replace the air, the argon supply was stopped and high-purity hydrogen gas was
The temperature was raised while flowing through the reactor at a flow rate of rd/min.

上記ガリウム入り石英ボート設置部の温度が８３０℃、
また、基板設置部の温度が７５０℃に達した後、その温
度を保ちながら、塩化水素ガスを９０ｍｌ！／分の流量
で２分間、上記ガリウム入り石英ボートよりも下流で２
分間、上記ガリウム入り石英ボートよりも下流側から、
リアクターに供給２０ してＧａＡｓ単結晶基板の表面をエッチングした。The temperature of the installation part of the gallium-containing quartz boat is 830℃,
Also, after the temperature of the board installation area reaches 750℃, while maintaining that temperature, add 90ml of hydrogen chloride gas! /min for 2 minutes downstream of the gallium-containing quartz boat.
minutes, from the downstream side of the quartz boat containing gallium,
The surface of the GaAs single crystal substrate was etched by supplying it to the reactor.

上記塩化水素ガスの供給を停止した後、ジェチルテルル
を１０体積ｐｐｍ含有する水素ガスを１０一／分の流量
でリアクターに供給した。After stopping the supply of the hydrogen chloride gas, hydrogen gas containing 10 volume ppm of diethyl tellurium was supplied to the reactor at a flow rate of 10/min.

続いて、塩化水素ガスを、２０、２−／分の流量で、リ
アクター内の上記ガリウム入り石英ボート内のガリウム
の表面に触れるようにリアクター内に吹き出させた。続
いて、アルシン（ＡＳＨ３）及び、ホスフィン（ＰＨ．
）を、以下の通り供給して第１層である混晶率変化層を
形成した。Subsequently, hydrogen chloride gas was blown into the reactor at a flow rate of 20.2-min so as to touch the surface of the gallium in the gallium-containing quartz boat in the reactor. Subsequently, arsine (ASH3) and phosphine (PH.
) was supplied as follows to form a mixed crystal ratio change layer as the first layer.

ＰＨ３、ＡｓＨ！ｌともＨ２で希釈された濃度１０％の
ガスを用いた。初めにＡ　ｓ　Ｈ　ｓを３７６一／分の
流量でリアクターに供給し、９分間に徐々に３５３−／
分の流量まで減少させた。同時にＰＨ３を０−／分から
２２．４−／分の流量まで増加させて、第１−１層を形
成した。PH3, AsH! In both cases, a gas with a concentration of 10% diluted with H2 was used. Initially, A s H s was supplied to the reactor at a flow rate of 376 −/min, and gradually at a flow rate of 353 −/min over 9 minutes.
The flow rate was reduced to 1 minute. At the same time, PH3 was increased from 0-/min to a flow rate of 22.4-/min to form layer 1-1.

次の２０分間はＡｓＨ，、ＰＨ３の流量をそれぞれ３４
５ｍｆ／分、６７．２ｒｎＩ！／分一定として第１−２
層を形成した。For the next 20 minutes, the flow rates of AsH, PH3 were increased to 34°C, respectively.
5mf/min, 67.2rnI! /minute constant 1-2
formed a layer.

次の９分間はＡｓＨ３の流量を３４５ｒｄ／分から３２
９ｍｊ２／分に徐々に変化させｔこ。同時にＰＨ，の流
量を２２．４ｍｅ／分から４４．８−／分に徐々に変化
させて第１−３層を形成した。For the next 9 minutes, the AsH3 flow rate was increased to 345rd/min.
Gradually change the speed to 9mj2/min. At the same time, the flow rate of PH was gradually changed from 22.4 me/min to 44.8 me/min to form the 1st to 3rd layers.

次の２０分間はＡＳＨ３　、ＰＨ．＋の流量をそれぞれ
３２９ｒｄ／分、４４．８ｍｅ／分一定として第１−４
層を形戒した。For the next 20 minutes, ASH3, PH. 1-4 with constant flow rates of 329rd/min and 44.8me/min, respectively.
The layers were formalized.

次の９分間はＡＳＨ３の流量を３２９−／分から３０６
ｄ／分に徐々に変化させた。同時にＰＨ３の流量を４４
．８ｍｌ／分から８９．６ｍｌ．／分に変化させて、第
１−５層を形成した。For the next 9 minutes, increase the ASH3 flow rate to 329-/min to 306-min.
d/min. At the same time, increase the flow rate of PH3 to 44
．． 8ml/min to 89.6ml. /min to form the 1st to 5th layers.

このように第１−１、１−２、１−３、１−４、１−５
層から或る第１層を混晶率変化層として形成をした。In this way, 1-1, 1-2, 1-3, 1-4, 1-5
A certain first layer of the layers was formed as a mixed crystal ratio changing layer.

混晶率変化層の形成を開始した時点から、６０分経過後
、アルシンを含有する水素ガスの流量を２８２ｄ／分、
ホスフィンを含有する水素ガスの流量を８９．６−／分
、及びジエチルテルルを含有する水素ガスの流量を１１
．２ｍｆ／分に保って、６０分間混晶率一定層を形成し
た。続いて、リアクターの温度を降下させて、エビタキ
シャル・ウエハの製造を終了した。After 60 minutes from the time when the formation of the mixed crystal ratio change layer started, the flow rate of hydrogen gas containing arsine was increased to 282 d/min.
The flow rate of hydrogen gas containing phosphine was 89.6-/min, and the flow rate of hydrogen gas containing diethyl tellurium was 11-/min.
．． A constant mixed crystal ratio layer was formed for 60 minutes while maintaining the rate at 2 mf/min. Subsequently, the temperature of the reactor was lowered to complete the production of the epitaxial wafer.

以上の如くして得られたエビタキシャル多層膜に対して
各種物性測定並びに解析を実施した結果、表４が得られ
た。Table 4 was obtained as a result of various physical property measurements and analyzes performed on the epitaxial multilayer film obtained as described above.

このときの組成の断面構造は第５図に示す通りである。The cross-sectional structure of the composition at this time is as shown in FIG.

次に本実施例により得られたエビタキシャル膜を有した
エビタキシャル・ウェハーを用い、赤色発光ダイオード
を作威し、輝度値（光出力）を実測した。Next, a red light emitting diode was produced using the epitaxial wafer having the epitaxial film obtained in this example, and the brightness value (light output) was actually measured.

即ち、該エビタキシャル・ウェハーを、Ｐ型不純物とし
てＺｎＡｓ２２５ｍｇと共に高純度石英ア２３ ンプル中に真空封入し、温度７２０℃で不純物熱拡散を
行って得られたＰ−ｎ接合深さは、表面より３．８μｍ
であった。That is, the epitaxial wafer was vacuum-sealed in a high-purity quartz ample with 225 mg of ZnAs as a P-type impurity, and the impurity was thermally diffused at a temperature of 720°C. 3.8μm
Met.

以上の如くして得られたエビタキシャル・ウエハーを、
裏面（基板）研磨工程、電極形成工程、ワイヤー・ボン
ディング工程等一連のデバイス製作ラインに投入し、赤
色発光ダイオード・チップを作或した。The epitaxial wafer obtained as above,
A red light emitting diode chip was created by putting it into a series of device production lines, including a backside (substrate) polishing process, electrode forming process, and wire bonding process.

次に該発光ダイオード・チップ（チップ寸法及びＰ／ｎ
接合寸法は、共に５００μｍＸ５００μｍ角）に対し直
流電流密度２ＯＡ／ｃｕｔの電流を通電し、該チップに
エポキシ樹脂コート無しの条件下で輝度値（光出力）を
測定した。その結果、尖頭発波長６６０ｎｍ±２ｎｍ，
輝度値が１３９０Ｆｔ−Ｌ−１５２０Ｆｔ−Ｌ，平均１
４８０Ｆｔ・Ｌであった。Next, the light emitting diode chip (chip size and P/n
A current with a DC current density of 2 OA/cut was applied to the bonding dimensions (both 500 μm x 500 μm square), and the brightness value (light output) was measured under the condition that the chip was not coated with an epoxy resin. As a result, the peak emission wavelength was 660nm±2nm,
Brightness value is 1390Ft-L-1520Ft-L, average 1
It was 480Ft・L.

〔実施例４〕 第１−５層の成長時間を２０分間とした以外は〔実施例
３〕と全く同様にしてエピタキシャルウェハを作或し、
同様の方法で物性測定及び解析を２４ 実施したところ表５が得られた。[Example 4] An epitaxial wafer was produced in the same manner as [Example 3] except that the growth time of the first to fifth layers was changed to 20 minutes.
When physical properties were measured and analyzed using the same method, Table 5 was obtained.

表５（実施例４のデータ） このときの組成の断面構造は第６図に示す通りである。Table 5 (data of Example 4) The cross-sectional structure of the composition at this time is as shown in FIG.

次に、〔実施例３〕と全く同様にしてダイオードチップ
を作或して同一条件で測定したところ、尖頭発波長６６
０ｎｍ±２ｎｍ，輝度値が１４１０Ｆｔ−Ｌ　〜１５０
０Ｆｔ−Ｌ，平均１４６０Ｆ１−］，であった。Next, a diode chip was manufactured in exactly the same manner as in [Example 3] and measured under the same conditions, and the peak emission wavelength was 66.
0nm±2nm, brightness value 1410Ft-L ~150
0Ft-L, average 1460F1-].

〔比較例２〕 単結晶基板として、直径５０ｍｍの円形で、厚さが３５
０μｍのＧａＡｓ単結晶基板を用いた。この基板の表面
は、鏡面に研摩されており、その面方位は、（００１）
面から＜１　　１　　０＞方向へ２．０゜傾いた面であ
った。このＧａＡｓｊｌ！結晶基板はシリコンがドープ
されており、ｎ型キャリア濃度が７．　　Ｏ　ｘ．ｌ　
Ｏ　Ｉ７ｃｍ−３のものであった。[Comparative Example 2] A circular single crystal substrate with a diameter of 50 mm and a thickness of 35 mm was used.
A 0 μm GaAs single crystal substrate was used. The surface of this substrate is polished to a mirror surface, and its plane orientation is (001).
The surface was inclined by 2.0° from the plane in the <1 1 0> direction. This GaAsjl! The crystal substrate is doped with silicon and has an n-type carrier concentration of 7. Ox. l
It was of OI7cm-3.

上記単結晶基板を、内径７０ｍ＋ｎ長さ１０００ａｕｎ
の石英製水平型エビタキシャルリアクター内に設置した
。続いて、金属ガリウムを収容した石英製ボートを上記
リアクター内に設置した。The above single crystal substrate has an inner diameter of 70 m + n length of 1000 aun.
The system was installed in a horizontal quartz epitaxial reactor. Subsequently, a quartz boat containing metallic gallium was placed in the reactor.

リアクターにアルゴンを流して、空気を置換した後、ア
ルゴンの供給を停止して、高純度の水素ガスを２８００
−／分の流量で上記リアクターに流しながら昇温した。After flowing argon into the reactor to replace the air, the argon supply was stopped and high-purity hydrogen gas was
The temperature was raised while flowing through the reactor at a flow rate of -/min.

上記ガリウム入り石英ボート設置部の温度が８３０℃、
また、基板設置部の温度が７５０℃に達した後、その温
度を保ちながら、塩化水素ガスを９０−／分の流量で２
分間、上記ガリウム入り石英ボートよりも下流側から、
リアクターに供給して、ＧａＡｓ単結晶基板の表面をエ
ッチングした。The temperature of the installation part of the gallium-containing quartz boat is 830℃,
In addition, after the temperature of the board installation area reached 750°C, while maintaining that temperature, hydrogen chloride gas was added at a flow rate of 90°C/min.
minutes, from the downstream side of the quartz boat containing gallium,
It was supplied to a reactor to etch the surface of a GaAs single crystal substrate.

上記塩化水素ガスの供給を停止した後、ジエチルテルル
を１０体積ｐｐｍ含有する水素ガスをｌ〇一／分の流量
でリアクターに供給した。After stopping the supply of hydrogen chloride gas, hydrogen gas containing 10 volume ppm of diethyl tellurium was supplied to the reactor at a flow rate of 101/min.

続いて、塩化水素ガスを、２０．２ｍｌ！／分の流量で
、リアクター内の上記ガリウム入り石英ボート内のガリ
ウムの表面に触れるように、リアクター内に吹き出させ
た。続いて、アルシン（ΔｓＨ３）及び、ホスフィン（
ＰＨ．）を、以下の通り、供給して、混晶率変化層を形
成した。すなわち、アルシンを１０体積％含有する水素
ガスを、３７６ｒｎｌ．／分の流量でリアクターに供給
し、６２分間に、２８２ｄ／分まで流量を徐々に減少さ
せた。Next, add 20.2ml of hydrogen chloride gas! The gallium was blown into the reactor at a flow rate of /min so as to touch the surface of the gallium in the gallium-containing quartz boat in the reactor. Subsequently, arsine (ΔsH3) and phosphine (
P.H. ) was supplied as follows to form a mixed crystal ratio change layer. That is, hydrogen gas containing 10% by volume of arsine was heated to 376rnl. The reactor was fed at a flow rate of 282 d/min over a period of 62 minutes.

同時に、ホスフィンをｌＯ体積％含有する水素ガスを、
０−／分の流量で供給し、６０分間に、８９．６ｒｎＩ
！／分まで流量を徐々に増加させた。At the same time, hydrogen gas containing 10% by volume of phosphine,
Delivered at a flow rate of 0-/min, over 60 minutes, 89.6rnI
! The flow rate was gradually increased up to 1/min.

混晶率変化層の形成を開始した時点から、６０分経過後
、アルシンを含有する水素ガスの流量を２８２−／分、
ホスフィンを含有する水素ガスの流量を８９．６ｍｆ／
分、及び、ジエチルテルルを含有する水素ガスの流量を
１１．２ｄ／分に保って、６０分間混晶率一定層を形成
した。続いて、２７ リアクターの温度を降下させて、エビタキシャルウェハ
の製造を終了した。After 60 minutes from the time when the formation of the mixed crystal ratio change layer started, the flow rate of hydrogen gas containing arsine was increased to 282-/min.
The flow rate of hydrogen gas containing phosphine was set to 89.6 mf/
and the flow rate of hydrogen gas containing diethyl tellurium were maintained at 11.2 d/min to form a constant mixed crystal ratio layer for 60 minutes. Subsequently, the temperature of the 27 reactor was lowered to complete the production of the epitaxial wafer.

以上の如くして得られたエビタキシャル多層膜に対して
各種物性定数解析を実施した結果表４が得られた。Table 4 was obtained as a result of various physical property constant analyzes performed on the epitaxial multilayer film obtained as described above.

表４において＊■、＊■は、それぞれ基板とエビ層界面
から１０μｍ、２０μｍの位置における値である。この
表から分かるように第１層である組成変化層の組成変化
率はすべて、０．０２（組成／μｍ）以下であった。こ
のときの組筬の断面構造は第７図に示す通りである。In Table 4, *■ and *■ are values at positions 10 μm and 20 μm from the substrate and shrimp layer interface, respectively. As can be seen from this table, the composition change rate of the composition change layer, which is the first layer, was all 0.02 (composition/μm) or less. The cross-sectional structure of the assembled reed at this time is as shown in FIG.

次に本比較例により得られたエビタキシャル膜を有した
エビタキシャル・ウェハーを用い、赤色２８ 発光ダイオードを作或し、輝度値（光出力）を実測した
。Next, using the epitaxial wafer having the epitaxial film obtained in this comparative example, 28 red light emitting diodes were fabricated, and the brightness value (light output) was actually measured.

即ち、該エビタキシャル・ウェハーを、Ｐ型不純物とし
てＺｎＡｓ２２５ｍｇと共に高純度石英アンプル中に真
空封入し、温度７２０℃で不純物熱拡散を行って得られ
たＰ−ｎ接合深さは、表面より３．９μｍであった。That is, the epitaxial wafer was vacuum-sealed in a high-purity quartz ampoule with 225 mg of ZnAs as a P-type impurity, and the impurity was thermally diffused at a temperature of 720° C. The P-n junction depth obtained was 3 mm from the surface. It was 9 μm.

以上の如くして得られたエビタキシャル・ウエハーを、
裏面（基板）研磨工程、電極形成工程、ワイヤー・ボン
ディング工程等一連のデバイス製作ラインに投入し、赤
色発光ダイオード・チップを作或し、次に該発光ダイ才
一ド・チップ（チップ寸法及びＰ　／　ｎ接合寸法は、
共に５００μ×５００μ角）に対し直流電流密度２ＯＡ
／ｃｎｆの電流を通電し、該チップにエボキシ樹脂コー
ト無しの条件下で、輝度値（光出力）を測定した。その
結果、尖頭発波長６　６　０　ｎｍ±２ｎｍ，輝度値が
１０５０Ｆｔ−Ｌ〜１１６０Ｆｔ−Ｌ，平均１０９０Ｆ
ｔ−Ｌであった。The epitaxial wafer obtained as above,
A red light emitting diode chip is produced by putting it into a device production line that includes a backside (substrate) polishing process, an electrode forming process, and a wire bonding process. /n junction dimension is
DC current density 2OA for both 500μ x 500μ square)
A current of /cnf was applied, and the brightness value (light output) was measured under the condition that the chip was not coated with epoxy resin. As a result, the peak emission wavelength was 660 nm±2 nm, the brightness value was 1050Ft-L to 1160Ft-L, and the average was 1090F.
It was t-L.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、組成変化層の構造と、組
成一定層と急激な組成変化層を交互に所定の構造に形成
することにより、ＧａＡｓまたはＧａＰ基板の格子不整
合による転位の発生を組戒変化層内で抑制することがで
きるので、発光層となるＧ　ａ　Ａ　ｓ　＋　−ｗ　Ｐ
　Ｘ層として結晶欠陥転位の少ない良質の結晶性を有す
るものを得ることができ、本発明のエピタキシャルウェ
ハを用いることにより高輝度の発光ダイオードを得るこ
とができる。As described above, according to the present invention, dislocations occur due to lattice mismatch in the GaAs or GaP substrate by alternately forming a constant composition layer and a rapidly changing composition layer in a predetermined structure. can be suppressed within the group change layer, so that GaAs + -wP, which becomes the light emitting layer,
An X layer having good crystallinity with few crystal defects and dislocations can be obtained, and by using the epitaxial wafer of the present invention, a high brightness light emitting diode can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の発光ダイオードの断面構造を示す図、
第２図、第３図は本発明によるＧａＰ単結晶基板を用い
た発光ダイオードの実施例における断面構造を示す図、
第４図は比較例の断面構造を示す図、第５図、第６図は
ＧａＡｓ単結晶基板を用いた発光ダイ才一ドの実施例に
おける断面構造を示す図、第７図は比較例の断面構造を
示す図、第８図、第９図は従来の発光ダイオードの断面
構造を示す図である。 １・・・ＧａＡｓまたはＧａＰ単結晶基板、２・・・組
成変化層、 ３　−Ｇ　ａ　Ａ　Ｓ　＋ ８　Ｐつ。 出 願 人 三菱モンサント化或株式会社 （外１名）FIG. 1 is a diagram showing a cross-sectional structure of a light emitting diode of the present invention,
2 and 3 are diagrams showing the cross-sectional structure of an embodiment of a light emitting diode using a GaP single crystal substrate according to the present invention,
FIG. 4 is a diagram showing a cross-sectional structure of a comparative example, FIGS. 5 and 6 are diagrams showing a cross-sectional structure of an example of a light emitting diode using a GaAs single crystal substrate, and FIG. 7 is a diagram showing a cross-sectional structure of a comparative example. 8 and 9 are diagrams showing the cross-sectional structure of a conventional light emitting diode. DESCRIPTION OF SYMBOLS 1... GaAs or GaP single crystal substrate, 2... Composition change layer, 3-G a A S + 8 P one. Applicant Mitsubishi Monsanto Kaoru Co., Ltd. (1 other person)

Claims (3)

【特許請求の範囲】[Claims] （１）ＧａＡｓまたはＧａＰ単結晶基板上にＧａＡｓ＿
１＿−＿ｘＰ＿ｘをエピタキシャル成長させ、単結晶基
板と組成一定層ＧａＡｓ＿１＿−＿＿ｘＰ＿ｘとの間に
組成変化層を形成したエピタキシャルウェハにおいて、
前記組成変化層は層厚１μｍ以上の少なくとも１つの組
成一定層部分と、少なくとも２つ以上の組成変化層部分
とを有し、組成変化層部分のうちの少なくとも１層は１
μｍ当たりに対する組成変化率Δｘが、 約０．０２≦Δｘ≦約０．０８ であることを特徴とするエピタキシャルウェハ。(1) GaAs_ on a GaAs or GaP single crystal substrate
In an epitaxial wafer in which a composition change layer is formed between a single crystal substrate and a constant composition layer GaAs_1_-__xP_x,
The composition change layer has at least one constant composition layer portion with a layer thickness of 1 μm or more and at least two or more composition change layer portions, and at least one of the composition change layer portions has a layer thickness of 1 μm or more.
An epitaxial wafer characterized in that a composition change rate Δx per μm satisfies the following: approximately 0.02≦Δx≦about 0.08. （２）ＧａＡｓまたはＧａＰ単結晶基板上にエピタキシ
ャル成長させ、単結晶基板と組成一定層ＧａＡｓ＿１＿
−＿ｘＰ＿ｘとの間に組成変化層を形成するエピタキシ
ャルウェハの製造方法において、組成変化層の形成は、
原料供給量と温度とを同時に変化させて組成変化層部分
を形成する工程と、原料供給量と温度とを一定にして組
成一定層部分を形成する工程とからなることを特徴とす
るエピタキシャルウェハの製造方法。(2) Epitaxially grown on a GaAs or GaP single crystal substrate, and a constant composition layer GaAs_1_
-_xP_x In the method for manufacturing an epitaxial wafer in which a compositionally varied layer is formed between P_x, the compositionally varied layer is formed by:
An epitaxial wafer characterized by comprising a step of simultaneously changing the raw material supply amount and temperature to form a compositionally variable layer portion, and a step of forming a constant composition layer portion by keeping the raw material supply amount and temperature constant. Production method. （３）請求項２記載のエピタキシャルウェハの製造方法
において、基板と組成一定層との間の組成変化層を形成
する開始の成長温度が９７０〜８９０℃であり、終了時
の成長温度が９１０〜８００℃であることを特徴とする
製造方法。(3) In the method for manufacturing an epitaxial wafer according to claim 2, the growth temperature at the start of forming the compositionally variable layer between the substrate and the constant composition layer is 970 to 890°C, and the growth temperature at the end is 910 to 890°C. A manufacturing method characterized by a temperature of 800°C.
JP30367789A 1989-11-22 1989-11-22 Epitaxial wafer and manufacturing method thereof Expired - Fee Related JPH0760903B2 (en)

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DE4037198A DE4037198B4 (en) 1989-11-22 1990-11-22 Epitaxial wafers and method of making the same
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05347432A (en) * 1992-06-15 1993-12-27 Sharp Corp Semiconductor light-emitting element
JPH05347431A (en) * 1992-06-15 1993-12-27 Sharp Corp Substrate for semiconductor element and semiconductor element
WO1997025747A1 (en) * 1996-01-12 1997-07-17 Shin-Etsu Handotai Co., Ltd. Epitaxial wafer of compound semiconductor
JP2015525965A (en) * 2012-07-05 2015-09-07 コーニンクレッカ フィリップス エヌ ヴェ Light emitting diode having a light emitting layer containing nitrogen and phosphorus
JP2021182615A (en) * 2020-05-15 2021-11-25 信越半導体株式会社 Compound semiconductor epitaxial wafer and method for manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6039803A (en) * 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60148109A (en) * 1984-01-13 1985-08-05 Shin Etsu Handotai Co Ltd Epitaxial wafer

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696834A (en) * 1979-12-28 1981-08-05 Mitsubishi Monsanto Chem Co Compound semiconductor epitaxial wafer and manufacture thereof
JPS61291491A (en) * 1985-06-19 1986-12-22 Mitsubishi Monsanto Chem Co Gallium phosphide arsenide mixed crystal epitaxial wafer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60148109A (en) * 1984-01-13 1985-08-05 Shin Etsu Handotai Co Ltd Epitaxial wafer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05347432A (en) * 1992-06-15 1993-12-27 Sharp Corp Semiconductor light-emitting element
JPH05347431A (en) * 1992-06-15 1993-12-27 Sharp Corp Substrate for semiconductor element and semiconductor element
WO1997025747A1 (en) * 1996-01-12 1997-07-17 Shin-Etsu Handotai Co., Ltd. Epitaxial wafer of compound semiconductor
JP2015525965A (en) * 2012-07-05 2015-09-07 コーニンクレッカ フィリップス エヌ ヴェ Light emitting diode having a light emitting layer containing nitrogen and phosphorus
JP2021182615A (en) * 2020-05-15 2021-11-25 信越半導体株式会社 Compound semiconductor epitaxial wafer and method for manufacturing the same

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KR100210758B1 (en) 1999-07-15
DE4037198B4 (en) 2005-02-24
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DE4037198A1 (en) 1991-05-23
JPH0760903B2 (en) 1995-06-28

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