JPH03163817A - Large scale semiconductor integrated circuit chip - Google Patents

Abstract

PURPOSE:To increase the number of logic circuits contained in one chip by using a same aligner, by exposing circuit layout data which are inscribed in a circumference showing a range where optical aberration satisfies a reference value, has six or more vertexes of even number, and is provided with at least two pairs of facing parallel sides. CONSTITUTION:The inside of a circumference 8 is a region capable of assuring that aberration of a wafer stepper is lower than or equal to a reference value. A shaded region 19 is one where circuit elements are formed, i.e., the effective region of a chip. Even in a case where a same optical system of same wafer stepper is used, the effective chip region which can be used for the arrangement of circuit elements can be increased by about 40%, only by tranforming the external shape of a chip from, e.g. a square into an octagon. When the number of corners of the polygon inscribed in the circumference is increased, the area capable of effectively exposing circuit elements can finally be increased by about 60%. Thereby the chip size can be enlarged up to the limit of wafer stepper capability, and a circuit chip on which many logic circuits can be mounted is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a large-scale semiconductor integrated circuit chip.

[Conventional technology]

Figure 6 shows, for example, a diamond issued in July 1982; 7 F
Company publication l” @ L S I Technology @ Collection 1 9 8
FIG. 2 is a diagram schematically showing the optical system of a conventional reduction projection type exposure apparatus (1) shown on page 160 of "2nd Edition."

With the increasing size of wafers and the demand for finer patterns, the reduction projection type exposure equipment mentioned above has become impossible to expose the entire wafer at once. It is.

In FIG. 6, 1 is a wafer such as a silicon crystal, 2 is an XY stage, 3 is a reduction projection lens, 4 is a condenser lens, 5 is a reticle, 6 is an illumination optical system, and 7 is a chip on the wafer 81. This is a chip with data reduced and exposed.

Next, the operation will be explained.

Place the wafer 1 on the XY stage 2, and
Move Y stage 2 in steps, from 1/5 to 1
Reticle images (chip data) reduced to 1/0 are sequentially exposed onto the wafer 1.

After the wafer 1 is exposed, it is cut with a fine diamond cutter or the like and housed in a package as a chip 7. Therefore, the chip 7 has a rectangular shape in consideration of ease of processing. On the other hand, in an optical system (2) such as the wafer stepper shown in FIG. 6, aberrations occur that cause image distortion. Normally, this aberration becomes severe as the distance from the optical axis increases in a concentric manner.

Therefore, as shown in FIG. 7, the chip size is determined so that the maximum value is a rectangle inscribed in the circumference within a range within which the aberration is within a certain reference value.

In FIG. 7, 8 is a circumference indicating the range within which the aberration of the optical system of the wafer stepper is within a certain reference value, 9 is a large-scale semiconductor integrated circuit chip, and 10 is a dicing line.

As shown in FIG. 8, the dicing line 10 represents the boundary line of the chip, and is an area on the semiconductor substrate 11 where there is no insulating film 12 for element isolation, no intra-chip wiring 13, and no chip protective film 14. Therefore, the chips are separated by cutting the area B with a diamond cutter.

The separated chips are housed in a package shown in FIG. In this figure, 15 is a package, 16 is a via, and 17 is a wire that connects the bonding pad on the chip and the inner lead of the package 15 (3). Since the chip 7 is rectangular, the cavity in which the chip 7 is accommodated is also rectangular.

[Problem to be solved by the invention]

Since the conventional large-scale semiconductor integrated circuit chip is constructed as described above, the maximum dimension of the chip 7 is determined by the wafer stage.
The size must be smaller than the rectangle inscribed in the circumference 8 defined by Soba's aberration, making it impossible to fully utilize the capabilities of the Ueno stepper, and the chip size becoming insufficient to accommodate the ever-increasing number of logic circuits. There were problems such as not having enough.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a large-scale semiconductor integrated circuit chip that can increase the chip size to the full capacity of a wafer stepper and can mount a large number of logic circuits. shall be.

[Means to solve the problem]

The large-scale semiconductor integrated circuit chip according to the present invention has (4) inscribed in the circumference indicating the range in which the optical aberration of the optical device for exposing the large-scale semiconductor integrated circuit chip satisfies the reference value, and has an even number of six or more points. A polygonal shape having a vertex, at least two pairs of opposing sides being parallel to each other, and two pairs of sides perpendicular to each other, and an effective distribution layout 1 of a large-scale semiconductor integrated circuit inside the polygonal shape. It has been exposed to light.

[Effect]

In the large-scale semiconductor integrated circuit chip of the present invention, the polygon inscribed in the outer circle of the area where the aberration of the wafer stepper is within a reference value has an even number of vertices larger than 6, and at least 2i11 opposite sides are parallel to each other. By using a polygonal chip external shape and laying out circuit elements inside this chip, even if the same wafer stepper is used, it is possible to expose any number of circuit elements within one chip. can.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a large-scale semiconductor integrated circuit chip showing one embodiment of the present invention. Figure 1 Smell (5)? , the inside of the circumference 8 is a region where it can be guaranteed that the aberration of the wafer stepper is less than the reference value. A shaded area 19 indicates an area where circuit elements have been completely formed, that is, an effective area of the chip. Reference numeral 10 is a dicing line, which electrically separates the effective area 9 of the sample from the area where the yield cannot be guaranteed.

The area inside the circumference 8 is πR2, where R is the flat diameter.

The area of the square inscribed in the circumference 8 is 2R2. Also, the area of the regular octagon inscribed in the circumference 8 is 2 ffR
It becomes 2. In other words, even if the same optical system of the same wafer stepper is used, by simply changing the external shape of the chip from a square to an octagon, the effective chip area that can be used for arranging circuit elements can be reduced to 2F/2= 1.4 1 4..., which can be increased by about 40%. As we increase the number of strokes of the inscribed polygon, ultimately π/2 = 1.570
. . . The area of the region where circuit elements can be effectively exposed can be increased by about 60%.

In order to expose a large chip within the finite exposure range of the wafer stepper, it is possible to consider a method such as dividing one chip into two parts and exposing each half of the chip twice. The edge of the exposure area of the stepper (
In other words, it corresponds to the dicing line area of a normal chip) (It has quite large aberrations and there is some light reflection, so it is not a suitable area for exposing fine metal wiring or elements. (2) Step and Revy 1 chips on a wafer one by one using a wafer stepper
・Since the movement during exposure is done mechanically, double exposure and interference are likely to occur due to accuracy, and it is difficult to connect fine metal wiring and elements at their boundaries. It's not very realistic.

Therefore, it is of great significance that the exposed area can be increased by 40% to 60% all at once without changing the exposure method using the existing exposure apparatus. This is due to the fact that the number of circuit elements per chip is increasing rapidly, such as by installing a floating point arithmetic unit, memory management unit, and cache memory control unit on a conventional microprocessor chip, while reducing capital investment costs. This is an effective way to absorb it without increasing it.

(7) Figure 2 shows a package that accommodates this large-scale semiconductor integrated circuit chip. In this figure, 7 is a chip (large-scale semiconductor integrated circuit chip), 15 is a package, 16 is a pin that electrically connects the internal board of this package 15 and the printed circuit board, and 17 is a pin of the chip 7.
This is a wire that electrically connects the pad 18 (FIG. 3) and the inona lead of the package 15.

This is shown in Figure 3. An enlarged view of f-, so-I7 is shown. Otsu0〕
In the figure, 10 is a ding line and 18 is a bonding pad. By arranging the bonding pads 18 around the chip 7 in this way, the circuit logic inside the chip 7 can be efficiently connected to the control signals and power supply from outside the chip 7.

In addition, by arranging the dicing line 10 between the area where the effective pattern layout 1- of the chip 7 is exposed and the boundary between the dicing lines 10 and 2, as shown in the figure, the effective pattern layout 1-exposed area within the chip 7 is placed. This is an area where aberrations are not guaranteed due to constraints such as the optical system of the external exposure device, and the electrical behavior is unpredictable (8).
This allows the chip 7 to operate normally. As shown in FIG. 8, the structure of the Guisinog line 10 is such that an insulating film 12 for element isolation and a chip protection film 14 are placed between the effective area inside the chip 7 and the area where the behavior cannot be controlled. By introducing impurities of the appropriate conductivity type into the substrate surface, it is mechanically and electrically isolated from areas outside the dicing line.

To separate the chip 7 shown in FIG. 3 from the wafer, it may be cut into a rectangular shape, or the corners of the rectangle may be cut down to form a polygon. In that case, if it is housed in the package 15 shown in FIG. 2, the inner leads of the package 15 and the bonding pads 18 of the chip 7 can be easily interconnected by the wires 17, and the connection length of the wires 17 is also shortened, increasing the speed of circuit operation. be done.

FIG. 4 shows a chip 7a in which the polygonal chip shown in FIG. 3 has more corners. The more the number of polygonal chips inscribed in the circumference of a constant aberration of the exposure optical system increases, the closer it becomes to a circle, and the effective chip area expands (9).
It will be possible to store the information in the chip.

FIG. 5 is a diagram for explaining the design method of the chip 7, which is inscribed in the circumference indicating the range in which the optical aberration of the optical device that exposes the chip 7 satisfies the reference value, and has six or more vertices. , inside a polygon whose at least two sets of opposing sides are parallel to each other and whose two sets of sides are orthogonal, calculate the ratio of the width of the stairs in the row arrangement of basic circuit blocks to the height of the basic circuit blocks, The basic circuit blocks are arranged and routed so that the slope is equal to the tangent of the slope of the side that is not horizontal or vertical.

In other words, the Ga1 array method or the cell-based design method, which constructs circuit logic by arranging basic circuit blocks (Voricells) with a constant height, is applied to the polygonized chip with the effective chip area. This is the case. As shown in the figure (the wiring area is omitted in the figure), desired circuit logic is formed by arranging circuit blocks of height Y in the horizontal direction and interconnecting the blocks. When the effective area is a polygon as shown in the figure, the tangent of the side inclination angle (θ) is (1
0) If a design method is adopted in which the basic circuit blocks are arranged by determining the ratio (Y/X) between the stepped deviation X of the row arrangement of the basic circuit blocks and the height Y of the basic circuit blocks so that they are equal, the chip The utilization efficiency of the effective area within the area is improved.

In addition, in the above embodiment, the case of the game 1 array method or the Vori cell method design method was shown, but it
A megacell type large-scale integrated circuit design method including A and the like may be used, and the same effects as in the above embodiment can be achieved.

In addition, in each example, the exposure of the circuit diau 1 data was inscribed in the circumference that strictly indicates the range in which the optical aberration satisfies the reference value, but some of the vertices were located at positions that were not inscribed to some extent. I don't mind.

〔Effect of the invention〕

As explained above, the present invention provides a circle inscribed in the circumference indicating a range in which the optical aberration of an optical device for exposing a large-scale semiconductor integrated circuit chip satisfies a reference value, and having an even number of vertices of six or more points, At least two sets of opposing sides are parallel to each other, and the two sets of sides (11) are perpendicular to each other, forming a polygon, and valid circuit layout data for a large-scale semiconductor integrated circuit is exposed inside the polygon, so that the same Even if an exposure apparatus of 1 is used, the effect of increasing the number of circuit logics that can be accommodated in one chip can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a large-scale semiconductor integrated circuit chip and a dicing line according to an embodiment of O's invention, and FIG. 2 is a plan view showing a package for a large-scale semiconductor integrated circuit chip according to an embodiment of this invention. A perspective view, FIG. 3 is a plan view showing a large-scale semiconductor integrated circuit chip according to another embodiment of the invention of B, and FIG. 4 is a plan view showing a large-scale semiconductor integrated circuit chip according to still another embodiment of the invention. , FIG. 5 is a plan view showing an embodiment of the method for designing a large-scale semiconductor integrated circuit chip of the present invention, and FIG. 6 is a schematic diagram of a wafer stepper for exposing a large-scale semiconductor integrated circuit chip to explain the present invention. Fig. 7 is a plan view showing a conventional large-scale semiconductor integrated circuit chip, Fig. 8 is a cross-sectional view explaining the dicing line structure according to the conventional method and the present invention (12), and Fig. 9 is a plan view showing a conventional large-scale semiconductor integrated circuit chip. FIG. 2 is a perspective view showing a circuit chip package. In the figure, 7 is a chip, 8 is a circumference that does not indicate an area where the optical aberration of the exposure optical system is within the standard value, 10 is a dicing line, 11 is a semiconductor substrate, 12 is an oxide film for element isolation,
13 is internal wiring on the chip, 14 is a chip protective film, 15 is a package, 16 is a bin, 17 is a wire, 18 is a bonding pad, 19 is an effective area, Basic circuit block height, θ
is an edge other than horizontal or vertical. It is the slope. Note that the same reference numerals in each figure indicate corresponding parts.

Claims (1)

[Claims] It is inscribed in the circumference of a circle that indicates the range in which the optical aberration of an optical device that exposes large-scale semiconductor integrated circuit chips satisfies the reference value, has an even number of vertices of 6 or more points, and has at least two pairs of opposing sides that are parallel to each other. A large-scale semiconductor integrated circuit chip, characterized in that the chip has a polygonal shape with two sets of sides orthogonal to each other, and effective circuit layout data of the large-scale semiconductor integrated circuit is exposed inside the polygonal shape.