JPH03162181A - Signal processing circuit for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To reduce an unnecessary leakage component to a color subcarrier frequency region by band-limiting a vertical detail signal to a horizontal direction with a digital low pass filter whose characteristic has two or more zero points, at least, in the vicinity of the color subcarrier frequency of a composite color video signal. CONSTITUTION:The vertical detail signal IEV is band-limited to the horizontal direction and outputted by the specified digital low pass filter 27 having two or more zero points, at least, in the vicinity of the color subcarrier frequency of the composite color video signal. An addition circuit operates at processing rate 2fs, and adds a horizontal detail signal IEH of clock rate 2fs supplied from a digital high pass filter 26 and the vertical detail signal IEV of the clock rate fs supplied from the digital low pass filter 27. Thus, the unnecessary leakage component to the color subcarrier frequency region is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention digitizes an imaging output signal from a solid-state image sensor for generating video signals, and forms detail signals for image enhancement processing by digital signal processing. This paper relates to a signal processing circuit for a solid-state imaging device. B. Summary of the Invention The present invention provides a solid-state imaging device in which an imaging output signal from a solid-state image sensor for generating a video signal is digitized, and a detail signal for performing image enhancement processing is determined by digital signal processing. In the signal processing circuit, a digital output signal obtained by digitizing the imaging output signal from the solid-state image sensor for generating the video signal is synthesized by giving a delay time equal to approximately 1 horizontal scanning period to generate a vertical detail signal. death,
By limiting the band of the vertical detail signal in the horizontal direction using a digital low-pass filter having a characteristic of having at least two or more zero points in the vicinity of the color subcarrier frequency rse of the composite color video signal, the vertical detail signal is output in the color subcarrier frequency domain. This effectively prevents the vertical detail signal from being mixed in to some extent. C Conventional technology Charge coupled device (CCD)
In a solid-state imaging device that uses a solid-state image sensor with an M-like pixel structure as the imaging unit, which is popular in devices such as As shown, aliasing from the spatial sampling frequency Is is mixed in the imaging output signal from the solid-state image sensor. Conventionally, a birefringent optical low-pass filter is provided in the imaging optical system to suppress the Takagi side of the baseband predetermined value of the imaging signal, thereby satisfying the Nyquist condition of the sampling system using the solid-state image sensor. , the generation of aliasing components to the baseband of the imaging output No. 4T is prevented. In addition, color television camera devices include dual-type solid-state imaging devices that capture images in three primary colors using solid-state image sensors that are equipped with a solid-state image sensor for capturing green images and color coding filters for red pixels and blue pixels. 2. Description of the Related Art Multi-temporary solid-state imaging devices such as a three-plate type that capture three primary color images using individual solid-state image sensors have been put into practical use.

Furthermore, as a method for improving the resolution of the multi-chip solid-state imaging device, the solid-state image sensor for green image sensing is inscribed with 1/1 of the spatial sampling period of the pixel.
2) A so-called spatial pixel shifting method is known in which solid-state image sensors for red and blue images are arranged in a staggered manner. By adopting this spatial picture element shifting method, analog 141→]・′i″l′
The fS plate type solid-state imaging device can achieve high resolution that exceeds the pixel limit of solid-state image sensors.
In addition, standardization of the so-called DI/D2 format is underway for commercial digital video tape recorders used at broadcasting stations, etc., and color television is the digital interface for digital video-related equipment that conforms to these standards. It is also required for camera equipment. In the digital interface standards for digital video-related equipment mentioned above, the sampling rate is the sampling rate of the current solid-state image sensor [,
It is set to about. Furthermore, in general, in a television camera device, etc., W'
In order to improve R, gamma correction processing is performed on the imaging output signal obtained by the imaging unit, and image enhancement processing is performed in which a detail signal is formed from the imaging output signal and added to the original signal. There is. D. Problems to be Solved by the Invention By the way, as mentioned above, in a solid-state imaging device using a solid-state image sensor having a discrete pixel structure such as a COD as an imaging section, the above-mentioned image is processed by digital signal processing on an imaging output signal. When performing enhancement processing, there is a problem in that vertical detail signal components are mixed into the color subcarrier frequency domain, causing image quality deterioration due to cross color interference. Therefore, in view of the above-mentioned problems, the present invention performs image enhancement processing on a digital output signal obtained by digitizing an imaging output signal from a solid-state image sensor for generating a video signal without causing image quality deterioration due to cross color interference. The present invention aims to provide a signal processing circuit for a solid-state imaging device that is capable of forming a vertical detail signal that does not mix into the color subcarrier frequency domain. EL1! Means for Solving the Problems In order to achieve the above-mentioned objects, the present invention provides an analog-to-digital conversion means for digitizing an imaging output signal from a solid-state image sensor for generating a video signal, and an analog-to-digital conversion means for digitizing an imaging output signal from a solid-state image sensor for generating a video signal. a vertical detail signal, which includes at least one digital delay means whose delay time is approximately equal to one horizontal scanning period, and which synthesizes a plurality of output signals from the cough delay means to generate a vertical detail signal. a digital low-pass filter to which the output {i of the vertical detail signal generating means is supplied and which limits the band of the output signal in the horizontal direction;
The digital low-pass filter is characterized by having at least two or more zero points near the color subcarrier frequency of the composite color video signal. F action In the signal processing circuit of the solid-state imaging device according to the present invention, the delay time is approximately l horizontal scanning period for the digital output signal obtained by digitizing the imaging output signal from the solid-state image sensor for generating a video signal using the analog-to-digital conversion means. The vertical detail signal generating means includes at least one digital delay means equal to . . . , which combines the plurality of output signals from the delay means to form a vertical detail signal. Then, the vertical detail signal from the vertical detail signal generating means is band-limited in the horizontal direction by a digital low-pass filter having a characteristic of having at least two or more zero points near the color subcarrier frequency of the composite color video signal. G. Example Hereinafter, an example of a signal processing circuit for a solid-state imaging device according to the present invention will be described in detail with reference to the drawings. Figure 1 shows how the lid 11 light L+ incident from the imaging lens (1) via the optical low-pass filter (2) is separated into the three primary color lights of R, C, and B by the color separation prism (3). A color television camera device is constructed by applying the present invention to a three-chip solid-state imaging device that captures three primary color images of a subject using three COD image sensors (41?), (4G), and (4B). It shows. In this embodiment, the above three COD image sensors (4R
), (4G), (48) employs the spatial cylindrical shift method to obtain C for green image imaging, as shown in Figure 2.
In contrast to the OD image sensor (4G), a CCD image sensor (4R) for capturing a red image a and C for capturing a blue image
The OD image sensor (4B) is set to a spatial sampling period of picture elements τ. They are placed offset by 1/2 of the . And the above three CCD image sensors (4R). (4
G) and (4B) are driven by a CCD drive circuit (not shown), and the imaging charge of each pixel is adjusted to the color subcarrier frequency rs.
The sampling frequency is four times c, that is, 4rsc. The three CCD image sensors (4R), (4G), and (4B) that adopt the spatial pixel shifting method are used to capture the green image of the three primary colors of the subject image.
D image sensor (4G) and each CCD image sensor (4R) for capturing the red image and blue image,
(4B) and τ. Spatial sampling is performed at a position shifted by /2. As a result, the above CCD image sensor (4R
)． (4G). Each imaging output signal S R$+ S @11+ S @m read from (411) is
As shown in FIG. 3, the spectral components are as follows: the sampling frequency Is of the green image output signal SGII by the COD image sensor (4G) and each
Red image output signal Sl. by CD image sensor (4R), (4B). and blue imaging output signals S, . The above-mentioned sampling frequencies ``S precept'' and ``S precept'' are in opposite phase to each other. Then, each CCD image sensor (
Each imaging output signal SEIISGl11Sl* read from buffer amplifiers (5R), <5G), (5B)
an analog-to-digital (A/D) converter (61
1), (6G), and (611). Each of these A/Di converters (6R). (6G) , (6
B) includes each of the above-mentioned imaging output signals S Ill S G *+
A clock rate equal to the sampling rate of S l+1, that is, each of the above CCD imagers (4R)
．． (4G), (4[1) 0) A clock with a clock frequency fs of 4fsc, which is the same as the FA output clock? The timing is given by a timing generator (not shown). Each of the above A/D converters (6R), (6G) . (
6B) is each of the above imaging output signals Sll*l S@*I
S. ．． is digitized as it is with the 4fsc crofcrate fs, and each of the above image pickup output signals S. ．． ,S @
Each color data D l11+ D s of the same output spectrum as the spectrum shown in FIG. 3 above for 11+ 3111
Form **+D**. The above A/D converter (6R). (6G). (6B
) Each color data D*m+Dc■D. ．． teeth,
The signal is supplied to the signal processing section (7). The signal processing section (7), whose detailed configuration is shown in FIG. 4, processes the red data D obtained by the A/D converter (6R). and the above A/DitIIll2i
(6G) green data D, . a detail signal generator (1l) to which is supplied the A/D converter (6R) . (6G). (6B) Three primary color data DSagi-II) Golo original. − is the delay circuit (
1211). (12G). <1211) is supplied via the interpolation processing unit (13R). (13G)
．． (13B) and these interpolation processing units (13R).
(13G) . (138) to interpolated three primary color data D@**. Dc. Detail signal D 11mm from ID1** and the detail signal generating section (11) is {i
Adders (14R), (14G), (1
4B) and these adders (14R), (14G)
．． Gamma correction processing circuits (15R), (15G) . to which the addition output of (14B) is supplied. (15B). In this signal processing section (7), the interpolation processing section (13
R). (13G) . (13I1) is the above A/
By performing interpolation processing on the three primary color data DI., D6th.D Im at the clock rate Is of the 4f prize supplied from the D converter ((iR). Three primary color data D @ clock rate 2fs with twice the rate fs, that is 8rsc
**． Form D c**+ D I11m. Then, the interpolation processing section (131?), (13G) .
(13B) is the three primary color data D at the clock rate of 2rs. , Da**+Dm** above is added 3E! S(1
4R). (14G). (1411). These adders (14R). (14G) , (73+1
) is the interpolation processing unit (131?) . (13G)
, (3 primary color data D**+D from (1.1111>)
s. Add the detail signal 0 11464 from the detail signal generator (1l) to 1L11*? As a result, image enhancement processing is applied to the three primary color data Da●●+k+D1**. This image-enhanced three primary color data D @6m, D G**+Dl1
111 is the gamma correction processing circuit (15R). (15G
), (15B). And the gamma correction processing circuit (151?). (15G) , (15[
1) is the adder (14R). (14G).
(14B) image enhancement processed three primary color data D, . ■DG*1DI. Gamma correction processing is applied to
Gamma-corrected each color data DI$11+ DG
Outputs ＊＊+ D ＊＊＊. Further, in this embodiment, the detail signal generating section (11) has green data DG. A first delay circuit (2l) which takes input data cps as input data, and a second delay circuit (22) which takes red data Dam obtained by the A/D converter (6R) as input data RIM. The l-th delay circuit (21
) are two 111 delay circuits (21a) . (2l
b) are connected in series. This first delay circuit (21)
For the green input data CIN supplied from the above A/DI:tAa (6G), the OH delay output C+N,
IH delay output G, lI. L and 2H delay output G! oL to the first comb filter (23), and
11 delayed output is supplied to the interpolation processing section (14G) via the delay circuit (13G). Similarly, the second delay circuit (22) includes two IH delay circuits (22a) .
(22b) are connected in series. This second delay circuit (22) outputs 0 11 delayed outputs R, .
, tH delay output R. , and 2H delay output R tNlIL
is supplied to the second comb filter (24), and the LH delayed output is supplied to the interpolation processing section (14R) via the delay circuit (13R). The first comb filter (23) is the A/D variable? Regarding the green input data CIN supplied from the device (6G) to the first delay circuit (2l), the first delay circuit (2l)
l) The above three types of delayed output G INI G II
Based on IIIG■1, filter outputs OH, GV, and DC indicated by DG-ω1・COX...■ are given to the mixer circuit (25). Further, the second comb filter (24) includes the A/D
Regarding the red human input data Ril+ supplied from the converter (6R) to the second delay circuit (22), the three types of delay outputs RIN+R from the second delay circuit (22) are
IHIL+R! Based on NIL, ω publication RH--7- (2+(ω1+ω)・R 181...
・■4 Or, RH-ω-1・RIN ... ■or, RV-0 ...■ or DR-0 ...■ Filter output RH, T? V, DR to the above mixer circuit (
25〉. The mixer circuit (25) receives the filter outputs OH, GV, DC from the first comb filter (23) and the filter output +111,R'/,DR from the second comb filter (24). Based on IEH'-G
Hl? I1 ... [phase] IEV' -GV+α
・RV (α−0, '/a. K, N ・・・■L已V
-OH+β・r? H...@ or LEV-DC+β-DR (β-0.1)... @ joint output IEH', LEV'. Output LEV. The composite output IEH' from the ξ xer circuit (25) is generated by combining the filter output GH from the first comb filter (23) and the filter output RH from the second comb filter (24) at a clock rate of 2rs. The first digital filter circuit Ws(2
6). In this way, also in this color television camera device in which the spatial pixel shifting method is adopted in the imaging section, the A/D converters (6R), (6G)
The above red data D1. and green data DG
．． In the detail signal generating unit (11), the filter output OH from the comb filter (22) of the ffil and the filter output RH from the second comb filter (24) are input to the ξ xer circuit ( By adding equal amounts in step 25), all the first-order carrier power is canceled, and a wideband horizontal detail signal IEH' can be formed without aliasing distortion. Here, in this color television camera device in which the spatial pixel shifting method is adopted in the imaging section, in addition to adding equal amounts of the green image imaging signal and the red image imaging signal, the green image imaging signal and the blue image imaging signal are Even if you add the same amount of the red image signal and the blue image signal, or add the composite signal of the red image signal and the blue image signal to the green image signal, all the first-order carrier components will be canceled and aliasing distortion will occur. It is possible to detect wideband horizontal detail signals without any accompanying noise. Further, the filter output GV from the first comb filter (23) and the filter output RV from the second comb filter (24) are divided into 1:α by the ξ xer circuit (25).
The above-mentioned combined output IEV' added at the ratio of is sent to the second digital filter circuit (27) as a vertical detail signal.
is supplied to Furthermore, the filter output GH or DG from the first comb filter (23) and the second comb filter (24)
The combined output obtained by adding the filter output 17H or DH from the mixer circuit (25) at a ratio of l:β is supplied as a level signal to the level dependent signal generation circuit (28). ．． The first digital filter circuit (26) receives the combined output IEH' from the mixer circuit (25) as a horizontal detail signal with a clock rate of 2rs. The first daisicle filter circuit (26) has an equalizing block structure as shown in Fig. 6, for example. As shown, l H+(z) − − (−z−′+2z−” − 1
) −・− 814 The first filter profile (41) is represented by the transfer function H+(z), and 1 H*(z) − (z−”+2z−’
1) ... ■4 A second filter block (42〉) indicated by the transfer function Hz(z), and
)...- ■4 A third filter plotter (43) represented by the transfer function H3(z), and ■ H4(Z) − (Z-'+22-''+1)
...@4 transfer function H. Cx) and weighting coefficients ap, β1 . Each coefficient circuit (45) giving β3, β. (46) , (47) ,
(48) and the above coefficients (46), (47)
．． Adding circuit (49) that adds the outputs of (48)
Tachibana was given the precept by Tachibana. The first digital filter circuit (26) has 2Is
1 E E H m − (− z−'+2z−” − 1
)4 4 β, + (-z""+2z-' - 1) }・IEH' 4...■ ap A P = (-z-'+2z-"+ l)
l6 x(-z-"+2z-'-1) = @
Each filter output IEH. Administer AP. Here, the combined output IEH' from the ξx 1 (25) is the filter output OH from the first comb filter (23) and the filter output RH from the second comb filter (24). Each of the above comb filters (23) . (24), the band is limited in the vertical direction on the two-dimensional frequency space shown in FIG. ? j
! near the color subcarrier frequency rsc of the combined color video signal (
The first digital filter circuit (2
The horizontal detail signal IEH obtained by band-limiting in the horizontal direction in step 6) has unnecessary leakage components to the color subcarrier frequency SC ( r sc + 1/4) fiI region on the two-dimensional frequency space shown in Figure 8. It is possible to perform high-quality horizontal contour enhancement processing without cross-color interference. The filter output IEH from the first digital filter circuit (26) is supplied to the adder (29) as a horizontal detail signal, and the filter output AP is
It is supplied to the adder (34) via the first core circuit I8 (30) that performs nonlinear processing. Further, the second digital filter circuit (27) applies 1H. (z) = (z one meeting + 2z-'+
1) A first filter block (5l) giving a transfer function H + (z) of -@4 and this lth filter block (51)
a first switching circuit block (52) that selects between the filter output signal of the filter output signal and the vertical detail signal ■巳■゛ to switch the filter characteristics; and a first selection output from the first switching circuit block (52). l Hz(z) − (z−'+2z−”+, l
) −． ．． ■Transfer function of 4 H. (z); and a second switching circuit that selects between the filter output signal from the second filter block (53) and the first selection output signal to switch filter characteristics. block (54) and this second switching circuit block (54).
4) The weighting coefficient α is multiplied by n to the second selected output signal! 8 (55) and the output signal from this coefficient circuit (55), l Hs(z) − − (1 + z”)
- a third filter block (56) giving a transfer function 1{s(z) of @2. This second digital filter circuit (27) is a combination of the above-mentioned comb filter (23) . By (24), H(2)
= − (z−”+2z−′+ 1) −
For the above vertical detail signal IEV' at a clock rate of Is given a filter characteristic H(z) of 64,
The filter characteristic H + (
z) and the filter characteristic Hz(z
), the transfer function He(
z) 1 H, (z) = (z-” +2z-'+
1) 64 X (z-'+2z-"+ 1)
1EV is supplied to the adder circuit (29). Here, the vertical detail signal IEV' is the filter output Gv from the first comb filter (23),
Filter output R from the second comb filter (24)
Each of the above comb filters (23
)． (24), the band is limited in the vertical direction on the two-dimensional frequency space shown in FIG. 8 above. ? 3 [The above-mentioned second digital filter circuit (27
), the vertical detail signal IEV obtained by horizontally band-limiting the signal has unnecessary leakage components to the chrominance subcarrier frequency SC (r sc, I/4) H region on the two-dimensional frequency space shown in Fig. 8 above. It is possible to perform high-quality vertical contour enhancement processing without cross-color interference. The adder circuit (29) operates at a processing rate of 2fs and processes the horizontal detail signal IEH at a clock rate of 2rs supplied from the first digital filter circuit (26) and the second digital filter circuit ( 27) and the vertical detail signal IEV at the clock rate of Is supplied from Is. 2 by this adder circuit (29)
The addition output signal at the fs clock rate is sent to the multiplication circuit (32) via the second core circuit (3l) that performs nonlinear processing.
). Further, the level dependent signal generation circuit (28) to which the composite output LE■ from the mixer circuit (25) is supplied as a level signal generates a level dependent signal LD according to the level signal LEV, The multiplier circuit (32) multiplies the level dependent signal LDII by the multiplier (33)
Supply to. The multiplication circuit (32) multiplies the weighting coefficient by the multiplication circuit (33) and processes the Oyoi dependent signal LD by the addition circuit (29), which is subjected to nonlinear processing by the second core circuit (31). The multiplication output signal is multiplied by the addition output signal and the multiplication output signal is supplied to the addition circuit (34). This addition circuit (34) is the first core circuit (3o)
The filter output AP from the first digital filter circuit (25), which has been subjected to non-linear processing, is added to the multiplication output signal from the multiplication circuit (32), and the added output is converted into a detail signal [)+1 with a clock rate of 2 fs. .

Output as . The detail signal IE+t* of the above 2fs crof crate is generated from the detail signal generating section (1l) of such a structure.
* is supplied to the adder (14R). (14G)
, (14B) processes the detail signal D lill* at the clock rate of 2fs by the interpolation processing unit (13R).
, (13G) . 2rs supplied from (13B)
Rate three primary color data D 11 m m + D @
lj * + D l * 1) to perform image enhancement processing. And the adder (14R). (14G) and (14B) are three primary color data Dlm*, D@* that have undergone image enhancement processing.
-+ D l◆Gamma correction processing circuit (15R)
), (15G), (15B). The above gamma correction processing circuit (1512), (15G).
(15B) is the adder (14R) . (14G
), (14B) 3 primary color data 0 1m111 0G*61 Dl** is subjected to gamma correction processing, and 3 primary color data D $1) + 11 D G m 111 D @ *
Outputs 11. In this way, the signal processing section (
7) One outputs three primary color data D 6m1D@**ID1*a at a clock rate of 2 fs which has been subjected to image enhancement processing and gamma correction processing. 3 of the above 2fs clock rate output from this signal processing section (7)
Primary color data D l11$+ D @**+ D m**
Is it a color encoder? (8) and a digital-to-analog (D/A) converter (9R). (9
G), (9B). And the above D/A strange F
IA device (9R), (9G). (9B) is three primary color data D, which ensures the high resolution of the 2 fs croft crate provided from the signal processing section (7). +D6mm
ID@. is converted into analog and an analog three-primary color imaging output signal R out+G OIl? l B OLIT is connected to the signal output terminal (IOR), (IOC), (IOB
). Further, as shown in FIG. 11, the color encoder (8) receives three primary color data Dll*111D@*■ from the signal processing section (7) at a clock rate of 2 fs. D lm Yuga {
” (The supplied matrix circuit (8l) and the luminance signal data D y formed by this matrix circuit (81)
A delay circuit (82) to which * * is supplied, and each low-pass filter (to which each color difference signal data DI-Y1D m-vD+**+D** formed by the matrix circuit (81) is supplied) 83), (84). (
85), (86) and the above matrix circuit (81)
D, which is influenced by ■D. ．． is supplied through each of the above-mentioned low-pass filters (85) and (86), and a modulation circuit (87). an interpolation processing circuit (88) to which the modulated output data from the modulation circuit (87) is supplied; and an interpolation processing circuit (88) to which the interpolated output data from the interpolation processing circuit (88) is supplied and shaped by the matrix circuit (81). The luminance signal data D y *@ is the delay/delay circuit (82)
and an adder circuit (89) that is supplied via the adder circuit (89).
The matrix circuit (8l) receives the three primary color data D at a clock rate of 2fs. ．． ■By performing matrix arithmetic processing on D@am,k, luminance signal data Dvo at a clock rate of 2 fs and color difference signal data D1Y** at a clock rate of Is are obtained.
Form D l*, D@*. Then, this color encoder (8) inputs the three primary color data D1**+D
As the component color image data for @6m, D 1**, the luminance signal data D y * is sent from the matrix circuit (8l) through the delay circuit (82).
*, and the color difference signal data D I-Y11+D@-1m from the matrix circuit (8l) via the low-pass filters (83) and (84).
Outputs . Note that the delay circuit (82) includes the respective low-pass filters (83) . A delay characteristic corresponding to (84) is given to the luminance signal data DY*m. Also,
In this color encoder (8), the modulation circuit (
87) performs modulation processing to perform two-phase modulation of Dl*+Dos supplied from the matrix circuit (81) via the respective low-pass filters (85) and (86). The modulated output data from this modulation circuit (87) corresponds to a modulated color difference signal containing odd harmonics of the color subcarrier frequency rsc. Further, the interpolation processing circuit (88) includes the modulation circuit (
Regarding the modulated output data according to 87), ``,, precepts and 1
A digital filtering process is performed to extract the fsc signal, and the modulated color difference signal data with a clock rate of 2fs corresponding to 8r, . The color encoder (8) then outputs the luminance signal data D from the matrix circuit (81) via the delay circuit (82).
7. ．． and 2r formed by the above interpolation processing circuit (88).
By adding the modulated color difference signal data at a clock rate of s by the adder circuit (89), a digital composite? Form a video signal D CSmm. That is, the color encoder (8) generates three primary color data Dl111 at a clock rate of 2rs, which has been subjected to image enhancement processing and gamma correction processing by the signal processing section (7).
*l D @11111 D @** Regarding 2 above
A component color image composed of the luminance signal data D y * * ensuring high resolution at a clock rate of Is and each of the color difference signal data DI-7*I D m-y* at a clock rate of fs. The digital composite video signal D (3
Outputs **. The component color image data, that is, the luminance signal data D. output from this color encoder (8). ．． and each color difference signal data D. V■Dl-y* is a digital to analog ([1/A) converter (9Y)
, (9R-Y) . (9B-Y) is supplied.
The above D/A converter (9Y), (9R-Y), (
9B-Y) is the luminance signal data D y * * and each color difference signal data D I-Ylb+ D I-y *
By converting the analog component into an analog video signal Y. uT+ R-Yout+ B Y
Signal output terminal (IOY) as oui. (IOR-Y
)． Output from (IOB-Y). Furthermore, the digital composite video signal I)ct●● output from the color encoder (8>) is a digital composite video signal I).
Supplied to the analog (D/A) converter (9CS). The D/A converter (9CS) converts the digital composite video signal Dcs**, which has a high resolution of the 2rs clock rate, into an analog signal and outputs it as an analog composite video signal CSauy through a signal output terminal (IOCS). Output from. 1 { Effects of the Invention As described above, in the signal processing circuit of the solid-state imaging device according to the present invention, the imaging output signal from the solid-state image sensor for generating a video signal is digitized by the analog-to-digital conversion means. , a vertical detail signal generating means including at least one digital delay means whose delay time is approximately equal to one horizontal scanning period synthesizes a plurality of output signals from the delay means to form a vertical detail signal, and generates a composite color video signal. Since the vertical detail signal from the vertical detail signal generating means is horizontally band-limited by a digital low-pass filter having a characteristic of having at least two or more zero points in the vicinity of the color rjAWi transmission frequency, there is no need for the color subcarrier frequency domain. It is possible to obtain a vertical detail signal with small leakage and with which high-quality vertical contour enhancement processing can be performed without cross-color interference.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a three-panel color television camera device to which the present invention is applied, FIG. 2 is a schematic diagram showing the arrangement of each CCD image sensor in the three-panel color television camera device, and FIG. 4 is a diagram showing the signal spectrum of each imaging output signal from the CCD image sensor in the color television digital camera device (red), and FIG. FIG. 5 is a block diagram showing a specific example of the structure of the detail signal generation section of the signal processing section, and FIG. 6 is an equalization diagram of the first digital filter circuit of the detail signal generation section. FIG. 7 is a characteristic diagram showing the filter characteristics of the first digital filter circuit, and FIG. 8 is a two-dimensional diagram showing the frequency characteristics of the detail signal generated by the detail signal generating section. A schematic diagram shown in the frequency space, FIG. 9 is a block diagram showing the equalization block configuration of the second digital filter circuit of the detail signal generation section,
FIG. 11 is a characteristic diagram showing the filter characteristics of the second digital filter circuit, and FIG. 11 is a block diagram showing the structure of the color encoder constituting the above-mentioned dual color television camera device. FIG. 12 is a schematic diagram showing the signal spectrum of an image output signal from a general solid-state image sensor having a discrete pixel structure. (41?), (4G), (4B)...
・(6R) ． (6G), (6B)...
・(7)・・・・・・・・・・・・・・・(8)・・
・・・・・・・・・・・・・・・(1l)・・・・・・・・・
・・・・・・・・・(21) , (22)・・・・・・
・・・・・・・・・(25)・・・・・・・・・・・・・・・
・・・(27)・・・・・・・・・・・・・・・CCD
Image sensor A/D converter Signal processing section Color encoder Detail signal generation section Delay circuit Mixer circuit Digital filter circuit

Claims (1)

[Claims] Analog-to-digital conversion means for digitizing an imaging output signal from a solid-state image sensor for generating a video signal; and a digital output signal from the analog-to-digital conversion means is supplied, the delay time of which is approximately 1. Vertical detail signal generating means including at least one digital delay means equal to a horizontal scanning period and generating a vertical detail signal by synthesizing a plurality of output signals from the delay means; and an output signal of the vertical detail signal generating means; supplied,
and a digital low-pass filter that limits the band of the output signal in the horizontal direction, and the digital low-pass filter has a characteristic of having at least two or more zero points near the color subcarrier frequency of the composite color video signal. A signal processing circuit for a solid-state imaging device characterized by: