JPH03162037A - Psk modulation circuit - Google Patents

Psk modulation circuit

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Publication number
JPH03162037A
JPH03162037A JP30164989A JP30164989A JPH03162037A JP H03162037 A JPH03162037 A JP H03162037A JP 30164989 A JP30164989 A JP 30164989A JP 30164989 A JP30164989 A JP 30164989A JP H03162037 A JPH03162037 A JP H03162037A
Authority
JP
Japan
Prior art keywords
signal
counter
output
rom
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30164989A
Other languages
Japanese (ja)
Inventor
Shigeyuki Furushima
古島 重幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP30164989A priority Critical patent/JPH03162037A/en
Publication of JPH03162037A publication Critical patent/JPH03162037A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To avoid duplication and discontinuity of a signal at changeover of a carrier wave by storing one period of a PSK (Phase Shift Keying) modulation signal into a ROM and using a PCM (Pulse Code Modulation) input signal so as to count up or down the ROM address thereby obtaining carriers of 0 deg. and 180 deg.. CONSTITUTION:Since a PCM input signal 8 is inputted to an upcount/down-count control terminal of a counter 2, the counter 2 is counted up when the PCM input signal 8 is at an H level and the output of the counter 2 reaches from 0 into 2M<-1>, from 0 into 2M<-1>,... In this case, an output data 5 of a ROM 4 is a 0 deg.C carrier signal data. On the other hand, when the PCM input signal is at an L level, since the counter 2 is counted down, the output of the counter 2 goes from 2M<-1> into 0, 2M<-1> into 0,... and the output data 5 of the ROM 4 is a data of 180 deg. carrier signal. Thus, the duplicate and discontinuous signal at the carrier signal changeover point is avoided.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は, P C M (Pulsu Code 
Modulation)信号により搬送波を2相位相変
調するPSK(Phase Shift Keying
)変調回路に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] This invention is based on PCM (Pulsu Code
PSK (Phase Shift Keying) which performs two-phase phase modulation of the carrier wave using a modulation signal.
) relates to modulation circuits.

[従来の技術] 従来,この種の回路は第4図に示すものがあった。第4
図において.(7)はPSK出力信号をイネーブルする
ためのイネーブル信号,(8)はPCM入力信号,(9
)はPSK出力信号, (10)は搬送波用正弦波信号
+’ [11)はバツファ回路, (12)は搬送波用
正弦波信号(lO)を180度位相反転させる位相反転
回路, (13)は搬送波用正弦波信号(lO)と同一
位相の0度搬送波信号, (14)は位相反転回路によ
り搬送波用正弦波信号(lO)と180度の位相差をも
つ180度搬送波信号, (15)はPCM入力信号(
8)により0度搬送波信号(13)と180度搬送波信
号(l4)を切替えて出力する単極双投スイッチ, (
161はイネーブル信号(7)によりPSK出力信号(
9)をイネーブルする単極単投スイッチである。
[Prior Art] Conventionally, there was a circuit of this type as shown in FIG. Fourth
In the figure. (7) is an enable signal for enabling the PSK output signal, (8) is a PCM input signal, (9
) is the PSK output signal, (10) is the carrier wave sine wave signal +' [11] is the buffer circuit, (12) is the phase inversion circuit that inverts the phase of the carrier wave sine wave signal (lO) by 180 degrees, (13) is (14) is a 180 degree carrier signal with a phase difference of 180 degrees from the carrier sine wave signal (1O) by a phase inversion circuit. (15) is PCM input signal (
8), a single-pole double-throw switch that switches and outputs the 0 degree carrier wave signal (13) and the 180 degree carrier wave signal (14), (
161 outputs the PSK output signal (
9) is a single-pole, single-throw switch.

次に動作について説明する。第4図において,搬送波用
正弦波信号(10)はバッファ回路(11)および位相
反転回路(l2)により,0度搬送波信号(l3)と1
80度搬送波信号(l4)に変換され,単極双投スイッ
チ(l5)はPCM入力信号(8)で制御される。
Next, the operation will be explained. In Fig. 4, the carrier wave sine wave signal (10) is connected to the 0 degree carrier wave signal (l3) by a buffer circuit (11) and a phase inversion circuit (l2).
It is converted into an 80 degree carrier wave signal (l4), and the single pole double throw switch (l5) is controlled by the PCM input signal (8).

したがって,単極双投スイッチ(l5)の出力を短絡し
た点の信号は,PCM入力信号{8}が”H″′レベル
の時はO度搬送波信号(l3)が,”L”レベルの時は
180度搬送波信号(l4)が現れる。この信号は単極
単投スイッチ(16)に入力され.イネーブル信号(7
)で制御されて有効な信号のみが単極単投スイッチ(l
6)の出力よりPSK信号(9)として出力される。
Therefore, the signal at the point where the output of the single-pole double-throw switch (l5) is short-circuited is that when the PCM input signal {8} is at the "H" level, the O degree carrier signal (l3) is at the "L" level. A 180 degree carrier wave signal (l4) appears. This signal is input to a single-pole, single-throw switch (16). enable signal (7
) and only valid signals are sent to the single-pole, single-throw switch (l
6) is output as a PSK signal (9).

[発明が解決しようとする課題] 以上記述したように,従来回路では位相反転回路で18
0度搬送波信号を作るため,PSK変調信号の搬送波と
なるO度と180度搬送波信号の位相を正確に180度
にすることが困難であり,また0度と180度搬送波信
号をスイッチで切替えるため.切替時に発生する信号の
重複および不連続が生じるなどの問題あがった。
[Problem to be solved by the invention] As described above, in the conventional circuit, the phase inversion circuit
In order to create a 0 degree carrier signal, it is difficult to make the phase of the 0 degree and 180 degree carrier signals, which are the carrier waves of the PSK modulation signal, exactly 180 degrees, and because the 0 degree and 180 degree carrier signals must be switched with a switch. .. Problems such as signal duplication and discontinuity that occur during switching have arisen.

この発明は上記のような問題点を解決するためになされ
たもので,PSK変調信号の0度および180度搬送波
信号を正確に180度の位相差をちっと共に,0度およ
びl80度搬送波信号切替点での信号の重複および不連
続のないPSK変調回路を得ることを目的とする。
This invention was made in order to solve the above-mentioned problems, and it is possible to accurately change the phase difference of 180 degrees between the 0 degree and 180 degree carrier wave signals of the PSK modulation signal, and to switch between the 0 degree and 180 degree carrier wave signals. It is an object of the present invention to obtain a PSK modulation circuit without signal overlap and discontinuity at points.

[課題を解決するための手段] この発明によるPSK変調回路は,PSK変調信号の搬
送波!周期分をR O M (Read Only M
emor・y)に記憶させ.PCM入力信号でROMア
ドレスをカウント・アップおよびカウン1・・ダウンさ
せることによりO度搬送波と180度搬送波を発生させ
,D/A変換回路によりアナログ信号に変換したもので
ある。
[Means for Solving the Problems] The PSK modulation circuit according to the present invention uses a carrier wave of a PSK modulation signal! The period is R O M (Read Only M
emo・y). The ROM address is counted up and counted down by 1 using the PCM input signal to generate an O degree carrier wave and a 180 degree carrier wave, which are converted into analog signals by a D/A conversion circuit.

[作用] この発明におけるPSK変調回路は.O度および180
度搬送波の波形をROMに記憶させておくことにより.
2つの搬送波の位相が正確に180度に保持され,また
,PCM人力信号によりROMの波形を読み出すことに
より2つの搬送波の切替点における信号の重複および不
連続点を無くすことができる。
[Function] The PSK modulation circuit in this invention has... O degrees and 180
By storing the waveform of the carrier wave in ROM.
The phases of the two carrier waves are maintained at exactly 180 degrees, and by reading out the waveform in the ROM using a PCM manual signal, it is possible to eliminate signal overlap and discontinuity at the switching point of the two carrier waves.

[実施例] 以下.この発明の一実施例を図について説明する。第1
図において.(l)はPSK搬送波周波数の2M倍のP
SK搬送波用クロック信号,(2)はアップ・カウント
/ダウン・カウント制御端子付きのMビット・カウンタ
(以下カウンタと略す)i3)はカウンタ(2)が出力
するアドレス信号.(4)は正弦波1周期分を時間軸で
2M分割して振幅を量子化数Nビットで表わしたデータ
を記憶されたROM.(5)はR O M (4)の出
力データ,(6)は量子化数Nビットの正負出力および
アウトプット・イネーブル(OE)端子をもつD/A変
換回路である。なお,(7)はPSK出力信号をイネー
ブルされるためのイネーブル信号,(8)はPCM入力
信号,(9)はPSK出力信号である。
[Example] Below. An embodiment of the present invention will be described with reference to the drawings. 1st
In the figure. (l) is P which is 2M times the PSK carrier frequency
SK carrier wave clock signal, (2) is an M-bit counter (hereinafter abbreviated as counter) with up count/down count control terminal (i3) is an address signal output by counter (2). (4) is a ROM that stores data in which one period of a sine wave is divided into 2M on the time axis and the amplitude is expressed in quantization number N bits. (5) is the output data of R O M (4), and (6) is a D/A conversion circuit having a positive/negative output with a quantization number of N bits and an output enable (OE) terminal. Note that (7) is an enable signal for enabling the PSK output signal, (8) is a PCM input signal, and (9) is a PSK output signal.

第1図において,PSK搬送波用クロック信号(1)は
アップカウント/ダウンカウント制御端子はカウンタ(
2)によりM分周され,ROM(4)のアドレス信号と
なる。
In Figure 1, the PSK carrier clock signal (1) has an up-count/down-count control terminal connected to a counter (
2) and becomes the address signal for ROM (4).

ROMは第2図に示すように,搬送波用正弦波1周期分
が記憶されていて,アドレスは正弦波の時間軸に対応し
,lアドレスは360度/M (M:整数)に相当して
いる。
As shown in Figure 2, the ROM stores one period of a carrier sine wave, the address corresponds to the time axis of the sine wave, and the l address corresponds to 360 degrees/M (M: integer). There is.

データは正弦波の振幅をNビット(N:9数)で量子化
したもので,最小値が1,最大値が(2N−1)である
The data is obtained by quantizing the amplitude of a sine wave using N bits (N: 9 numbers), and the minimum value is 1 and the maximum value is (2N-1).

PCM入力信号(8)はカウンタ(2)のアップカウン
ト/ダウンカウント制御端子へ接続する。したがって.
カウンタ(2)の出力は,第3図(C)に示すようにP
CM入力信号(8)が”H”レベルの時カウンタ(2)
はカウント/アップするので0から2’−’ ,Oから
2kl−1,・・・どなる。この時r{ O M (4
1の出力データ(5)は第3図(d)に示すように0度
搬送波信号のデータとなる。一方.PCM入力信号が”
L”レベルの時カウンタ(2)はダウンカウントするの
で.カウンタ(2)の出力は第3図(d)に示すように
2v−+から0.2k″−1から0・・・となり,RO
M(4)の出力データ(5)は図3(d)に示すように
180度搬送波信号のデータとなる。
The PCM input signal (8) is connected to the up-count/down-count control terminal of the counter (2). therefore.
The output of the counter (2) is P as shown in Figure 3 (C).
When the CM input signal (8) is at “H” level, the counter (2)
counts/up, so it goes from 0 to 2'-', from O to 2kl-1, and so on. At this time r{ OM (4
The output data (5) of 1 becomes the data of the 0 degree carrier wave signal as shown in FIG. 3(d). on the other hand. The PCM input signal is
Since the counter (2) counts down when the level is L'', the output of the counter (2) changes from 2v-+ to 0.2k''-1 to 0... as shown in Figure 3(d), and RO
The output data (5) of M(4) becomes data of a 180 degree carrier wave signal as shown in FIG. 3(d).

このROM出力のNビットのデータ(5)はD/A変換
回路(6)によりアナログ信号に変換されてPSK出力
信号(9)になる。イネーブル信号(7)は,D/A変
換回路(6)のアウトプット・イネーブル端子に接続し
,PSK出力信号(9)の停止を行うものである。
This ROM output N-bit data (5) is converted into an analog signal by a D/A conversion circuit (6) and becomes a PSK output signal (9). The enable signal (7) is connected to the output enable terminal of the D/A conversion circuit (6) and is used to stop the PSK output signal (9).

なお,上記実施例でD/A変換回路(6)はイネーブル
端子付きの6ので示したが,アウトプット・イネーブル
端子なしのD/A変換回路の後にゲート回路を設け,イ
ネーブル信号(7)でゲート回路を開/閉しても同じ効
果を奏する。
In the above embodiment, the D/A conversion circuit (6) is shown as 6 with an enable terminal, but a gate circuit is provided after the D/A conversion circuit without an output enable terminal, and an enable signal (7) is provided. The same effect can be achieved by opening/closing the gate circuit.

また,ROM(4)は搬送波1周期分記憶で示したが整
数倍周期を記憶させても同じ効果を奏する。
Further, although the ROM (4) is shown as storing one period of the carrier wave, the same effect can be obtained even if the period is stored as an integral number.

[発明の効果] 上記のように.この発明によればPSK変調信号の1周
期分をROMに記憶させ.PCM入力信号によりROM
アドレスをアップカウントおよびダウンカウントさせて
0度と180度搬送波を得て,D/A変換回路でアナロ
グ信号に変換するように構成したので,0度および18
0度搬送波信号の位相差を正確に180度に保持し.ま
たO度および180度搬送波切替時における信号の重複
および不連続などをなくす効果がある。
[Effects of the invention] As mentioned above. According to this invention, one cycle of the PSK modulation signal is stored in the ROM. ROM by PCM input signal
The configuration is such that addresses are counted up and down to obtain carrier waves of 0 degrees and 180 degrees, and then converted to analog signals using a D/A conversion circuit.
The phase difference of the 0 degree carrier signal is maintained at exactly 180 degrees. It also has the effect of eliminating signal duplication and discontinuity when switching carriers at 0 degrees and 180 degrees.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明によるPSK変調回路の一実施例を示
す図,第2図,第3図はこの発明にょるPSK変調回路
の動作を示す図.第4図は従来のPSK変調回路を示す
図である。 図において,(l)はPSK搬送波周波数の2M倍のP
SK搬送波用クロック信号,(2)はアップカウント/
ダウンカウント制御端子付のMビット・カウント.(3
)はアドレス信号,(4)はROM, (5)はROM
出力データ.(6)はD/A変換回路,(7)はイネー
ブル信号.(8)はPCM入カ信号,(9)はPSK出
力信号, (10)は搬送波用正弦波信号. (11)
はバッファ回路. (12)は位相反転回路, (13
)は0度搬送波信号, (14)は180度搬送波信号
, (Is)は単極双投スイッチ. fl6)は単極単
投スイッチである。 なお, 図中の同一または相当部分には同一符号を付して示して
ある。
FIG. 1 is a diagram showing an embodiment of the PSK modulation circuit according to the present invention, and FIGS. 2 and 3 are diagrams showing the operation of the PSK modulation circuit according to the present invention. FIG. 4 is a diagram showing a conventional PSK modulation circuit. In the figure, (l) is P which is 2M times the PSK carrier frequency.
Clock signal for SK carrier wave, (2) is up count/
M-bit count with down count control terminal. (3
) is address signal, (4) is ROM, (5) is ROM
output data. (6) is a D/A conversion circuit, and (7) is an enable signal. (8) is a PCM input signal, (9) is a PSK output signal, and (10) is a carrier wave sine wave signal. (11)
is a buffer circuit. (12) is a phase inversion circuit, (13
) is a 0 degree carrier signal, (14) is a 180 degree carrier signal, (Is) is a single pole double throw switch. fl6) is a single pole single throw switch. In addition, the same or corresponding parts in the figures are indicated with the same reference numerals.

Claims (1)

【特許請求の範囲】[Claims] 搬送波周波数の2^Mのクロック信号を入力してM(M
は整数)分周するアップ・カウントとダウン・カウント
制御端子付きのカウンタと、このカウンタの出力をアド
レス信号とする正弦波n(nは整数)周期分のデータを
量子化数N(Nは整数)ビットで記憶させた記憶手段と
この記憶手段からの出力をアナログ量に変換する量子化
数NビットのD/A変換回路とを具備したことを特徴と
するPSK変調回路。
Input a clock signal with a carrier frequency of 2^M and calculate M(M
is an integer) A counter with up-count and down-count control terminals is used to divide the frequency, and the output of this counter is used as an address signal.N (n is an integer) period of data is quantized by a quantization number N (N is an integer) 1.) A PSK modulation circuit characterized by comprising a storage means for storing data in bits, and a D/A conversion circuit with a quantization number of N bits for converting the output from the storage means into an analog quantity.
JP30164989A 1989-11-20 1989-11-20 Psk modulation circuit Pending JPH03162037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30164989A JPH03162037A (en) 1989-11-20 1989-11-20 Psk modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30164989A JPH03162037A (en) 1989-11-20 1989-11-20 Psk modulation circuit

Publications (1)

Publication Number Publication Date
JPH03162037A true JPH03162037A (en) 1991-07-12

Family

ID=17899479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30164989A Pending JPH03162037A (en) 1989-11-20 1989-11-20 Psk modulation circuit

Country Status (1)

Country Link
JP (1) JPH03162037A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010183125A (en) * 2009-02-03 2010-08-19 Hitachi Ltd Gps signal transmitter and signal transmission method thereof
JP2013242325A (en) * 2013-07-12 2013-12-05 Hitachi Ltd Gps signal transmitter and signal transmission method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010183125A (en) * 2009-02-03 2010-08-19 Hitachi Ltd Gps signal transmitter and signal transmission method thereof
JP2013242325A (en) * 2013-07-12 2013-12-05 Hitachi Ltd Gps signal transmitter and signal transmission method thereof

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