JPH03161856A - Information apparatus - Google Patents

Abstract

PURPOSE:To prevent the processing speed of a program from being sharply reduced by allowing a main processor to programmably control the bus acquisition of a bus master to secure the bus cycle of the main processor itself. CONSTITUTION:The information apparatus is provided with a counter 110 for counting up the bus aquisition frequency of bus masters 101 to 104, a maximum bus acquisition frequency setting register 109 to be set up by the main processor 115 and a comparator 111 for comparing the value of the counter 110 with that of the register 109. When the value of the counter reaches the value of the register 109, the bus acquisition of the bus masters 101 to 104 is temporarily suspended. Since the bus cycle of the main processor 105 is secured, the program processing speed can be prevented from being sharply reduced.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to information equipment. [Prior Art] An example of a main processor bus arbitration protocol in a multi-bus master system including a main processor and a plurality of bus masters is shown in the timing chart of FIG. 6, which will be followed hereinafter. Each signal in FIG. 6 is a signal related to bus arbitration of the main processor,
Here, for the sake of simplicity, the description will be made assuming a multi-bus master system consisting of a main processor and one bus master. Each signal is the system clock rcLK of a multibus master system including the main processor.
J, an address strobe signal rASJ indicating that one of the main processor and the bus master is executing a bus cycle, and an address strobe signal rASJ indicating that one of the main processor and the bus master is executing a bus cycle. A data transfer response signal rDSACKx* that is output by a memory or peripheral device accessed by one of the devices during data transfer, a bus acquisition request signal rBR* that requests the main processor to acquire the bus from the bus master, and a bus acquisition request signal rBR* that requests the main processor to acquire the bus from the bus master. Bus permission signal rBG* that notifies the bus master of bus abandonment
J and a bus grant response signal "BGACK*J" from the bus master that acquired the bus to notify the main processor that the bus is acquired or in use.
When there are multiple bus masters, C K * J is also output to other bus masks to inform them that the bus has been acquired or is in use. Note that a signal with "*" at the end of each signal name indicates a negative logic, and the same applies hereinafter. At "T1" in FIG. 6, the bus master requesting bus acquisition outputs a bus acquisition request signal rBR*. Since the main processor generally has the lowest priority for bus acquisition, if the above-mentioned "BR*" is input, the main processor must relinquish the bus immediately after the end of the currently executing bus cycle. As shown in “T2” in the figure, the rBR*
A few clock cycles after the input of J, the bus permission signal “B
G*J is output to notify the path master that the bus will be handed over immediately after the currently executed bus cycle ends. At "T3" in FIG. 6, the bus mask indicates that after the rBG)kJ is input, the address strobe signal rAs*J, the data transfer response signal rDSACKX)kJ, and the data permission response signal rBGACKX) become invalid. By checking, we recognize that the main processor or other busmask has relinquished the bus. Thereafter, the bus master outputs the bus acquisition response signal rBGAcK*, and also outputs the bus acquisition request response signal rBRl as shown at T4 in FIG.
Disable kJ. At "T5" in FIG. 6, when the bus master completes its own bus cycle, the rBGAcK
*" to notify the main processor or other bus masks of bus relinquishment. The above is the bus arbitration protocol for the main processor to the bus master. 7th
The figure is a block diagram of a multi-bus master system showing the input/output relationship of each signal in FIG.
1 and a bus master 702. The address strobe signal 724 is connected to rAS*J in FIG. 6, the data transfer response signal 725 is connected to rDsACKX* in FIG. 6, the bus acquisition request signal 721 is connected to rBR*J in FIG.
22 is the bus permission response signal 723 to rBG*J in FIG.
correspond to rBGAcK*J in FIG. 6, respectively. Address strobe signal 724 and data transfer response signal 7
25 is a shared signal between the main processor 701 and the bus master 702; the bus acquisition request code 721 and bus grant response signal 723 are sent from the path master 702 to the main processor 701, and the bus grant signal 722 is sent to the main processor 701.
01 to the bus master 702, respectively. Further, the bus permission response signal 723 is re-inputted to the bus master 702. FIG. 8 is a block diagram of a multi-bus master system showing the input/output relationship of each signal when there are multiple bus masters.
02, 803, 804, 805 and bus acquisition control circuit 8
06. The address strobe signal 824 is connected to "AS*" in FIG. 6, the data transfer response signal 825 is connected to rDSACKX)kJ in FIG. 6, the bus acquisition request signal 821 is connected to rBRIJ in FIG. Figure 6 “
BG) kJ, the bus permission response signal 823 is rB in FIG.
Each corresponds to GAcK*J. Address strobe signal 824 and data transfer response signal 825 are signals shared by main processor 801 and bus masters 802-805. The bus acquisition request signal 821 is sent from the bus acquisition control circuit 806 to the main processor 801, and the bus grant signal 821 is sent from the bus acquisition control circuit 806 to the main processor 801.
22 is a bus acquisition control circuit 8 from the main processor 801;
06 respectively. Also, the bus permission response signal 82
3 from the bus acquisition control circuit 806 to the main processor 80
1, and also input to bus masks 802 to 805 so that each bus master can monitor the bus usage status of other bus masters. The bus acquisition request candidate signals 831-1 to 831-4 are sent from the bus masters 802 to 805 to the bus acquisition control circuit 806, and the bus permission response candidate signals 833-1 to 833-4 are sent from the bus masters 802 to 805 to the bus acquisition control circuit 806, respectively. The bus permission candidate signals 832-1 to 832-4 are sent from the bus acquisition control circuit 806 to the bus masters 802 to 805, respectively.
are input into each. The bus acquisition request response signal 821 for the main processor 801 is the logical sum of the bus acquisition request candidate signals 831-1 to 831-4 from each bus master, and is the bus grant response signal 8 for the main processor 801.
23 is a bus permission response candidate signal 833 from each bus master.
-1 to 833-4. The bus permission candidate signals 832-1 to 832-4 for each bus master are sent to the bus acquisition control circuit 806 after the bus permission signal 822 is input from the main processor 801 to the bus acquisition control circuit 806.
The signal connected to the next bus master selected by 6 becomes valid (LO). Therefore, the bus acquisition control circuit 806 has an arbitration function that arbitrates bus acquisition among a plurality of bus masters. Figure 9 is the 8th
This is a configuration diagram of the well-known bus acquisition control circuit 806 shown in the figure, including negative logic OR gates 901 and 902, and negative logic AND gates 903, 904, 905, 906, 913, and
914/915 and inverter 923/924/925
including. The bus acquisition request signal 931 to the main processor 801 in FIG. 8 is sent to 821 in FIG. 8, and the bus grant signal 932 from the main processor 801 in FIG.

[2. The bus permission response signal 933 to the main processor 8o1 in FIG. 8 is sent to the bus acquisition request candidate signal 9 from each bus master 802 to 805 in FIG.
41-1 to 941-4 are respectively 831-1 to 831-1 in Fig. 8.
831-4, bus permission candidate signals 942-1 to 942-4 to each bus master 802 to 805 in FIG. 8 are respectively sent to 832-1 to 832-4 in FIG. Bus permission response candidate signal 943 from 805
-1 to 943-4 are 833-l to 83 in Figure 8, respectively.
3-4 respectively. A bus acquisition request candidate signal 941-1 from the bus master 802 in FIG. 8 is input to a negative logic OR gate 901, a negative logic AND gate 903, and an inverter 923, respectively. Further, the output of inverter 923 is input to AND gate 913 of negative logic. Bus master 80 in Figure 8
The bus acquisition request candidate signal 941-2 from No. 3 is input to a negative logic OR gate 901, a negative logic AND gate 904, and an inverter 924, respectively. Further, the output of inverter 924 is input to AND gate 914 of negative logic. A bus acquisition request candidate signal 941-3 from the bus master 804 in FIG. 8 is input to a negative logic OR gate 901, a negative logic AND gate 905, and an inverter 925, respectively. Further, the output of inverter 925 is input to AND gate 915 of negative logic. The bus acquisition request candidate signal 941-4 from the bus master 805 in FIG.
is input. A bus grant signal 932 from the main processor 801 in FIG. 8 is input to negative logic AND gates 903 and 913. If the operation result is valid, the negative logic AND gate 913 connects the negative logic AND gates 904 and 9.
The signal connected to 14 is enabled (Lo). If the operation result is valid, the negative logic AND gate 914 makes the signals connected to the negative logic AND gates 905 and 915 valid (Lo). If the operation result is valid, the negative logic AND gate 915 makes the signal connected to the negative logic AND gate 906 valid (LO). If the operation result is valid, the negative logic AND gate 903 makes the signal connected to the bus permission candidate signal 942-1 to the bus master 802 in FIG. 8 valid (Lo). Negative logic AND gate 90
4 is the bus master 803 in FIG. 8 if the calculation result is valid.
The bus permission candidate signal 942-2 is enabled (Lo). If the operation result is valid, the negative logic AND gate 905 outputs the bus permission candidate signal 94 to the bus master 804 in FIG.
2-3 is enabled (Lo). If the operation result is valid, the negative logic AND gate 906 sends a bus permission candidate signal 942 to the bus master 805 in FIG.
-4 is enabled (Lo). Negative logic OR gate 902
is sent to the main processor-IO-801 in FIG. 8 if at least one of the bus permission response candidate signals 943-1 to 943-4 from each of the four bus masters 802 to 805 in FIG. 8 becomes valid (Lo). bus permission response signal 933 is enabled (Lo). A negative logic OR gate 901 receives a bus acquisition request signal 941- from each of the four bus masters 802 to 805 in FIG.
At least one of 1 to 941-4 is valid (Lo)
When this happens, the bus acquisition request signal 931 to the main processor 801 in FIG. 8 is enabled (Lo). As explained in FIG. 6, after the bus acquisition request cancellation signal 931 to the main processor 801 in FIG. 8 is enabled (LO), the input bus permission signal 932 from the main processor 801 in FIG. )become. Negative logic AND gate 913.9
The daisy chain consisting of 14, 915 and inverters 923, 924, and 925 receives the bus permission signal 932 from the main processor 801 in FIG.・In order to perform the interruption, if the bus acquisition request candidate signal 9
If the bus permission signal 932 is enabled (Lo) after both 4l-1 and 941-2 are enabled (Lo), the output of the negative logic AND gate 903 becomes L-11-O, as shown in FIG. The output bus permission candidate signal 942-1 to the bus master 802 becomes valid (Lo), but the output of the negative logic AND gate 904 remains Hi, and the bus permission candidate signal 942-1 to the bus master 803 in FIG. 2 remains invalid (Hi). The bus master 802 in FIG. 8 has a bus permission candidate signal 942-
1 is enabled (Lo), the address strobe signal 824, data transfer response signal 825, and bus permission response signal 823 are all disabled (H) as explained in FIG.
i), the bus permission response candidate signal 943-1 is enabled (LO), and then the bus acquisition request candidate signal 941-1 is disabled (Hi). But the 8th
Bus acquisition request candidate signal 94 from bus master 803 in the figure
Since 1-2 is still enabled (Lo),
11 request redemption code 931 also remains valid (LO), which is referred to as a bus request pending state. FIG. 10 is a timing chart showing the pending state of the bus request. The signal names are the same as in FIG. As shown in "T6"-12-1 in FIG. 10, the main processor outputs the bus permission signal "BG*".
At the time of invalidating J, the bus acquisition request signal r is still
If the input of BR*J is continued, it is recognized that the bus request is in a pending state, and after several clock cycles, the bus permission signal "BG*" is enabled again, and the After the bus cycle of bus master 802 in the figure ends, it is notified that the bus will continue to be handed over. Therefore, bus usage rights are transferred between bus masters. However, in a multi-bus master system, if such a pending state of bus requests occurs frequently, the main processor continues to relinquish the bus to each bus master, significantly reducing the program execution speed. Furthermore, if the main processor is abandoning the bus, even if an interrupt request is received, it will not be accepted and there is a risk that a buffer overflow of data from the interrupt requesting device will occur. FIG. 11 is a block diagram of a bus acquisition control circuit according to the prior art in which the bus acquisition control circuit of FIG. 9 is modified and restrictions are added to the generation of a bus acquisition request signal to the main processor. Or Gate 1101/1102
and negative logic AND gates l103, 1104, 110
5, 1106, 1113, 1114, and l115, inverters 1123, 1124, and 1125, a NAND gate 113l, and an inverter 1132. The bus acquisition request compensation code 1131 to the main processor 801 in FIG. 8 is sent to 931 in FIG. 9, and the bus grant signal 1132 from the main processor 801 in FIG. Bus grant response signal 113 to 801
3 corresponds to 933 in FIG. 9, and each bus master 802 to 802 in FIG.
Bus acquisition request candidate signals 1141-1 to 1141-11 from 805
41-4 are respectively 941-1 to 941-4 in FIG. 9, and bus permission candidate signals 1142-1 to 1142-4 to each bus master 802 to 805 in FIG. 8 are respectively 942-1 to 942-1 in FIG. 942-4, each bus master 80 in FIG.
Bus permission response candidate signal 1143-1 from 2 to 805
1143-4 are 943-1 to 943- in Fig. 9, respectively.
4 respectively. The configuration and operation of this circuit are as described in FIG. 9, except for the N-14 gate 1131 and the inverter 1132. The output of the negative logic OR gate 1101, that is, the bus acquisition request code 931 to the main processor 801 of FIG. 8, referred to in FIG.
The output of 132 is input to a NAND gate 1131. The output of the negative logic OR gate 1102 is the bus grant response signal 33 to the main processor 801 in FIG. 8, and is also input to the NAND gate 1131. If the operation result is valid, the NAND gate 1131 issues an output bus acquisition request code 1 to the main processor 801 in FIG.
Enable l31 (Lo). The NAND gate 1131 makes any of the bus acquisition request candidate signals 1141-1 to 1141-4 from each of the bus masters 802 to 805 in FIG. 8 valid (Lo), and bus permission from the bus masters 802 to 805 in FIG. Response candidate signal 1143-
When all of 1 to 1143-4 are invalid (Hi), that is, when all bus masters have given up the bus, the bus acquisition request redemption code 1131 to the main processor 801 in FIG. 8 is valid. (Lo), the 10th
The bus request pending state shown in the figure does not occur. However, if multiple bus masters request bus acquisition at the same time or in close proximity, the bus master connected higher up in the daisy chain will always acquire the bus. The controller performs DM from the generation of a bus acquisition request.
Synchronous DM with a specified maximum time until the start of A transfer
When attempting to perform A transfer, the data buffer
There is a risk of overflow. [Problems to be Solved by the Invention] However, as explained above, in an information device including a conventional bus acquisition control circuit, when the bus acquisition control circuit shown in FIG. 9 is used,
In situations where bus acquisition requests from the bus master occur frequently, the main processor unconditionally hands over the right to use the bus to the bus master, making it impossible to secure bus cycles for the main processor, resulting in a significant drop in program processing speed. There is also a risk of buffer overflow of data from the interrupt requesting device. Further, when the bus acquisition control circuit shown in FIG. 11 is used, if the bus master is a device that performs synchronous DMA transfer, there is a risk that buffer overflow of data to be DMA transferred may occur. Therefore, in order to eliminate the above-mentioned drawbacks, the present invention provides a circuit that suspends a bus acquisition request from a bus master for a certain period of time when the total number of bus acquisitions from the bus master reaches a preset number. An object of the present invention is to provide an information device having a bus acquisition control circuit that avoids a significant decrease in program processing speed by securing bus cycles. [al! Means for Solving Problem I] An information device of the present invention includes a multi-bus master system including a main processor and a plurality of bus masters, and includes a counter for counting the total number of bus acquisitions by the bus master. , a maximum bus acquisition count setting register that can be set by a main processor; a comparator that compares the value of the counter with the setting register; and when the value of the counter reaches the value of the setting register, the bus acquisition of the bus master is performed. The bus acquisition control circuit includes means for temporarily holding the bus. [Embodiment] FIG. 1 is a block diagram of a multi-bus master system including a bus acquisition control circuit according to the present invention.
20, 130, 140, 150, bus request daisy chain 105, and negative logic OR gates 106, 107,
108, a register 109, a counter 110, a comparator 111 that compares the register and the counter, a count control circuit 114 that controls the register and the counter, a negative logic OR gate 112, and a negative logic AND gate 11.
3 and a main processor 115. The block shown in FIG. 1 excluding the bus masters 101-105 and the main processor 115 is the bus acquisition control circuit 18-. All the signals are negative logic except for the register latch signal 172 and the bus acquisition request generation permission signal 179. The address strobe signal 180 and data transfer response signal 181 are transmitted to the main processor 115 and the bus mask 10.
This is a common signal with 1 to 105. Bus master 101-1
Bus acquisition request supplementary signals 161-1 to 161- from 04
4 indicates bus permission candidate signals 169-1 to bus masters 101 to 104, respectively, to 941-1 to 941-4 in FIG.
~169-4 are 942-1 to 942- in FIG. 9, respectively.
4, the bus permission response candidate signals 170-1 to 170-4 from the bus masters 101 to 104 are respectively 94 in FIG.
3-1 to 943-4, the bus acquisition request signal 167 to the main processor 115 is sent to 931 in FIG. 9, and the bus grant response signal 171 to the main processor 115 is sent to 9 in FIG.
33, the bus grant signal 1 from the main processor 115
68 corresponds to 932 in FIG. 9, respectively. The switch circuit 120 includes negative logic AND gates 122 and 123,
and an inverter 124. SW-19- The Tsuji circuit 130 includes negative logic AND gates 132 and 13.
3 and an inverter 134. switch circuit 140
includes negative logic AND gates 142 and 143 and an inverter 144. Switch circuit 150 includes negative logic AND gates 152 and 153 and an inverter 154. The bus master 101 sends the bus acquisition request candidate 161-1 to the negative logic AND gates 122 and 123 and the bus request candidate signal 170-1.
1 is output to each negative logic OR gate 108. The bus master 102 sends the bus acquisition request candidate signal 161-2 to the negative logic AND gates 132 and 133 and the bus request daisy chain 105, and sends the bus grant response candidate signal 170-2 to the bus request daisy chain 105.
are output to the negative logic OR gate 108, respectively. The bus master 103 outputs the bus acquisition request candidate signal 161-3 to the negative logic AND gates 142 and 143 and the bus request daisy chain 105, and outputs the bus grant response candidate signal 170-3 to the negative logic OR gate l08. The bus master 104 outputs the bus acquisition request candidate signal -20-161-4 to the negative logic AND gates 152 and 153 and the bus request daisy chain 105, and outputs the bus grant response candidate signal 170-4 to the negative logic OR gate l08. . Negative logic OR gate 108 outputs a bus grant response signal 171 to main processor 115. A bus grant response signal 171 to the main processor 115 is input to the counter 110 and is also used as an input clock for the counter 110, and is also used as an input clock for the counter 110.
The bus masters 101 to 105 also use the signals as monitor signals for confirming that other bus masters have abandoned the bus. Bus request daisy chain 105
are the bus permission signal 168 from the main processor 115 and the bus acquisition request candidate signal 16 from the bus masters 101 to 104.
Based on the inputs from 1-1 to 161-4, the bus master 101
Bus permission candidate signals 169-1 to 169- for ~104
4 is enabled (Lo). The negative logic OR gate 106 is the output 163- of the negative logic AND gate 122.
1, the output 163-2 of the negative logic AND gate 13-21-2, the output 163-3 of the negative logic AND gate 142, and the output 163-4 of the negative logic AND gate 152. If even one of the inputs is valid (Lo), the bus acquisition request signal (A) 166 is made valid (Lo) for the negative logic OR gate 112. Negative logic OR gate 107 is negative logic AND gate 1
23 output 162-1 and negative logic AND gate 133
output 162-2 of negative logic AND gate 143, and output 1 of negative logic AND gate 153.
62-4 as an input, and if even one of these inputs is valid (Lo), it is input to the negative logic AND gate 113.
On the other hand, the calculation result is made valid (Lo). The count control circuit 114 includes switch circuits 120, 130, 140-150.
Bus acquisition request selection signals 178-1, 178-2, and
178-3 and 178-4 respectively, and register 1
register latch signal 172 for counter 11
Counter reset signal 174 and counting operation for 0/
and an interrupt signal 175, respectively. -22- The comparator 111 calculates the maximum number of bus acquisitions 173 from the register 109 and the total number of bus acquisitions 17 from the counter 110.
6, and when the maximum number of bus acquisitions 173 and the total number of bus acquisitions 176 are both the same number, the negative logic AND gate 113 and the count control circuit 114 are set to be valid (Hi). The permission signal 179 for generating a bus acquisition request is invalidated (LO). If the operation result is valid (Lo), the negative logic AND gate 113 sends an output bus acquisition request signal (B) 1 to the negative logic OR gate 112.
65 is enabled (Lo). Negative logic OR gate l12
is the bus acquisition request signal (A) 166 and the bus acquisition request signal (A) 166
B) 165 is input, and if the calculation result is valid (Lo), a bus acquisition request signal 16 is sent to the main processor 115.
7 is enabled (Lo). Then main processor 11
5 to the bus request daisy chain 105 is asserted (LO). The operation of the bus request daisy chain 105 is as described in FIG. Suppose that the bus master 101 and the bus master 102 receive the bus acquisition request candidate signal 16 almost simultaneously.
1-1 and 161-2 are respectively enabled (LO), the bus permission candidate signal 169- to the bus master 101 with the highest priority selected in the bus request daisy chain 105
1 is enabled (LO). The bus master 101 responds with a bus grant after confirming that the address strobe signal 180, data transfer response signal 181, and bus grant response signal 171 are all invalid (Hi), that is, other bus masters including the main processor 115 have abandoned the bus. The candidate signal 170-1 is enabled (Lo), and the bus acquisition request candidate signal 161-1 is disabled (H1). The bus grant response candidate signal 170 - 1 passes through the negative logic OR gate 108 and outputs the bus grant response signal 171 to the main processor 115 .
becomes. Also, almost at the same time, the bus acquisition request candidate signal 161-
1 and 161-2 are enabled (Lo), the bus acquisition request signals 161-2 from the bus master 102 are still enabled (r, o), and the bus request is in the pending state as explained in FIG. occurs one by one. Therefore, after several clock cycles have elapsed since the main processor 115 disabled the bus permission signal 168 (H1), it again enables the bus permission signal 168 (Lo). This time, the bus request daisy chain 105 makes the bus grant candidate signal 169-2 valid (Lo), and the bus master 102 waits for the bus master 101 to relinquish the bus and continues to acquire the bus. FIG. 2 is a block diagram of the bus request daisy chain 105 shown in FIG.
213, and inverters 221, 222, and 223. The bus acquisition request candidate signals 231-1 to 231-4 from the bus masters 101 to 104 in FIG. 1 are sent to the bus masters 101 to 161-4 in FIG.
Bus permission candidate signals 232-1 to 232-1 to ~104
correspond to 169-1 to 169-4 in FIG. 1, respectively, and the bus permission signal 233 from the main processor 115 corresponds to 168 in FIG. The bus acquisition request candidate signal 231-1 city 1 from the bus master 101 is input to the negative logic AND gate 201 and the inverter 221. Further, the output of the inverter 221 is input to the AND gate 211 of negative logic. Bus acquisition request candidate signal 231- from bus master 102
2 is input to a negative logic AND gate 202 and an inverter 222. Further, the output of the inverter 222 is inputted to the AND gate 212 of negative logic. The bus acquisition request candidate signal 231-3 from the bus master 103 is input to the negative logic AND gate 203 and the inverter 223. In addition, the output of the inverter 223 is output from the AND gate 213 of negative logic.
is input to. The bus acquisition request candidate signal 231-4 from the bus master 104 is input to the negative logic AND gate 204. Bus grant signal 2 from main processor 115
33 is input to AND gates 201 and 221 of negative logic. The negative logic AND gate 211 sends the operation result to the negative logic AND gates 202 and 212, and the negative logic AND gate 212 sends the operation result to the negative logic AND gates 203 and 2.
13, the negative logic AND gate 213 converts the operation result into a negative
26- Output to each logic AND gate 204. The negative logic AND gate 201 sends the operation result to the bus master 1.
The negative logic AND gate 202 sends the operation result to the bus master 102 as the bus permission candidate signal 232-1 to 01, and the negative logic AND gate 203 sends the operation result to the bus master 103 as the bus permission candidate signal 232-1. A negative logic AND gate 20 is used as the permission candidate signal 232-3.
4 outputs the calculation results to the bus master 104 as a bus permission candidate signal 232-4. FIG. 3 is a block diagram of the count control circuit 114, and the register 10 in FIG.
9 and the counter 110, and also selects the signal output destination of the switch circuits 120, 130, 140, and 150. The count control circuit 114 is connected to the decoder 301/3
02, inverter 315, and flip frog 303
, a binary pinary counter 304, and a decoder 305.
306, flip-flop 307, and selector 308
, NAND gate 309, and decoders 311, 312,
313, 314, and flip-flops 3-27-2l, 322, 323, and 324. The register latch signal 351 is connected to 172 in FIG. 1, the count operation/interruption signal 352 is connected to 175 in FIG. 1, the counter reset signal 355 is connected to 174 in FIG. 179, the bus acquisition request selection signal 3
57-1 to 357-4 are respectively 178-1 to 178-1 in Figure 1.
178-4, respectively. The decoder 301 decodes the write signal 331 from the main processor 115 and the address bus 332, and the operation result is valid (Lo
), this is the input to the inverter 315. Inverter 315 uses its output as register latch signal 351 to register 109 in FIG. The register 10
9 latches the contents of the data path at the time when the register latch signal 172 (FIG. 3: 351) is enabled (Hi), and outputs this to the comparator 111 as the maximum number of bus acquisition times 173. The decoder 302 decodes the write signal 331 from the main processor 115 and the address bus 332, and if the operation result is valid (Lo), it makes the signal to the flip-flop 303 valid (Lo).
Make it. The flip-flop 303 indicates that the signal is invalid (H
i), that is, when the signal rises, the specific bit 333 of the data path is latched and a count continuation/suspension signal 352 is output to the counter 110 in FIG. If the count continuation/interruption signal 175 (Fig. 3: 352) is at Lo level, the counter 110 receives a bus permission response signal l.
71 as a clock input, and if the count continuation/interruption signal 175 (FIG. 3: 352) is at Hi level, the count-up is interrupted. Bus acquisition request generation permission signal 340 (Figure 1: l79)
is the manual reset of the binary pinary counter 304 (RO(1)
), the system clock 339 is input to one of the AND gates 310, and the output of the AND gate is input to the clock input A of the binary counter 304. The binary binary counter 304 starts counting up using the system clock 339 after the bus acquisition request generation permission signal 340 (179 in FIG. 1) becomes invalid (Hi).
29- Start the process. Output QA of binary pinary counter 304
Since ~QD are all input to the NAND gate 309, the NAND gate 309 makes the output valid (LO) when all the outputs QA-QD become Hi. The output of the NAND gate 309 is the counter reset signal (A) 35
3 and is input to the A channel of the selector 308. Also, the counter reset signal (A) 353 is the AND gate 3
Since it is the other input to the binary counter 304, when the counter reset signal (A) 353 becomes valid (Lo), the output of the AND gate 310 is always Lo and does not output a clock to the binary counter 304. Decoder 305 decodes write signal 331 from main processor 115 and address bus 332. The output of the decoder 305 is input to the B channel of the selector 308 as a counter reset signal (B) 354. The decoder 306 decodes the write signal 331 from the main processor 115 and the address bus 332, and if the operation result is valid, makes the signal to the flip-flop 307 -30- valid (Lo). The flip-flop 307 latches a specific bit 334 of the data path when the signal becomes invalid (Hi), and uses this as a selection signal 356. If the flip-flop 307 is reset, the selection signal 3
56 becomes LO level, and when flip-flop 307 is set, the selection signal 356 becomes Hi level. The selection signal 356 output from the flip-flop 307 is input to the selector 308, and the selector 308 receives the selection signal 3.
56 is at LO level, the counter reset signal (A) 353 input to the A channel is used as the counter reset signal 3.
55, if the selection signal 356 is at LO level, the counter reset signal (B) 354 input to the B channel is output as the counter reset signal 355. The counter 110 in FIG. 1 resets the contents of the counter when the counter reset signal 174 (355 in FIG. 3) becomes valid (Lo). Therefore, if the flip-flop 307 is set by a program, the counter reset signal 174 (355 in FIG. 1) will not be generated until the decoder 305 is accessed for writing and the counter reset signal (B) 354 is output. Therefore, the bus acquisition request generation permission signal 179 that was once invalidated by the comparator 111 remains invalid until the main processor 115 performs write access to the decoder 305 and resets the contents of the counter 110. It becomes possible to continue acquiring buses for an arbitrary period of time. The decoder 311 is the main processor 115
The write signal 331 from the address bus 332 is decoded, and if the operation result is valid, the flip-flop 32 is decoded.
Enable the signal to 1 (Lo). flip flop 3
21 latches the specific bit 335 of the data path when the output signal becomes invalid (Hi), and uses the contents as the bus acquisition request selection signal 357-1 (FIG. 1: 178-1) in FIG. Negative logic AND gate 123 and inverter 1
Enter 24. Similarly, the pair of decoder 312 and flip-flop 322 is the negative logic AND gate 1 of FIG.
The bus acquisition signal 357-2 (FIG. 1: 178-2) input to the bus acquisition signal 33 and the inverter 134 is connected to the negative logic AND gate 143 of FIG. and inverter 144
bus acquisition request selection signal 357-3 (first
178-3) in FIG. 7, the set of decoder 314 and flip-flop 324 is
3 and inverter 154, respectively. When initializing the bus acquisition control circuit, the flip-flop 32
1, 322, 323, and 324 to the reset state or set state, the bus master 10 in FIG.
1 to 104 bus acquisition request candidate signals 161-1 to 161
-4 is the flip-flop 321, 322, 323,
324 is in the reset state, that is, at Lo level, the flip-flop 32 is sent to the negative logic OR gate 106.
1, 322, 323, and 324 are set, that is, H
If it is at i level, it is output to OR gate 107 of negative logic. The following explanation assumes that the flip-flops 321 and 3-33-22 have been reset. The bus master 101 and the bus master 102 enable the bus acquisition request candidate signals 161-1-161-2 almost simultaneously (LO
), the signals are passed through the negative logic AND gates 123 and 133, respectively, and inputted to the negative logic OR gate 107 as 162-1 and 162-2, respectively. In addition, the outputs 163-1 and 163- of the negative logic AND gates 122 and 132
2 remain invalid (Hi). The output of the negative logic OR gate 107 passes through the negative logic AND gate 113 and the negative logic OR gate 112 to the main processor 1.
This becomes a bus acquisition request signal 167 to 15. On the other hand, assuming that the bus master 101 in FIG. 1 is a device that performs synchronous DMA transfer, the bus acquisition request selection signal 178-1 is set to Hi.
If set to the level, the bus acquisition request candidate signal 161-1, which is enabled (Lo) by the bus master 101, passes through the negative logic AND gate 122, the negative logic OR gate 106, and the same 112, and becomes input to the main processor 115. , the register 109, the counter 110, the comparator 111, and the negative logic AND gate 113.
can freely enable the bus acquisition request signal. FIG. 4 is a timing chart showing the operation of the bus acquisition control circuit when the flip-flop 307 of FIG. 3 is set to Lo level and the counter 110 is reset by the counter reset signal (A) 353. FIG. 5 is a timing chart showing the operation of the bus acquisition control circuit when the flip-flop 307 is set to Hi level and the counter 110 is reset by the counter reset signal (B) 354. Each signal in FIGS. 4 and 5 will be explained. rCLK is the system clock of the multi-bus system, rAS* is the address strobe signal, rDSACKX*J is the data transfer response signal, and r
ADD" is an address bus, rDATA is a data path, and rWR*J is a write signal from the main processor 1l5. "aSet" is a register latch signal, and corresponds to 172 in FIG. 1 and 351 in FIG. 3-35, respectively. "rathru" is a permission signal for generating a bus acquisition request, and corresponds to 179 in FIG. 1 and 340 in FIG. 3, respectively. ``rarrst*'' is a counter reset signal, and the first
This corresponds to 174 in the figure and 355 in FIG. 3, respectively. r
aregJ is the maximum number of bus acquisitions, and is 173 in Figure 1.
corresponds to racnt" is the total number of bus acquisitions, and corresponds to 176 in FIG. "abr*" is a bus acquisition request signal sent from the bus acquisition control circuit to the main processor 115, and corresponds to 167 in FIG. rabr*
(1) J is a bus acquisition request signal sent from the bus master 101 in FIG. 1 to the bus acquisition control circuit, and 161-1 in FIG.
and 231-1 in FIG. 2, respectively. rabr* (2) J is a bus acquisition request signal from the bus master 102 in FIG. 1 to the bus acquisition control circuit, and corresponds to 161-2 in FIG. 1 and 231-2 in FIG. 2, respectively. rabr* (3) J is a bus acquisition request signal sent from the bus master 103 to the bus acquisition control circuit in FIG.
This corresponds to 161-3 in the figure and 231-3 in Fig. 36-2, respectively. rabr* (
4) J is a bus acquisition request signal from the bus master 104 in FIG. 1 to the bus acquisition control circuit, and corresponds to 161-4 in FIG. 1 and 231-4 in FIG. 2, respectively. rabg*”
are bus grant signals sent from the main processor 115 to the bus acquisition control circuit, and correspond to 168 in FIG. 1 and 233 in FIG. 2, respectively. rarbg* (1) J is a bus permission signal sent from the bus acquisition control circuit in the engineering drawing to the bus master 101, and corresponds to 169-1 in FIG. 1 and 232-1 in FIG. 2, respectively. rarbg* (2) J is a bus grant signal sent from the bus acquisition control circuit in FIG. 1 to the bus master 102, and corresponds to 169-2 in FIG. 1 and 232-2 in FIG. 2, respectively. rarbg*(3)'' is a bus permission signal sent from the bus acquisition control circuit in FIG. 1 to the bus master 103, and corresponds to 169-3 in FIG. 1 and 232-3 in FIG. 2, respectively. rarbg'k (4) J is a bus permission signal sent from the bus acquisition control circuit in FIG. 1 to the bus master 104, and corresponds to 169-4 in FIG. 1 and 23-37-2-4 in FIG. 2, respectively. . "abaCk*" is a bus grant response signal from the bus acquisition control circuit to the main processor 115, and corresponds to 171 in FIG. rabac
k* (1) J is a bus grant response signal from the bus master 101 in FIG. 1 to the bus acquisition control circuit, and 17 in FIG.
Corresponds to 0-1. raback* (2)” is the bus master 10 in Figure 1.
2 to the bus acquisition control circuit;
This corresponds to 170-2 in FIG. raback* (3
)J is a bus grant response signal from the bus master 103 in FIG. 1 to the bus acquisition control circuit, and corresponds to 170-3 in FIG. raback*(4)'' is a bus grant response signal from the bus master 104 in FIG. 1 to the bus acquisition control circuit, and corresponds to 170-4 in FIG. "Total number of bus acquisitions of counter 110 racnt" (Figure 1: 176)
and the maximum number of bus acquisitions rareg” (Figure 1: 173)
is already zero, and the flip-flop 307 in FIG.
are set to the reset state. The initial main processor pass cycle 38 in FIG.
32 decode address (401 in FIG. 4) and the write signal 331 from the main processor 115, the first
The register latch signal 351 to the register 109 in the figure is enabled (Lo). The register 109 in FIG.
t'' (Figure 1: 172) is the maximum bus acquisition number raregJ (Figure 1: 17).
3) to latch. Here, "2" is latched as the maximum number of bus acquisitions, and from this point on, the bus acquisition {q request generation permission signal ratru'' (Figure 1: 179)
becomes valid (LO). In “TO” in Figure 4, the first
Bus master 101 and bus master 102 in the figure each have a bus acquisition request redemption code rabrl (1)J (Figure 1: 1
61-1) and rabrl(2)J (Figure 1: 161-
2) is enabled (L○), the bus acquisition request code 1'abr* of 115 is sent to the main processor (Figure 1:
167) is enabled (Lo). Next, in Figure 4, “
As shown in "T1", the bus permission signal "RABG*" (168 in FIG. 1) from the main processor 115 is enabled (Lo), and the bus master 101 is sent via the bus request daisy chain 105 in FIG. bus permission signal rarbg'l'(1)'' (Figure 1:
169-1) is enabled (Lo). “T” in Figure 4
2, the bus master 101 in the construction drawing sends an address strobe signal rAs*J (Figure 1: 1'80) and a bus transfer response signal rDsACKX* (Figure 1: 18).
1) and the bus permission response signal “BGACK*” (Figure 1: 1
68) are both disabled (Hi), the bus permission response signal raback* (1) J (Figure 1: 170-1) is enabled (Lo), and the bus master 1
start a bus cycle. In Figure 4, bus master 10
411 and 412 are transferred during execution of one bus cycle. 412, the bus master 101 sends the bus permission response signal raback* at "T3" in FIG.
(1) J (FIG. 1 = 170-1) is disabled (Hi) to notify the main processor 115 of abandonment of the bus cycle. At this time, the bus permission response signal ra to the main processor 115 is
At the rise of "baCk*" (FIG. 1: 171), the total number of bus acquisitions "acnt,1 (
Figure 1: 176) is added by 1. During this time, while the bus master 101 was acquiring the bus, a pending state of a bus request by the bus master 102 occurred, so the main processor 115 again issued the bus permission signal "abg*" (FIG. 1: 1).
68) is enabled (Lo) at "rT2a" in FIG. 4, and the bus master 102 is waiting for the bus master 101 to relinquish the bus. Bus master 101 at “T3” in FIG.
As a result of the bus abandonment, the bus cycle of the bus master 102 is started at "T4" in FIG. In FIG. 4, 413 is transferred while the bus master 102 is executing a bus cycle. 413, the bus master 102 sends the bus permission response signal raback+* at "T5" in FIG.
(2) Disable (Hi) J (i 170-2 in FIG. 1) to notify the main processor 115 of abandonment of the bus cycle. At this time, -41 to the main processor 115
- bus grant response signal ra. back*” (Figure 1 = 171
) rises, the total number of bus acquisitions ``aCnt'' (176 in Figure 1) of the counter 110 is incremented by 1, and the total number of bus acquisitions ``racnt'' (176 in Figure 1) is increased by 1.
) is the maximum number of bus acquisitions rareg” (Figure 1: 17
3), and the comparator 111 outputs the bus acquisition request generation permission signal ratru, 1 (Fig. 1: 179).
Disable (LO). From this point on, counting up is started by the system clock 339 of the binary pinary counter 304 in FIG. In the second bus cycle of the main processor 115, an instruction fetch operation is performed twice and rDATA4J is transferred between "T6" and "T7" in FIG. “T” in Figure 4
8'', the count-up by the binary pinary counter 304 in FIG. 3 is completed and the counter reset signal rar is
rst* (FIG. 1: 174) is output, and the total number of bus acquisitions racnt'' (FIG. 1: 176) is cleared to zero. From the time when the above-mentioned "racnt" is cleared to zero, the bus acquisition request generation permission signal "a-42-thru" (179 in FIG. 1) becomes valid (Hi). Between "T6" and "T7" in FIG. 4, the bus master 103 and the bus master 104 in FIG.
abr* (3) J (Fig. 1: 161-3) and ra
br* (4) J (Fig. 1: 161-4) and valid (
Lo), the negative logic AND gate 113 in FIG.
The bus acquisition request generation permission signal rat is one input of
hru” (Fig. 1: 179) is invalid (Lo), the output 165 of the negative logic AND gate 113 is invalid (H
i) remains the same. Therefore, the bus acquisition request redemption signal RABR* (167 in FIG. 1) to the main processor 115 does not become valid (Lo), and the main processor 115 does not relinquish the bus. The binary pinary counter 304 in FIG. 3 receives a bus acquisition request generation permission signal "athru" (FIG. 1:
179) becomes invalid (Hi), at "T8a" in FIG. 4, 16 clocks after the counter reset signal r
arrst*, + (Figure 1 = 174, Figure 3: 355
) is enabled (LO) and the bus acquisition request generation permission signal r
ath-43-ru” (Figure 1: 179) becomes valid (Hi) again. Immediately after the bus acquisition request generation permission signal rathr+g (FIG. 1: 179) becomes valid (H1), the bus acquisition request signal ``abrlJ'' (FIG. 1: 167) to the main processor 115 becomes valid (Lo). After that, bus cycles of bus master 103 and bus master 104 are executed.
The second bus cycle is as described in the fourth section. In the second bus cycle of the main processor 115, after performing the instruction fetch operation twice, at "T10" in FIG. 4, the decode address (506 in FIG. 5) of the address bus 332 is sent to the decoder 305 in FIG. and the write signal 331 from the main processor 115, the counter reset signal "arrst*" (174 in FIG. 1, 355 in FIG. 3) is enabled (Lo), the counter 110 is cleared to zero, and a bus acquisition request is generated. permission signal ratru
” (Figure 1: 179) is re-enabled (Hi) -44
− I am. This example differs from the example shown in FIG. 4 in that the counter 110 is cleared to zero due to the operation of the main processor 115. In order to reset the counter by the main processor 115 in FIG.
It is considered optimal to use an interrupt triggered by the rising edge of , from the perspective of reducing the burden on the main processor. [Effects of the Invention] According to the information device having the bus acquisition control method of the present invention described above, the main processor programmably controls the bus acquisition of the bus master, so that the main processor secures its own bus cycle. It is possible to avoid a significant decrease in program processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multi-bus master system according to the present invention. FIG. 2 is a block diagram of a bus request daisy chain of FIG. 1 according to the present invention. -45- FIG. A configuration diagram of a count control circuit. FIG. 4 is a timing chart example 1 showing the operation of the circuit of FIG. 1 according to the present invention. FIG. 5 is a timing chart showing the operation of the circuit of FIG. 1 according to the present invention. Figure 6 is a timing chart diagram showing the bus arbitration protocol of the main processor according to the conventional example; Figure 7 is a block diagram of a multi-bus system showing the input/output relationship of each signal in Figure 6. 8 is a block diagram of a multi-bus system showing the input/output relationship of each signal when there are multiple bus masters, FIG. 9 is a block diagram of a bus acquisition control circuit of conventional example 1, and FIG.
1 is a timing chart showing a bus arbitration protocol of the main processor when a bus request pending state occurs. FIG. 11 is a block diagram of a bus acquisition control circuit of conventional example 2. -46- Bus master: l01, 102, 103, 104, switch circuit: 120, 130, 140, 150, bus request daisy chain: 105, negative logic OR gate = 106
・107・108・112, Register: 109, Counter: 110, Comparator: 111, Negative logic AND gate:
113, Counter control circuit: 114, Negative logic AND gate: 122, 123, 132, 133, 142, 14
3.152.153, inverter: 124.134.1
44/154, negative logic AND gate: 201/202
・203, 204, 211, 212, 213, Inverter: 221, 222, 223, Decoder: 301, 30
2.306, flip-flop: 303.305.30
7. Binary pinary counter: 304, selector: 308
, NAND gate: 309, decoder = 311・312・
313, 314, inverter: 315, flip-flop: 321, 322, 323, 324, decoder 301
Address: 401/501, data transfer destination address 1
:402/502, data transfer destination address 47- address 2:403/503, instruction reading source address 1
:404/504, instruction reading source address 2:405
・505, address of decoder 305: 506, data transfer destination address 3: 406/507, data transfer destination address 4: 407/508, data 1: 411/511,
Data 2: 412/512, Data 3: 413/51
3. Instruction code 1: 414/514, instruction code 2:
415/515, arbitrary value = 516, data 4: 41
6/517, data 5:417/518, main processor: 701, bus master: 702, main processor = 801, bus master: 802/803/804/80
5. Bus acquisition control circuit: 806, negative logic OR gate:
901/902, negative logic AND gate: 903/90
4, 905, 906, 913, 914, 915, Inverter: 923, 924, 925, Negative logic OR gate:
1101, Negative logic OR gate: 1102, Negative logic AND gate: 1103, 1104, 1105, 1106
・1113/1114/1115, Inverter: 1123/1124/1125, NAND gate:
1131, Inverter: 1132, System Kurozuku:
CKL・339, address strobe signal: AS*・
180/724/824, data transfer response signal = DSA
CKX*・181・725・825, bus acquisition request signal: BR*・abr*・721・821・931・113
1.167, bus acquisition request candidate signal: abr* (1
)~abr*(4)・831-1~831-4・941
-1~941-4・1141-1~1141-4・16
1-1 to 161-4, 231-1 to 231-4, bus permission signal: BG*, abg*, 722, 822, 932,
l132/233, bus permission candidate signal: abg* (
1) ~abg* (4) ・832 -1~832-
4・942-1～942-4・1142-1～1142
-4・168・169-1～169-4・232-1～
232-4, bus permission response signal: BGACK* ・a
back* - 723・823・933・1133・
171, bus permission response candidate signal: aback ho (1)
~abaCk-49- * (4)・833-1~833-4・943-1~9
43-4 ・ 1143-1 to 1143-4 ・
170-1 to 170-4, bus acquisition request selection signal: 17
8-1~178-4・357-1~357-4, Register latch signal: aset・172・351, Maximum number of bus acquisitions: areg・173, Counter reset signal: arr'st'+'・174・355, Counting continuation/interruption signal; 175/352, total number of bus acquisitions:
acnt・176, bus acquisition request generation permission signal:
athru・179, selector selection signal: 356, write signal from main processor: WR*・331, address bus: ADD・332, data path: DATA
・333・334・335・336・337・338,
that's all

Claims (1)

[Claims] In an information device including a multi-bus master system including a main processor and a plurality of bus masters, a counter that counts the total number of bus acquisitions by the bus master;
a maximum bus acquisition count setting register that can be set by the main processor; a comparator that compares the value of the counter with the setting register; and a comparator that temporarily stops the bus master from acquiring the bus when the value of the counter reaches the value of the setting register. 1. An information device comprising a bus acquisition control circuit including means for holding the bus.