JPH0316091A - Semiconductor recorder - Google Patents

Abstract

PURPOSE:To execute the operation at a high speed by providing a current source by which a current value drawn out of a pair of word lines is varied in accordance with the potential of the pair of word lines on every pair of word lines, and drawing out a current from the pair of word lines by the current source. CONSTITUTION:A current source 22 by which a current value drawn out of pairs of word lines 4 - 7 is varied in accordance with the potential of the pairs of word lines is provided on every pair of word lines 4 - 7. That is, a discharge current of the word line at the time when the pairs of word lines 4, 5 are migrated from a selecting state to a non-selecting state is increased, and also, a drawing-out current from the pair of word lines migrated to the non-selecting state is decreased continuously. Accordingly, a fall of the word line is executed quickly, and also, after the word line is migrated from the selecting state to the non-selecting state, the potential of the word line does not float up. In such a way, the operation can be executed at a high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular to a RAM (random access memory) using bipolar transistors.
It is effective for use in word discharge circuits that discharge charges accumulated in word lines and memory cells.

[Conventional technology]

FIG. 11 is a circuit diagram showing a word line selection circuit and a word discharge circuit of a conventional semiconductor memory device disclosed in, for example, Japanese Patent Laid-Open No. 56-37884. An example is shown. In the figure, 1 and 2 are word line selection circuits using ECL (emitter-coupled logic) NOR circuits, and the word line selection signal X00XOI is sent to the word line selection circuit l, and the word line selection signal X10. X11 is input to the word line selection circuit 2, and the comparison reference potential 3 is input to the word line selection circuit 1.
．． It is given in common to 2.

MCOO, MCOI, MCIO. MCI1 is a memory cell, MCOO and MCOI are connected to the positive word line 4 and negative word line 5, MCIO and MCl1 are connected to the positive word line 6 and negative word line 7, and the memory cell MCOO
, MCIO is connected to bit line pair 8.9, memory cell MC
O 1 and MCI 1 are connected to bit line pair 10.11. In addition, BDo and BDI are bit cotton drivers, BDO is bit line pair 8.9, BDI is bit line pair 8.9, and BDI is bit line pair 8.9.
91 and 10.11, respectively, and both are controlled by the Y address control circuit 40. 12 is a constant current source connected to the negative side word line 5, 13 is a constant current source connected to the negative side word line 7, 14 is a word line pair 4.5, and 15 is a word line source connected to the word line pair 6, 7, respectively. Discharge circuit, 16.17 is word discharge circuit 14.1
5 is a constant current source commonly connected, and 30 is a read/write control circuit.

Next, we will explain the operation. For example, memory cell MCOO
To select word line pair 4.5, select “H”.
This is done by setting the bit line driver BDO to ++ level and activating the bit line driver BDO. To select word line pair 4.5, set both inputs XOO and XOI of word line selection circuit 1 to a level lower than reference standard potential 3, and set the input level of at least one of the plurality of inputs of other word line selection circuits 2. By setting the word line pair 4.5 to a level higher than the reference potential 3, only the word line pair 4.5 becomes selected at the "H" level.

Next, to select memory cell MCIO, at least one of the inputs XOO and XOI of word line selection circuit 1 is set to ``1{
I1 level, input XIO of word line selection circuit 2,
The word line pair 6.7 is set to the selected "H" level by setting both Xll to "L" level.

At this time, the next selected memory cell M. In order to quickly switch to C10, word line pair 4 becomes unselected.
．． It is necessary to lower the potential of 5 at high speed. The word discharge circuits 14 and 15 operate as a switch circuit that connects the common current source l6 and the negative side word line when the word line pair to which they are connected falls,
Since the word line pair transitioning from the selected state to the non-selected state is discharged using a large current, the potential thereof can be rapidly lowered. Further, the constant current source 1213 is a holding current source, and is for holding the memory contents of the memory cells MCOO and MCII.

[Problems to be Solved by the Invention] By the way, in a conventional semiconductor memory device, especially when the memory cells MCOO to MCII are constituted by saturated memory cells as shown in FIG. When transitioning to the non-selected state, as shown in FIG. 13, the word discharge circuit operates as a current switch, so the current drawn from the word line pair is rapidly turned off at the same time as the circuit is switched. It is known that the electric charge accumulated in the memory cell overflows to the word line, causing the potential of the word line pair to rise once.

If the word line potential rises again in this way, a double selection state will occur between the word line pair that will next transition from a non-selected state to a selected state, and read and write operations, especially write operations, will be inhibited, and write operations will be inhibited. There are problems such as it takes a long time to write, and writing errors occur.

The present invention has been made in order to solve the problems of the conventional ones as described above, and it is possible to rapidly lower the potential of a pair of word lines transitioning from a selected state to a non-selected state, and
It is an object of the present invention to provide a semiconductor memory device that can prevent the potential of a word line pair from rising again after transitioning to a non-selected state.

[Means to solve the problem]

In the semiconductor memory device according to the present invention, a current source is provided for each word line pair, and the current value drawn from the word line pair changes depending on the potential of the word line pair.

[Function] By providing the current source as described above, the semiconductor memory device of the present invention increases the word line discharge current when the word line pair transitions from the selected state to the unselected state, and also increases the word line discharge current when the word line pair transitions from the selected state to the unselected state. Since the current drawn from the transitioning word line pair is continuously reduced, the word line falls rapidly and the word line potential after the word line transitions from the selected state to the non-selected state There is no lifting and high-speed operation is possible.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention. In the figure, 1 and 2 are word line selection circuits using ECL (emitter coupled logic) NOR circuits, and word line selection signals X00 and XOI are Word line selection signals XIO and Xll are respectively input to word line selection circuit 1 and word line selection circuit 2, and comparison reference potential 3 is commonly applied to word line selection circuits 1 and 2. MCOO
, MCo 1, MCI O, MCI 1 are memory cells, MCOO, MCO 1 are connected to the positive word line 4 and negative word line 5, and MCIO, MCI 1 are connected to the positive word line 6.
and negative side word line 7, MCOO and MCIO are connected to bit line pairs 8 and 9, and MCOI and MCI1 are connected to bit line pair 10 and 11, respectively.

In addition, BDO and BDI are focus line drivers, and BD
O to bit line pair 8.9, BDI to bit line pair 10.1
1, and both are controlled by the Y address control circuit 40. 14 and l5 are word discharge circuits, which are connected to the resistor l8 and the PNP transistor 19, respectively, and from the resistor 20 and the PNP transistor 21, and the PNP transistors 19 and 21 are connected to the negative side through the resistor 18 and 20, respectively. A power supply is connected to the word lines 5 and 7, a base is connected to the constant voltage generating circuit 22, and a collector is connected to the negative power source. Note that 30 is a read/write control circuit.

Next, the operation will be explained. To select word line pair 4 and 5, input XOO. of word line selection circuit 1 is used. Set both XOl to “L” level. Next, to select the word line pair 6.7 and make the word line pair 4.5 unselected, at least one of the inputs XOO and XOI of the word line selection circuit 1 is set to ``H''.
11 level, input XIO of word line selection circuit 2,
Set both Xll to t+ L II level. The potential of word line 4.56.7 and the current flowing through word discharge circuit 14.15 at this time are shown in FIG.

The current flowing through the word discharge circuit 14 (los
s) is the base structure of the PNP transistor ξ for simplicity.
Assuming that the voltage between the vines (V.) is constant, the potential (VIIEF) given by the constant voltage generation circuit 22, the potential of the word line 5 (■D), and the resistance value of the resistor 18.19 of the word discharge circuit. (Rots) is obtained from the following equation.

The current flowing through the power 1 discharge circuit l4 is
As shown in the figure, when the word line pair 4 and 5 are in the selected state, the value is the maximum value, gradually decreases as the pair of word lines 4 and 5 go into the non-selected state, and becomes the minimum value in the non-selected state. This minimum value is set to a current value necessary to hold the memory contents of the memory cell when the word line pair is in a non-selected state. In this way, the word discharge circuit causes a large current to flow in the initial stage when the word line pair transitions from the selected state to the unselected state, and as the word line potential approaches the unselected potential, the current value decreases. The potential of the word line pair transitioning to the unselected state changes rapidly at the beginning of falling, and gradually changes as it approaches the unselected state.

As described above, according to this embodiment, the word discharge circuit is controlled by the voltage difference between the potential of the word line and the potential given by the constant voltage generation circuit, and is constructed of a current source that continuously changes the current value. As a result, it is possible to rapidly and stably discharge the potential of the word line that changes from selected to unselected state, and to prevent the potential of the word line pair from rising again after the transition to the unselected state. can.

FIG. 3 shows a further improvement of the circuit shown in FIG. 1, in which a delay element 51 consisting of a capacitor 23, 24 and a resistor 25, 26 is added to the word discharge circuit 14, l5.
．． 52 respectively. That is, one end of the capacitor 23.24 is connected to the negative word line 5.7, and the other end is connected to the PN
Connect to the base of P transistor 19.21, PNP
The bases of l-transistors 19 and 21 are connected to resistors 25 and 25, respectively.
．． It is connected to the constant voltage generation circuit 22 via 26.

Next, the operation of the circuit shown in FIG. 3 will be explained. Fourth
The figure shows the potential and current at each contact point when the word line pair 4, 5 transitions from the selected state to the unselected state, and the word line pair 6.7 transitions from the unselected state to the selected state. Word discharge circuit 14 connected to negative side word line 5
, the current (loss
) is the voltage between the base and the terminal (V.) of the PNP transistor l9, the Hase potential (vcN.rL) of the PNP transistor l9, the potential of the negative side word line 5 (VW.), and the voltage of the word discharge circuit. Resistance value of resistor l8 (R
D+s) is obtained from the following formula.

Here, considering the voltage difference (Vows) between the potential (VW.) of the negative side word line 5 and the base potential (VCIITL) of the PNP transistor 19, the above equation can be rewritten as follows.

Considering that the current amplification factor of the PNP l-transistor is sufficiently large, this difference voltage (Vows) is given by the potential (VW-) of the negative side word line 5 and the constant voltage generation circuit 22? It changes with a delay of a time (δt) determined by the values of the capacitor 23 and the resistor 25 with respect to the potential difference with the potential (■■,). Therefore, the current (I.s) flowing through the negative side word line 5 changes with a delay of the delay time (Δt) compared to the case shown in FIG. At this time, the falling time of word line pair 4.5 is longer than the first line due to the large amount of current flowing at the falling edge.
This is faster than the circuit shown in the figure. Regarding the rise of the word line pair 6.7, in the circuit shown in Figure 1, the word line discharge current starts flowing in the middle of the rise of the word line, so the rising waveform is blunted, whereas the word line discharge current flows. Because there is a delay in the start-up waveform, there is no rounding of the rising waveform, allowing for faster operation.

In both of the above embodiments, a word discharge circuit is used to provide a holding current when the word line is not selected, but as shown in FIG. Even if it is provided separately, similar effects can be obtained.

In addition, as shown in Figure 6, the output of the word discharge circuit is connected to the positive word line using resistors 43, 44, etc., and the charges overflowing from the memory cells to the positive word line are also discharged at the same time. You can also make it look like this.

Further, in each of the above embodiments, an example was shown in which the current value whose output current value is controlled by the potential difference was controlled using a PNP transistor and a resistor, but this current source is shown in FIGS. 7 to 10, for example. As shown in pMOS61 only, or pM
The structure may be made of the OS 61 and the resistor 62, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, a current source whose current value drawn from the word line pair changes depending on the potential of the word line pair is provided for each word line pair, and the current source Since the current is drawn from the word line pair using This has the effect of providing something that can perform the movements.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the main parts of a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a diagram showing the operation of the circuit of FIG. 4 is a diagram showing the operation of the circuit of FIG. 3, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. FIG. 10 is a diagram showing another embodiment of the present invention, FIG. 11 is a circuit diagram showing a conventional semiconductor memory device, FIG. 12 is a circuit diagram showing a saturated memory cell, and FIG. 13 is a conventional semiconductor memory FIG. 3 is a diagram showing the operation of the device. In the figure, 1 and 2 are word line selection circuits, 45, 6.7
is word line, 8, 9, 10.11 is bit line, 14.1
5 is a word discharge circuit, 18.20 is a resistor,
19.21 is a PNP transistor, 22 is a constant voltage generation circuit, 23.24 is a capacitor, 25.26 is a resistor, 30
40 is a read/write control circuit, 40 is a Y address control circuit, MCOO, MCOI. MCIO and MCI1 are memory cells, and BDO and BDI are bit line drivers. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A memory cell is connected to a plurality of word line pairs, a plurality of bit line pairs, and the intersection of each word line pair and bit line pair, and the potential of the word line pair is switched according to the selected/unselected state. In a semiconductor memory device that performs read and write operations, a current is connected to one or both of a pair of word lines directly or through a delay element, and the value of the current drawn from the pair of word lines is controlled according to the potential of the word line. A semiconductor memory device characterized in that a source is provided for each word line pair.