JPH0316065Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an impedance detection circuit, and by using a differential amplifier and setting its operating voltage to a predetermined value, the impedance of the SEPP circuit load can be detected with high sensitivity and reactance components can be detected. It is an object of the present invention to provide an impedance detection circuit that can reliably detect load impedances including load impedances.

Conventionally, as a circuit for detecting changes in load impedance in a complementary SEPP circuit,
There is a circuit that forms a bridge whose sides are each emitter resistance of an NPN transistor or a PNP transistor, a load impedance, etc., and detects when the equilibrium condition of the bridge is no longer satisfied due to a change in the load impedance. This device had the disadvantage that it could not detect a change in impedance unless the load impedance changed by a relatively larger amount than a predetermined value that satisfies the equilibrium condition, and the detection accuracy was poor.

Therefore, the applicant proposed the following circuit in order to eliminate this drawback.

FIG. 1 shows a circuit diagram of an example of an impedance detection circuit previously proposed by the applicant. In the figure, transistor Q ₂ is turned off only when positive direction input is applied to transistors Q ₁ and Q ₂ , and as a result, resistors R ₁ , R ₃ , R ₄ , load impedance (input signal source V _S is In the case of a signal, the speaker R _L constitutes a bridge and performs impedance detection operation. The equilibrium condition of the bridge is R ₁ ·R ₄ =R ₃ · _RL , and each resistance value is selected so that this equilibrium condition is satisfied when the load impedance _RL is a predetermined value. When this equilibrium condition is established, the potential difference between the points is zero, so the differential amplifier _A1 is in the off state, and no output is taken out to the output terminal 1, so that It can be detected that the load impedance R _L is at a predetermined value.

On the other hand, when the load impedance R _L becomes smaller than the above predetermined value, (potential at the point) < (potential at the point)
Therefore, differential amplifier A ₁ is activated,
An output is taken out to the output terminal 1, thereby making it possible to detect that the load impedance R _L has become smaller than a predetermined value.

In this case, there is a differential amplifier A ₁ between the points.
is provided to detect the potential difference therebetween, so that a minute potential difference between points (that is, a minute change in the load impedance R _L ) can be detected with high accuracy.

Here, consider the load line of transistors Q ₁ and Q ₂ in the case where the load impedance R _L is a resistance including pure resistance and reactance components.
FIG. 2 shows the load lines of transistors Q ₁ and Q ₂ with the horizontal axis representing the potential V ₀ and the vertical axis representing the emitter current I _E of the transistor Q ₁ . In the same figure, the load impedance R _L of curves a and b is the absolute value.
The load line of transistors Q ₁ and Q ₂ at a frequency where the voltage and current phase shift is 45° at 8Ω,
Straight lines c and d are the load lines when the load impedance R _L is pure resistance 8Ω and 4Ω, respectively.
Those in the middle, third and third quadrants are transistors.
Q ₁ , those in the fourth quadrant and those in the fourth quadrant are the respective load lines of the transistor Q ₂ .

In the circuit shown in Figure 1, the load impedance R _L changes due to a change in the emitter current I _E of the transistor Q ₁ .
Since the configuration detects
You only need to think about the load line in _Q1 .

By the way, if the bridge is configured so that the load impedance R _L is an element whose absolute value is 8Ω and includes a reactance component and satisfies the above formula,
When the load line a of the transistor Q ₁ is in the shaded area in FIG. 2, the differential amplifier A ₁ detects the load impedance R _L as being lower than the actual 8Ω. In particular, when the output voltage V ₀ is a low value (that is, the shaded area in the first quadrant near the vertical axis in Figure 2),
Although the load impedance R _L is actually 8Ω, it is detected as being around 0Ω.

As described above, the circuit shown in FIG. 1 has a problem in that when the load impedance R _L is an element containing a reactance component, the differential amplifier A ₁ malfunctions and the actual impedance change cannot be detected accurately.

The present invention solves the above problems, and one embodiment thereof will be described below with reference to the drawings.

FIG. 3 shows a circuit diagram of an embodiment of the impedance detection circuit according to the present invention. In the figure, the same components as those in FIG. In the figure, NPN transistor Q ₃ has its base connected to a point and the non-grounded terminal of load impedance R _L , and its emitter
It is connected to the emitter of the NPN transistor _Q4 , while being grounded via a diode _D2 and a resistor _R5 , and its collector is connected to the power supply voltage +V _CC terminal via a resistor _R6 . The transistor Q ₄ has its base connected to the point, while the transistor _{Q 4 is}
It is connected to the emitter of Q ₂ , and its collector is connected to the power supply voltage +V _CC terminal via resistor R ₇ . Differential amplifier A ₂ with transistors Q ₃ and Q ₄
is configured.

On the other hand, the base of PNP transistor _Q5 is connected to the collector of transistor _Q4 , and
It is grounded via a resistor _R10 , its collector is grounded, and its emitter is further connected to the power supply voltage +V _CC terminal via a resistor _R8 . The base of the PNP transistor Q ₆ is connected to the collector of the transistor Q ₃ , which is connected to the output terminal 1 and the resistor
It is grounded via R ₉ and its emitter is connected to the emitter of transistor Q ₅ .
A differential amplifier _A3 is configured by transistors _Q5 and _Q6 .

Generally, the emitter resistors R ₁ and R ₂ are selected to have equal values, respectively, while the transistors Q ₁ and Q ₂ biased to class AB, which is close to class B, by the voltage sources E ₁ and E ₂ have Since an idle current of several tens of mA flows when there is no signal, a potential difference of several tens of mV is generated between both ends of the resistors R ₁ and R ₂ when there is no signal. Therefore, if the resistor R ₁₁ is not connected, the potential at the point will be several tens of mV higher than that at the point, and among the transistors Q ₃ and Q ₄ that make up the differential amplifier, transistor Q ₄ will be turned on, and the transistor Q ₃ is close to off. For this reason, when looking at the collector current of transistor _Q4 , it becomes impossible to obtain a sufficient amount of change in the increasing direction. Therefore, in this example, the resistor
By connecting R ₁₁ , its resistance value can be changed to resistor R ₃
If you select a value equal to
The collector currents of Q ₃ and Q ₄ are made approximately equal when there is no signal. In this case, it goes without saying that the resistance value of the resistor _R11 may be selected to be smaller than that of the resistor _R3 to reduce the collector current of the transistor _Q3 .

Also, the resistance values of resistors R ₅ , R ₆ , and R ₇ are
A ₂ is selected to operate only when the absolute value of the output voltage V ₀ in the positive or negative direction is equal to or higher than the voltage V ₁ shown in the second diagram.

Next, the operation of this impedance detection circuit will be explained. When the output voltage V ₀ of the complementary SEPP circuit consisting of transistors Q ₁ and Q ₂ is negative, the current flowing through the resistor R ₅ caused by the diode D ₂ becomes zero, so the differential amplifiers A ₂ and A ₃ are turned off (i.e. (in FIG. 2, the load line a is in the fourth quadrant), the differential amplifier _A2 does not perform an impedance detection operation.

Next, when the output voltage V ₀ is positive, the diode D ₂ turns on as it swings in the positive direction, and the current flowing through the resistor R ₅ gradually increases. In this case, the resistance
Since the resistance values of R ₅ , R ₆ , and R ₇ are selected as described above, when the output voltage V ₀ reaches the voltage V ₁ , the differential amplifier A ₂ enters the operating state and performs an impedance detection operation. Amplifier A ₂ is now operational,
The voltage across each of resistors R ₆ and R ₇ is the voltage across transistors Q ₅ and Q ₆
When the voltage is sufficient to turn on, amplifier _A3 becomes operational.

When the output voltage V ₀ is positive, the resistor R ₁₁ is equivalent to being connected in parallel between the points, so the resistors R ₁ , R ₃ , R ₄ and the load impedance R _L are connected on each side, respectively. A bridge is constructed, and its equilibrium condition is the same as the above equation. In this case, if the load impedance R _L is a predetermined value and the bridge is balanced, a predetermined voltage is taken out at the terminal 1.

On the other hand, when the load impedance R _L becomes smaller than the predetermined value, the potential at the point becomes higher than that at the point, and as a result, a voltage higher than the voltage taken out at terminal 1 is taken out at the above-mentioned equilibrium, and the impedance Changes in can be detected.

In this case, the amplifier _A2 does not perform impedance detection unless the output voltage _V0 is equal to or higher than the voltage _V1 .
Since the operating state occurs only when the load line a is in the cross-hatched area surrounded by the line e of V ₁ , as is clear from the figure, the load impedance R _L includes a reactance component and its absolute value is For example, in the case of 8Ω, it is only detected as a resistance within the range of about 8Ω to 5Ω, and it is not detected as an extremely different resistance value near 0Ω as in the circuit shown in FIG.

Note that the resistor _R10 is a bias resistor that allows a slight bias current of the transistor _Q5 to flow and makes the collector current of the transistor _Q6 zero when the bridge is balanced.

As described above, the impedance detection circuit according to the present invention includes first and second resistors connected in series between the emitter of the NPN transistor and the ground, and a common connection point between the first and second resistors. A differential amplifier with one input terminal connected to the terminal and the other input terminal connected to the common connection point of the emitter resistors, and the output voltage taken out to the common connection point of the emitter resistors only in the positive or negative direction. A resistor is connected between the power supply terminals of the differential amplifier so that the differential amplifier operates only when the absolute value of Since the load impedance detection signal obtained by detecting the potential difference between the resistance and the common connection point is extracted from the differential amplifier, the load impedance can be detected with higher sensitivity than conventional impedance detection circuits. Moreover, the differential amplifier does not perform impedance detection operation unless the output voltage exceeds a certain value, so when a load containing a reactance component is connected, the load is detected at the actual value as in the circuit proposed earlier by the applicant. By using it in the impedance detection circuit of a power amplifier that automatically switches the power supply voltage according to the size of the load impedance, it is not detected as a value that is more drastically different from the current value, and when used with a low load impedance. It also has the advantage of producing a small amount of heat and being able to construct a compact, lightweight, and inexpensive power amplifier.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an example of the circuit previously proposed by the applicant, Figure 2 is the load line of the SEPP circuit transistor when each load impedance is connected, and Figure 3 is an example of the circuit of the present invention. It is a circuit diagram. 1... Impedance detection signal output terminal, Q ₁ ,
Q ₂ ... SEPP circuit transistor, Q ₃ ~ _{Q 6} ... Differential amplifier transistor, R ₁ , R ₂ ... Emitter resistor, R ₃ , R ₄ ... Impedance detection resistor, R ₅
~ _R7 ...Resistance for setting differential amplifier operating voltage, R _L ...
...Load impedance.

Claims (1)

[Scope of utility model registration request] The load impedance of a complementary SEPP circuit in which the emitters of an NPN transistor and a PNP transistor are commonly connected via their respective emitter resistors, and a load impedance is connected between the common connection point of the emitter resistors and the ground. In the circuit for detecting the A differential amplifier whose input terminals are connected and whose other input terminal is connected to a common connection point of the emitter resistors, and an output voltage taken out to the common connection point of the emitter resistors that can only be output in the positive or negative direction. a resistor connected between the power supply terminals of the differential amplifier so that the differential amplifier operates only when the absolute value is equal to or higher than a predetermined voltage; An impedance detection circuit configured to extract from the differential amplifier a detection signal of the load impedance obtained by detecting a potential difference between the resistors and a common connection point of the resistors.