JPH0315983A - Construction of logical circuit - Google Patents

Abstract

PURPOSE:To enable the fine conversion of the kind of a gate for an objective package system in which there are many gates different in delay through the use of the same logical function by generating a desired logical circuit by replacing the gate of standard delay successively into a high-speed gate until a path delay condition is fulfilled. CONSTITUTION:A logical macro name 201 to express the kind of a logical macro and the path delay condition between the input/output terminals 204 to 207 to be generated automatically from the logical macro are inputted, and a model logical circuit 300 defined by the gates 301 to 304 of the standard delay of the logical macro is retrieved from a logical macro library as considering the logical macro name 201 a key. Then, the desired logical circuit is generated by replacing the gates 301 to 304 of the standard delay successively into the high-speed gate until the path delay condition is fulfilled in this model logical circuit 300. Thus, the fine gate kind conversion becomes possible by the same logical function according as the number of the gate of the different delay increases.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a logic circuit, and particularly to a method for manufacturing a logic circuit from a logic macro. [Conventional technology] In recent years, with advances in semiconductor technology, logic devices have become larger and larger.
As logic design becomes more complex, reducing the number of man-hours required for logic design and improving logic design quality have become important issues. One of the most effective methods to solve this problem is logic generation, and one of the techniques for logic generation is the logic macro expansion method, which generates logic circuits from logic macros. This logic macro expansion method registers a template logic circuit of a logic macro in a logic macro library.
This method generates logic by referring to this logic macro library. Here, a model logic circuit is defined by a combination of gates. On the other hand, in one implementation system, there are multiple gates with the same logic function but different delays. Therefore, considering the gate delay, the number of model logic circuits becomes extremely large. Therefore, in order to solve this problem, a model logic circuit is defined using standard delay gates, and when a logic circuit with a different delay is required, the standard delay gate is replaced with a gate with a different delay to create the desired logic. A gate type conversion method is used in which the circuit is modified. Such a gate type conversion method is discussed in the 30th National Conference of the Information Processing Society of Japan (1985), pages 1957 to 1958. [Problems to be Solved by the Invention] The above gate type conversion method targets implementation systems with at most three gates with the same logic function but different delays, and requires manual specification of the delay classification to be converted and the conversion target range. Gate type conversion is performed. Here, there are three types of delay classification: high delay, normal delay, and low delay, and in gate type conversion, since the model logic circuit is defined by a normal delay gate, either high delay or low delay is specified. Also, the range to be converted is either the entire logic circuit or a specific most output gate of the logic circuit. Therefore, the above gate type conversion method is
The problem was that as the number of gates with the same logic function but different delays increases, fine-grained gate type conversion becomes impossible. The objective is to provide a method that allows fine-grained gate type conversion for implementation systems with a large number of gates. [Means for Solving the Problems] In order to achieve the above object, the present invention provides a logic macro name indicating the type of logic macro and a bus delay condition between input and output terminals of a logic circuit automatically generated from the logic macro. input (Means 1), search the logic macro library for a model logic circuit defined by the gate of the standard delay of the logic macro using the logic macro name as a key (Means 2);
In this model logic circuit, a desired logic circuit is generated by sequentially replacing standard delay gates with high-speed gates until the bus delay condition is satisfied (means 3). [Operation] In the above means, means means input processing, means 2 represents logic circuit search processing, and means 3 represents gate type conversion processing. [Example] Hereinafter, an example of the present invention will be explained in detail with reference to the drawings.
FIG. 1 is a flowchart of logical macro expansion processing based on the present invention. Based on this figure, we will explain the steps of logical macro expansion processing one by one. Step 100: In this step, logic macro description data is input from the functional logic file 120. The logic macro description data consists of the logic macro name and the path delay conditions between the input and output terminals of the logic circuit automatically generated from the logic macro. Figure 2 shows an example of logical macro description data. In the logic macro description data 200, the logic macro name 201 indicates that the logic macro type is HALU (half adder), and the fanout number 202 of the output terminals indicates the output terminals 206, 207.
This means that the fan-out numbers of are 3 and 2, respectively, and that the upper limit value of the bus delay of each path element between the input terminal 204 and the output terminal 207 of the delay specified path 203 is 9 ns. Here, the fanout number of the output terminal is 20
2 and day-delay designated bus 203 are bus day-delay article 5! Step 101: This step uses the logic macro name input in step 100 as a key to search the logic macro library 21 for a template logic circuit of the logic macro. Figure 3 shows the template logic circuit of Ronzui macro name 201.
In the model logic circuit 300, gates 301 to 304
is a standard gate (a gate with the largest delay among gates with the same logic function).

Step 102: This step extracts all bus elements of the delay specified path input in step 100 in the model logic circuit searched in step 101. In the model logic circuit 300, the delay specification bus 20
Path elements 3 are bus elements 305 and 306. Step 103: This step determines whether there is an unprocessed path element among the path elements extracted in step 102. If there is an unprocessed bus element, the process advances to step 104;
If not, the process branches to step 112. Step 104: This step selects one unprocessed bus element among the bus elements extracted in step 102. Step 105: This step initializes the path element pointer used in step 108 to O. Step 1
06: This step refers to the gate table 130, adds the delays of each gate on the bus list selected in step 104, and calculates the bus delay of the relevant path element. Figure 4 shows the contents of the gate table. The gate table 30 is a table that describes symbols, logic functions, gate names, and gate type parameters (fan-out number, delay). Step 107: This step determines whether the bus delay calculated in step 106 is less than or equal to the upper limit value of the delay specified bus input in step 100. If it is less than the upper limit, the process branches to step 103, and if it exceeds the upper limit, the process proceeds to step 108. Step 108: In this step, the gate table 130
With reference to , a gate on the path element selected in step 104 that can be converted to a gate type is searched for. Figure 5 is a flowchart of this step. Based on this figure, the processing procedure of this step will be explained one by one. Step 500: This step adds 1 to the element bus counter. Here, the value of the element path counter represents the number of gate stages starting from the output terminal. Step 501: This step determines whether there is a gate pointed to by the element path counter in the path element. If the gate exists, the process branches to step 503; if the gate does not exist, the process proceeds to step 502. Step 502: This step sets the element path counter to 1.
Set to . Step 503: This step determines whether the element bus counter has completed one cycle in step 108. If the process has completed one cycle, the process advances to step 504, and if the process has not completed one cycle, the process branches to step 505. Step 504: In this step, the return cone is set to gate type conversion not possible, and step 108 is ended. Step 505: In this step, the gate table 130
Refer to , and determine whether the gate pointed to by the element bus counter can be converted to a gate type. Step 5 if possible
Proceed to step 06, and if impossible, branch to step 500. Step 506 sets the return code to "gate type conversion possible" and ends step 108. Step E09: In this step, the search result (return code) of step 108 is determined, and if the gate type conversion is possible, the process proceeds to step 110, and if the gate type conversion is not possible, the process branches to step 111. Step 110: In this step, the gate table 130
Referring to , convert the gate pointed to by the element path counter to a gate that has the same logic function as the gate and has the next smallest delay. In the model logic circuit 300,
An example of the processing in steps 103 to 110 described above when path delay conditions (output terminal fan-out number 202 and delay specified path 203) are specified will be described below. (1) The bus element of the delay specification bus 203 is bus element 3
There are two, 05,306. (2) Select bus requirement $305. This path element is a bus connecting gates 301 to 303. (3) The gate name of the gate 301 is NR21, and the fanout number of the output terminal 207 is 2 due to the fanout number 202 of the output terminal, so the fanout number is 2. Therefore, the delay due to the gate table 130 is 3.5 n
It is s. Also. Gate 302 has a gate name I
Since the number of fanouts of the output terminal 206 is 3 due to the number of fanouts of the output terminal 202, the number of fanouts is 4. Therefore, gate table 13
0, the delay is 4.3ns. Also, gate 3
For 03, the gate name is NA21 and the fan-out number is 1. Therefore, the delay due to gate table 130 is 3.3 ns. Therefore, bus element 3
The bus delay of 05 is 1 1.1 ns by adding the delays of gates 301 to 303. (4) Since the bus delay 1 1.1 n s of the path element 305 is larger than the upper limit value of 9 ns of the path delay of the delay specified path 203, gate type conversion is necessary. (5) Attempt to convert the gate type of the gate 301 by referring to the gate table 130. The gate name of gate 301 is N
NR21 exists as a gate with the same logic function as NR21 and the second smallest delay after NR21.
Therefore, gate 301 is replaced by gate 6 with gate name NR22.
Replace with 01. (6) The gate name of the gate 601 is NR22, and the fan-out number is 2. Therefore, gate table 1
30, the delay is 2.3 ns. Therefore, the bus delay of pass element 305 is
, 302, 303 delay is added to give 9.9 n s
It is. (7) Path delay 9.9 of path element 305
Since n s is larger than the upper limit value of 9 ns for the path delay of the delay specification bus 203, further gate type conversion is required. (8) Attempt to convert the gate type of the gate 302 by referring to the gate table 130. The gate name of gate 302 is I
It is NVI. INV2 exists as a gate with the same logic function as INV King and the next smallest delay after INVI.
Therefore, gate 302 is replaced with gate name INV2(7) gate 602. (9) The gate name of the gate 602 is INV2, and the fan-out number is 4. Therefore, gate table 1
30, the delay is 1.9 ns. Therefore, the bus delay of pass element 305 is
, 602, 603 delays are added to give 7.5 n s.
It is. (10) Bus delay 7 of bus element 305
．． 5 ns is less than the bus delay upper limit of 9 ns of the delay specification bus 203, so no further gate type conversion is required. (11) Select path element 306. This path element is a path connecting gates 601 and 304. (l2) The gate name of the gate 304 is NR21, and the fan-out number is l. Therefore, the delay due to gate table 130 is 3.3 ns. therefore,
The path delay of the path element 306 is the gate 601, 304.
The delay is 5.8ns. (13) Path delay of bus element 306 5.8ns
is the upper limit value 9 of the path delay of the delay specified bus 203
Since it is less than ns, there is no need to convert the gate type. (14) Since there are no unprocessed bus elements, this processing ends. Figure 6 shows the result of the above processing, that is, the logic circuit after gate type conversion. Step 11l: This step outputs an error message stating that a logic circuit that satisfies the path delay conditions input in step 100 cannot be generated, and abnormally terminates the logic macro expansion process. Step l12: This step outputs the logic circuit generated in steps l00 to l10 to the logic circuit file 122. According to this embodiment, it is possible to generate a logic circuit that satisfies the path delay conditions specified by the logic macro description data.

〔Effect of the invention〕

According to the present invention, the greater the number of gates with the same logic function but different delays, the more detailed gate type conversion becomes possible, making it possible to generate an optimal logic circuit.

[Brief explanation of the drawing]

Fig. 1 is a flowchart of logical macro expansion processing based on the present invention, Fig. 2 is an explanatory diagram of logical macro description data, and Fig. 3
The figure is an explanatory diagram of the logic macro model logic circuit, Figure 4 is an explanatory diagram of the gate table, and Figure 5 is step 10 of Figure ■.
8 is a flowchart of the gate search process for gate type conversion, and FIG. 6 is an explanatory diagram of the generated logic circuit. 100-112...Logic macro expansion processing step, 1
20~Eng 22...Logic file, 130...Gate table. Hanging 2 eyes 204 205 Jinto 1 rice! 2oz,'2θ7 Yoto f@J /30 Rod 4 Metaku 5 Ward

Claims (1)

[Claims] 1. In a logic design automation system for logic devices that uses a computer, enter the logic macro name that represents the type of logic macro and the pathdayless conditions between the input and output terminals of the logic circuit that will be automatically generated from the logic macro, and enter the logic macro name as a key. Search the logic macro library for a model logic circuit defined by the standard delay gate of the logic macro, and sequentially replace the standard delay gate with a high-speed gate in this model logic circuit until the path delay condition is satisfied. 1. A method for manufacturing a logic circuit, comprising: generating a desired logic circuit.