JPS58129650A - Data processor - Google Patents

Abstract

PURPOSE:To shorten sort processing time, by executing the sort-procession of data synchronously with a data stream by a linear array of a cell consisting of a comparator, two shift registers and a controlling circuit. CONSTITUTION:Data r1 are set up in a register 112 through a line 123. The data r1 are inputted to a register 113 under a transfer controlling function by a cell controlling unit 102 and control by a delay circuit 105 and also inputted to a comparator 108 through a line 125. Simultaneously with said input operation, the data r1 in the register 112 are inputted to the comparator 108 through a line 124 to be compared with the former input. The compared result is set up in a latch circuit 109 and transferred to a cell controlling unit 102 through a line 120. On the basis of the transferred result, a register in which data to be transferred to the succeeding cell are stored is determined and the transfer processing to the succeeding cell is started.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus for sorting data.

There are many algorithms for classifying data, and these are supported by software, but recently, with the development of new storage devices and advances in LSI technology, proposals for data sorting processing using hardware have become active.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that sorts data using dedicated hardware, which has the effect of shortening the sort processing time.

In order to achieve all of these objectives, the present invention is characterized in that data classification processing can be performed in synchronization with the data stream using a cell arrangement consisting of a comparator, two shift registers, and a control circuit. be. Also, the ratio l1l
According to IIIj flag, best 10 and worst) 10
You can also perform sort selection processing like this.

The present invention will be described in detail below with reference to embodiments.

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention, and FIG. 2 is an internal block diagram of an example of a notebook box that performs a sorting process. Hereinafter, it is assumed that the data handled in this embodiment is in a fixed format and its size is within the IIL range that can be stored in an intra-cell register.

In jll#A, the data to be sorted is stored in the mass storage device [1], and this data is divided based on the size ratio processing in cells 6 to 8 of note box 2. If the number of sort data is less than the number of cells in sort box 2, after the final transfer data soft processing is completed, the data in box 2 is transferred to Tetsuo Tsukuda for next processing through lines 14 and 15. On the other hand, if the number of sorted data is greater than the number of cells, data n after the sorting is pushed out from the last cell 8 is transferred and stored in the storage device i4. jl end data sort box 2F9 processing is finished, sort box 2 yen data (noted data) is placed on line 14.15t-
transfer to the next step. After the transfer is complete, write down! !
The data is transferred from 114 to the sort box 2, and the same process as described above is repeated until there is no more data in the tm fold straight 4. The storage device 4 and the like of the sort box 2 are controlled by the control unit 3.

Also, in the sort box 2, there is a ninth control unit 5 that controls the cells.

FIG. 3 shows the flow of processing in the cell controller 102 of FIG. 2.

Figure 4 shows the data processing according to the present invention! 1 is the configuration of another embodiment of the device. The difference from FIG. 1 is that there is a sort data tracing unit 9 and a memory storage unit 10 for storing the entire record.

Further, in this configuration, the number of records to be sorted is within the number of cells. In unit 9, the original data is converted into a data format that can be processed within the sort box 2. That is, in unit 9, an order representing the transfer order is added (the field representing this order is a fixed table).The data format in this embodiment is a fixed table format consisting of a sort field and other fields. It is assumed that the sum of the field size and the auxiliary field size generated in unit 9 is smaller than the register size within the cell. The sort field data generated in unit 9 is sorted in sort box 2. After sorting is completed, the value of the number field of the data in the register in the cell (this value indicates the order of data records transferred from storage device 1, and the records are transferred to JI
K storage device 10. ), storage device 10
is transferred to the next step through line 20t-.

The above transfer control is performed by the control unit 3.

gssa represents yet another embodiment of the data processing apparatus according to the present invention, and performs processing when the number of data to be sorted is greater than the number of cells in the note box 2. This fifth
The illustrated embodiment is a combination of the embodiments of FIGS. 1 and 4.

1h6 shows still another embodiment of the data processing device of the present invention, which is a more advanced data processing device provided in the data search processing unit 111 in the embodiment of FIG.

The operation of each embodiment will be explained below.

First, regarding the embodiment shown in Fig. 1, Figs.
This will be explained using figures. First, the control device 3 initializes each unit in the device. Accordingly, sort box 2
Then each cell is initialized by the sort box control unit 5 through the lines 22.23.241-. That is, as shown in FIG.
line 22.23゜24 etc. and similar control line) from the trap,
Cell control unit 1 consisting of general-purpose microprocessors
At 02, control returns and initializes each unit in the cell.

In the following explanation, it is assumed that data is sorted in ascending order.

In the initial state, the comparison control flag 106 in the data register control unit 104 is set to ``1''.

This is a message that instructs to transfer the larger comparison result to the next cell. Note that this flag 106 is @
In the case of OII, specify the "condition of equal to 1", and in the case of '-1', specify the cell operating condition to transfer the smaller comparison data to the next cell (i.e., in the case of descending order sorting) It is. It is also assumed that the changeover switch 110 is connected to the register 112, and the switches 111 and 114 are connected to either register 112 or 1113.

The above conditions activate the data transfer from the control unit 3 storage device 1 through the line 12, and input the transferred data stream into the notebook box 2 through the line 13t-.

Now, let this data fi be r,, r□..., r,
When the sort box control unit 5 detects data transmission, it passes control over line 22 to the cell 6, where the
As shown in FIG. 2, the cell delay circuits 105 and 107 control the timing of transfer data m, and first, data r is set in the register 112 through the line 123. Here, data storage, transfer from the register, etc. are controlled by a data table register and a counter control circuit (not shown) in the cell control unit 102.

At this time, the valid register flag 127 in the cell control unit 102 is set to 0'' (indicates the left register 112 of the cell. If it is '2', it indicates the right register 113). At the same time as the r1 set is completed, the selector switch 110 switches the register 113, the switch 111 switches the register 112, and the cell control unit) 1
02 changeover switch control function, each control line 1
Connected through 18 and 119. After this state is established, the data r.

is input to the comparator 108 through line 125 under the control of the data transfer control function of cell control unit 102 and delay circuit 105 . Simultaneously with this input operation, data r1 in the register 112 is input to the comparator 108 through the 2-in 124t-, and n1 comparison is performed. The result is set in latch circuit 109 and passed through line 120f to cell control unit 102 (step 202 in FIG. 3).

Here, the comparison result @1'' changes the value of the valid register 7 lag 127 by the register control function of the transfer denit 102 from the next cell, and also determines the register containing the data to be transferred to the next cell. Then, the transfer process to the next cell is started (step 203 in Fig. 3).The operation of the next cell is performed by passing water through lines 2B, 26.27.IIL 117.Now, r, >rl At this time, the value of the comparison control flag 106 is 11'', so the data transferred to the next cell is r, and the data register is the register 112.
becomes. At this time, the valid register flag 127 is set to @1'. At the same time as these operations are completed, switch 11G is set to register 112 and switch 111 is set to register 1 by the cell system @ Enit 102 changeover switch control function.
13 and switch 114 are connected to the fl register 112, respectively. After the connection is completed, the data r is changed to 'F e '!
Comparator 108 and register 11
Transferred to 2.

The comparator 108 of r in the register 113 is synchronized with n.
and transfers data r1 from register 112 to the next cell through line 126. The data flow r, ~r
, (step 206 in FIG. 3). If, n
If is smaller than the number of cells, check the value of the valid register flag 127 of each cell, and based on this value, transfer the data from either the left or right register of each cell to the next step through line 32. This completes the sorting process (step 2o7 in FIG. 3).

On the other hand, if the number of data to be sorted is greater than the number of cells, the data will be pushed out from cell 8! is stored in the storage device 4 through lines 14-16. Storage control is controlled by: L=', /
step 3 (step 208 in FIG. 3).

After all the data flows r1 to r have passed through the sort box 2, the data in the sort box 2 is transferred to the next step, and after that, the data in the storage device 4 is transferred to the control unit. Under the control of step 3, the same process as above is repeated (step 210 in FIG. 3). When no data is pushed out from the sort box 2 to the storage device 4, the data classification process for all data streams r1 to r is completed. When it ends, it becomes λ.

The operation of the valid register flag 127 in the above process is shown in FIG. 7(a), φ) using a specific example. Now, assume that the number of cells is 5 and the data flow is 8.4.6.2.10.

At this time, the value of the valid register flag 127 changes as shown in Figure 7) and is sorted into 2, 4, and 6.8. These data are stored in the register indicated by the valid register flag 127 (if the value of this flag is 10", the left register, @1"
indicates the right register). In addition, as shown in FIG. 7(b), depending on how the comparison control flag 106 is set, the best two and worst two (in FIG. 7,
You can select categories such as 2 from the smallest and 2 from the hottest.

Next, the operation of the embodiment shown in FIG. 4 will be explained.

In this embodiment, a record data set consisting of a note field and fields other than n is sorted. It is assumed that the number of record data is smaller than the number of cells.

Sort field (size can be stored in an in-cell register)
It is a genre that can be played. ).

~t, (n × N) is sent from storage 1 through line 12.18 to unit 9 for sort data selection numbering, and
It is transferred to the storage device [10 via line 12.19.

Record data r transferred from memory #ci[1,
~r, is in fixed table format.

Unit 9 performs processing such as cutting out a sort field from the original record and adding a transfer 1118 field to it. For example, the extraction of the sort field in unit 9 is as follows:
This can be realized as shown in 531.

Further, as a circuit for adding the transfer order field, the circuit shown in FIG. 8 or 9 can be used.

In the w & 8 diagram, 301 and 302 are changeover switches, 3
03.304 is a shift register, 305 is a control circuit, 3
06 indicates a counter.

In FIG. 9, 401 and 402 are changeover switches, 403 and 404 are data registers, 405 is a control circuit, 406 is a counter, and 407 is a shift register.

As shown in FIGS. 8 and 9, the basic configuration is double buffering, and a transfer order field TW is formed in synchronization with each data transfer. That is, the counter is updated in accordance with data transfer, and the updated value is added as a count section. The sort field to which the order field has been added is input from unit 9 through line 13 to sword box 2, and sorting is performed in the same manner as in the embodiment of FIG.

The cell control unit 102 of each cell controls so that the order field is ignored. In unit 9, a record format field information table (omitted) is set, and a sort field identifier is set in the sort field along with the field I.

Based on this information, shift registers 303, 304 or data register 40, which are buffers in unit 9,
3,404 (S) A tuple buffering configuration is used for IJ-me control. ).

Also, each time a record transfer is performed, the record transfer counter 306 or 406 in the unit 9 is set (initially set to zero). Then, when transferring from the buffer to the sort box 2, this counter value is added to the sort field data and transferred. The subsequent processing is the first
This is the same as the embodiment shown in the figure. After all the record data has been transferred, check the answer in the data register in order from cell 6, obtain the order field therein, access the storage device 10 based on that value, and sort the data. Line 20 transfers to mail order next step.

Furthermore, regarding the operation of the embodiment shown in FIG. Become clear.

This embodiment is a combination of the embodiment shown in FIG. 1 and the embodiment shown in FIG. 4. That is, this is the configuration when the number of record data to be sorted is larger than cell N. The processing operation is
Record data is transferred from storage device 1 to unit 9 through line 12.19'i and to storage device 10 through line 12.19'i. In unit 9, the sort field is extracted and the order field is created and added in the same manner as in the second embodiment shown in FIG. 4, and transferred to the sort box 2.
Performs sorting processing. The sort field data output from the sort box 2 is on line 141! - is transferred to the storage device 4 through. All data is sorted in box 2
Once the t-pass has been completed, the memory 10 is accessed under the control of the control unit 3, starting with cell 6, and transferred to the next step via line 20, based on the value of the order field in the register. The above processing is repeated until there is no more sort field data stored in the storage device ff14 to perform the sorting process.

Furthermore, the operation of the embodiment shown in FIG. 6 will be explained.

This example is! Patent application No. 55-89443 for the example of S diagram
．． A data search processing unit 11 (inner S* structure, operation omitted) as shown in No. 55-145531 transfers an incoming record data set from line 21 to This has the effect of reducing the number of data transferred to the sort box 2 and the storage device 10 by filtering the data. By adding this unit 11, a more advanced and faster data processing device can be realized.

As explained above, according to the present invention, the following effects can be obtained.

(1) Data can be sorted in synchronization with the input data stream, reducing processing time.

(2) The cell has a simple configuration and can be easily integrated into an LSI, and at the same time, the sort box can also be integrated into an LSI.

(3) Sort data selection Numbering allows data with large record sizes to be sorted by unit in accordance with the four rules for data transfer, and by repeatedly using the sort box, it is also possible to sort large amounts of data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the data processing device according to the present invention, FIGS. 1p and 2 are block diagrams of an example of the sort box in FIG. 1, and FIG. 3 is an example of the operation of the cell control unit in FIG. 2. FIGS. 4 to 6 are all configuration diagrams of other embodiments of the data processing apparatus according to the present invention. FIG. 7 is a diagram showing the state of the valid register flag IIi in FIG. Figure and #! FIG. 9 is a configuration diagram of an example of the sort data selection numbering unit shown in FIG. 4, respectively. 1.4.10... Storage device, 2... Sort box, 3... Data processing control unit, 5... Sort box system @: x-x-y, 6, 7, 8, 101 ”・Cell, 9... Sort data selection numbering is unit, 11
...Data search department 1! Unit, 1o2...Cell system (lIl]: L chive), 106...Comparison control flag,
1o7...Delay circuit, 108...Comparator, 109.
- Comparison latch, - 110° 111.114 - Changeover switch, 112, 113 - Data (sist) register, 127 - - Valid register flag. Y 1 diagram

Claims (1)

[Claims] 1. In a data processing device that classifies a data set, a register that stores transferred data, a comparison circuit that compares the data in this register with the transferred data, and a comparison circuit that stores the transferred data; It has a latch circuit that latches the result, a comparison control flag that sets ascending and descending instructions, and a valid register flag that indicates the register containing the necessary data, and a cell control circuit that controls the registers. A data processing device that performs a comparison between data and classifies the data without interrupting the transferred data stream. 2. When QI consists of a sort field and other fields, the sort data transfer order t count,
Add that i[, create a new sort data It, and min-
1. The data processing device according to item 1, characterized in that the data processing device is provided with means for performing the processing. λ When it is necessary to classify data exceeding the number of cells, an auxiliary memory iron is provided and the classification process is made possible by using the sort pock 4. Paragraph 1 of the patent claim The data processing device described.