JPH0315916A - Bicmos reference circuit - Google Patents

Abstract

PURPOSE: To change the simple ECL signal voltage in an ECL(emitter linked logic) circuit block with a maximum speed by providing the voltage generating circuit which generates a certain reference voltage based on a reference current to a partial circuit. CONSTITUTION: Each ECL circuit block has its own reference circuit VREGEN. The received signal of the ECL is not a voltage but, it is a current reference from a reference current generator. The generator converts the voltage from a band gap reference current into a current before transmitting signals to remote locations such as ECL gates distributed on a chip. In these locations the reference current is converted to a voltage and a correct reference current against a local circuit such as a local ECL gate is obtained. Thus, a simple ECL signal voltage is changed with a maximum speed in the ECL circuit block.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application 1 The present invention relates to the field of B i CMOS integrated circuits.

BACKGROUND OF THE INVENTION Until now, the voltage amplitude and signal margin of emitter-coupled logic circuits (ECLs) have not been controlled by a single on-chip voltage reference circuit. The problem with this conventional method is that
The voltage is accurately referenced only to the power supply voltage level in the physical vicinity of the reference circuit. Because of the voltage drop associated with the S current, the actual R source voltage varies considerably across the semiconductor chip, and therefore the reference voltage cannot be used. VLS I8i CMO
This has proven to be particularly problematic when ECL logic circuits are used in S-circuit designs.

FIG. 1 is a circuit diagram of a quasi-ECL gate.

The circuit comprises a differential pair 2 (with N-type bipolar transistors O1 and 02) and a source follower stage 4. N-type bipolar transistors 04 and 05 are connected and constitute the output of this gate. The power consumption of this gate is V R E F 1 signal (
VREFIG, tJ pressure)! ! 1111 will be sent. If transistor o3 is kept out of saturation during its operation, the current I (flowing through resistor R connected to the emitter of transistor 03)
. S is (VREF1-VBE)/Rl. :equal. Voltage VREF1 controls the output voltage amplitude of this gate. The difference between the high and low output levels of this gate is I. sxR, and it can be seen that this is the electrical ratio drop across the pull-up resistor of the differential pair. The input trip point of this gate is the signal voltage VRE between the voltage CC and the voltage at the base of transistor 02.
Set by F2. If the input of this ECL gate (node IN) is driven by a signal from the output of another ECL gate similar to this gate, then in order to obtain maximum signal margin and best performance, VREF2
should be set at the midpoint of this output voltage amplitude. If VREF1 and VREF2 are held at a constant level, the voltage drops on the vCC and VEE power supply lines will disable these two power supplies.

FIG. 2 shows the physical layout of the vcctu source pads and VEE power bands on the chip and the associated graphs. At 83 in FIG. 2, each pad is close to each other. A band gap reference circuit producing voltages VREFI and VREF2 is located near the power pad, and each block of ECL circuitry is located remote from the power pad. The resistance value of the power supply line is modeled and represented by a resistor R.

The graph in FIG. 2 is a graph showing the change in selected voltage versus distance. The X-axis indicates the distance from the power pad of the corresponding ECL@path shown above, and the Y
The axis is f! of the main signal in the ECL gate. ri. represents. The voltage drop along the vCC power line and the VEF power line is shown by the black area in the graph.

The ECL circuit at the end of the power supply line has the largest voltage drop 1
・Receive.

VREFI and VREF2 are referenced to the power pad, so no matter how far they are from the pad,
Regardless of that, it is at a certain level. However, the current produced by VREF1 in the local ECL circuit is not constant.

This results in a drop in the output voltage of the ECL gate along the power supply line. The high level output of the ECL gate also decreases due to the voltage drop in the vCC line. These effects significantly degrade signal margin. What if the voltage drop in the ma16J path is the output? If it is more than half of the t1mo amplitude, the chip will be far from normal operation.

FIG. 3 is a diagram of one example of an SRAM designed to fit into a standard JDEC package. Also shown in FIG. 3 is a graph of selected voltage versus distance, which corresponds to the graph shown in FIG. In FIG. 3, M source pads are placed at both ends of the chip. The effect of the voltage drop along the power supply line is the same (J), but in this case the signal voltage amplitude is larger and the forward direction The addition of bias can cause sudden and catastrophic failure of operation.

FIG. 4 is a diagram of a multiple (two) band gap reference circuit similar in configuration to the circuits shown in FIGS. 2 and 3; FIG. 4 also shows a corresponding graph of selected voltage versus distance. Two band-give V-tube circuits are located at each end of the package.

This method requires a large design area. The constraints on the placement of these reference circuits reduce the effectiveness of this scheme. The ECL circuits furthest from the reference circuit will still experience signal degradation, and it depends on how large the voltage drop is at those locations. Similar problems occur in other circuits having current mode logic (CML) gates. FIG. 5 is a circuit diagram of a standard CML gate, which has a differential pair 2, consisting of two transistors 01 and 02 connected to transistor 03, for a value of VREFI or a value of VEE. It will be readily seen that if either changes, the current flowing through this gate will change, and so will the amplitude of the signal. Roughly, VREF2 or vC
Varying C has a detrimental effect on the noise margin required to make this circuit's blocking capability reliable. The effect of the reference voltage on the current of the B + CMOS/ECL circuit block is shown in FIG. FIG. 6 is a graph showing changes in current IEE with respect to changes in reference voltage.

OBJECTS AND SUMMARY OF THE INVENTION One object of the invention is to provide a reference circuit that is novel and has superior performance.

Another object of the invention is to provide an 8 i CMOS reference circuit.

The above objects of the invention are obtained by providing a voltage source which is defined with respect to the local power level. The local power level is set using a reference 'Ni source circuit.

This standard? Eight current sources can be routed across the chip without special considerations for power supply variations. This '4 source serves as an input to an analog driver that generates a reference voltage relative to the local power supply level. The semiconductor chip on which the invention is implemented uses a global band gap reference circuit that operates with current source feedback implemented with a PMOS current mirror. B+CMOS as an analog driver
OP1(!) is used. This analog driver converts the band -4! YAP reference output to the required level, thereby providing a low impedance source for the ECL circuitry of that chip. (Global ·band·
Change the global band gap voltage (from the gap reference circuit) to the current reference I! I! η and by reintroducing a voltage reference to the local ECL circuit block, the effect of the voltage drop difference between the global band gap circuit power supply line and the local ECL block is virtually eliminated.

[Effects of the invention J The invention provides the following advantages.

(1) Simple ECL signal voltage changes at maximum speed within the ECL circuit block.

(2) Tracked standards for single-ended ECL signals provide maximum signal margin.

(3) Precise reference levels for off-chip interfaces provide high performance I/O.

+41? The effect of four source line voltage drops is minimal and contained within the circuit block.

{5} Improved chip operating margin is obtained by preventing feedback noise during gate switching from propagating back to the band gap reference circuit.

{6} A low impedance voltage reference source provides a high degree of current handling performance, which also helps improve bibolar transistor processing margins.

[Jiura Example] The above and other objects of the present invention, as well as its features and advantages, will become apparent from the following detailed description with reference to the accompanying drawings.

FIG. 7 is a diagram illustrating a preferred embodiment of the present invention and a selected voltage versus tip distance graph. Each ECL
The circuit block has its own reference circuit VREGEN. The ECL does not receive a voltage, but a current reference from a reference current generator. The reference ffi current generator must pass through the bandgap t1! before sending the signal to remote locations such as ECL gates distributed on the chip. From the current?
Converts +2 voltage to current. At these locations, this reference current is converted to a voltage and thus the correct reference current for the local circuit, such as the local ECL gate. Therefore, in the present invention, the problem of the voltage drop in the N source line connected to each ECLL block is virtually eliminated. As shown in this drawing, V'REF1 and VR
EF2 is properly based on the local power level. Each EC
Since the I/O signals in the L block are now at the correct level, maximum signal margin is restored. The signals are only offset from block to block.

Several circuit techniques can be used to solve the problem of global signal communication between ECL circuit blocks. These techniques include: i.e. use of differential signals, single terminated signal with trip point reference from transmitter, level shifter circuit, VCC? ! ! The goal is to minimize the source line voltage drop. To keep the vCC drop to a minimum, more area can be used for the vcca path in the design. When a CC power line with a large width is used, its resistance value becomes small. Prior to the present invention, the widths of both the vcca and VEEIi paths had to be large to reduce voltage drop. One or all of these techniques can be used depending on the requirements of the particular circuit. Differential signals for hidden communications in the ECL block provide the best signal margin, but require more design space and
There are also logical operations that can be performed on the available signals. Single terminated signals can be used.

However, a 1-rip point reference level must be sent from the transmitter to the receiver circuit to improve signal margin. Providing level shifter circuits in both the transmitter and receiver may provide effective communication, but will add some circuit complexity. However, the easiest way is to improve the ground line. In an ECL circuit (by increasing the width of the VCC power supply line), reducing the voltage drop on the VCC line effectively improves the signal margin by the same amount.

FIG. 8 is an embodiment of the present invention similar to the embodiment of FIG. 7, but by allocating more area to the VCC power line during circuit design, the voltage drop on the vCC power line is minimized. has been done.

As shown in the graph, the circuit of the present invention can tolerate more voltage drop on the VEE line than the standard reference method. If the vCC power line voltage is as shown in the figure, all ECL1/O (input/output) signals from all blocks will match.

With the present invention, the physical location of the band gear and ffi current generator with respect to the M source band and circuit lock becomes less important.

The key elements of the circuit of the present invention are 8 i CMOS band
It is a gap circuit. This B i CMOS band gap circuit is not TM sensitive to power supply fluctuations. This band gap circuit is disclosed in serial number 07/161.694, received February 29, 1988. This circuit will be explained with reference to FIG. FIG. 9 is a diagram of a standard band gap reference circuit. The current source is the base of the N-type bibolar transistor Q2 and the N-type bibolar transistor Q2.
It is connected to the collector of transistor Q1. The base of Q1 is connected to the collector of N-type transistor nQ3. The base of transistor nQ3 and the base of transistor Q3 are connected. The relative values of the resistance values of the resistors shown in the drawings are marked in the drawings. Voltages are shown between the arrows. The output of this circuit is the reference voltage VREF. Reference output V R E F l. It is equal to the sum of t V B E ( k Transistor Q1 is used as a negative feedback amplifier, thereby bringing VREF to the silicon band gap voltage (approximately 1.25 volts).
to maximize temperature stability. Variations in the load current Ia (from the current source) in this circuit have a direct effect on the VREF output. One of the main causes of fluctuations in the 1a current is fluctuations in the power supply. The band gap current of the present invention keeps the N current fa as stable as possible. Although there are a number of circuit techniques that provide stable 'Ii[ sources for this purpose, many of them are unreliable, complex, and require large design space. For example, one of the most popular designs uses yet another band gap to generate the I,ffi current.

FIG. 10 is a diagram of a B i CMOS band gap circuit used in the present invention. Standard band guitar IF
Unlike the Tsubu circuit, this circuit is rfIm and
No second band gap circuit is required to generate the Iaffi current. This circuit utilizes its own band gap output to generate the load current. This can be achieved by using P-channel MOS transistors P1 and P2 to cause the current I generated by the output voltage VREF and flowing from transistor Q4 through resistor 3R to flow in a mirrored manner to the load of transistor Q1, which is a feedback amplifier. It will be done. Stable voltage output VR
EF provides a stable load current change, and self-feedback provides the reverse. As shown in the drawing, we put this circuit into the biro current mode due to its self-feedback (this results in zero feedback).
A start-up circuit is required to keep the power off.

Once the reference output is at the correct level, start
The up circuit is no longer needed and should be electrically disconnected to avoid possible negative effects.

Note that the current flowing through each branch is kept the same to maximize tracking performance.

FIG. 11 is a diagram illustrating the output of the bandgap circuit of the present invention for VCCffi pressures from 3 volts to 7 volts. There is a 14 millivolt output change over the entire range (0.35%), but the circuit works fairly well in the 4 volt to 7 volt vCC region.

Within this region the output varies by 5 millivolts (0.16%
> only.

FIG. 12 is a diagram of a reference current/voltage conversion circuit according to the present invention. This circuit is used for each local location of the ECL circuit block. Global band gap voltage VREFI
I quasi-current rREF and sent to a remote ECL circuit block.

In the ECL block, the IREF current is mirrored by P-channel transistors 13 and 15 and through bipolar transistor Q20 and resistor R to again produce a VREF level corresponding to the local VEE voltage level. The output from this circuit can be connected directly to the ECL circuit (as shown). Alternatively, the output of this circuit can be connected to an OP amplifier, which provides greater current handling capability, or +! Greater flexibility can be obtained in that four voltage reference levels can be generated again. The VREF signal is obtained from the emitter of transistor QIO, which is connected to P-channel transistor 15 and bipolar transistor Q20.

FIG. 13 is a drawing of the drive circuit for the OP amplifier described above. The OP amplifier drive circuit is the part surrounded by the dotted line. The OP amplifier is connected in a unity gain configuration and produces at its output the same voltage level as that connected to its input. Bibolar transistors Q30, Q40 and ff
In order to improve the gain of the first stage of the difference between the i current source CS and the i current source CS, a 1] channel current source MP1 is used for the load.

VC between transistor Q30 and transistor Q40
To reduce input offsets that may be caused by Effi pressure differences, a cascade transistor Q
11# and Q12 are used.

The output from the OP amplifier driver circuit is obtained from the emitter of transistor Q5. The other circuit parts connecting this OP amplifier to other parts include gate-connected P-channel transistors MP2 and MP3.

Diode-connected transistor Q50 is connected to P'f-Yannel transistor MP3 and produces a reference current IREF.

An experimental prototype of the present invention was made using the 0.8u B i CMO82 heavy metal method. #The operating power is 7 volts without O volts. band gipp and o
Most of the design area of the P11'l@ device is occupied by the compensation capacitor used for operational stability. The output band gap voltage was measured to be 1.356 volts, with a temperature coefficient of 200 1) Ilm per 1°C.
Met. This is a little large because the band gap resistor capacitor k is not optimal. The open loop gain 1g of the OP amplifier was 45 db, which is an appropriate value for its purpose in this circuit. 1■V
The input A hit was measured. The power rejection ratio of this bandgap circuit was 47 db, while the blocking ratio for the OP amplifier was 67 db. This circuit is tle
g B i CMOS SRAMt' was implemented.

A block diagram of this circuit is shown in FIG. The power pad is on the back side of the chip. global band
The gap is placed near the VCCffi source pad.

A reference current is supplied to the other side of this circuit, and the local E
Occurs again at the CL circuit location.

The B i CMOS circuit is used for global communication within this SRAM. The characteristics of the above circuit are that the power supply voltage drop effect is small, the ECL signal margin is large, and the ECL signal margin of the VLSI B + CMOS ECL chip is small.
The CL circuit characteristics are improved.

Although the invention has been described in detail with reference to preferred embodiments and certain modified embodiments, it is meant by way of example only that the invention is limited thereto. It's not a thing. Those skilled in the art will be able to make many changes to the details of the embodiment shown in Suimei 4111 and add other embodiments within the scope of the present invention. will be understood soon. For example, other types of logic circuits can be substituted for the emitter-coupled logic gates. For example, TTL%
There are DTL1RTL and CML circuits. Furthermore, analog circuits can be used in place of logic circuits. Furthermore, any circuit that requires a reference voltage F can be used in place of the ECL circuit. Although field effect transistors and bibolar transistors are shown as specific examples, bibolar transistors can be used in place of field effect transistors, and vice versa. Also, P-type transistors can be used in place of N-type transistors, and vice versa. Similarly, N-channel transistors can be substituted for P-channel transistors, and vice versa. The scope of the claims of the present invention is intended to cover all such modifications and additions.

Regarding the above description, the following sections are further disclosed.

(1) A voltage reference circuit that generates a reference voltage by its operation; a reference current generator that operates in conjunction with the voltage reference circuit and generates a reference current derived from the reference voltage; and a constant base for proper operation. Q! A reference circuit comprising: at least one subcircuit requiring a voltage; and at least one voltage generating circuit operative to generate the constant reference voltage based on the reference my1 to the subcircuit.

(2) The reference circuit according to paragraph 1, further comprising at least one power source connected thereto.

(3) The reference circuit according to item 1, further comprising a connection line for power supply.

(4) In the first term, at least the first terminal and the second terminal are i, and the bias of the first terminal is equal to the reference current passing through the second terminal.
a current mirror connected to the second terminal of the first device for mirroring the reference current through the second terminal;
Said MFM&lIPI! connected to the first
a bandgap subcircuit for providing a bias determined by a reflected current to a terminal, the voltage reference circuit having bandgap diversity.

(5) In paragraph 4, the electric mirror reflector is
a diode device for receiving a predetermined current from the device, and the diode device is connected to the first
said reference circuit connected to said second terminal of the device and connected to a transistor connected to J3 and said bandgap subcircuit;

(6) The reference circuit according to clause 5, wherein the ptJ diode device includes a transistor connected in a diode configuration.

(7) The reference circuit of paragraph 1, wherein at least one of the voltage generation circuits has a current mirror connected to a current-to-voltage conversion circuit.

(8) The reference circuit according to item 7, wherein the voltage conversion circuit has a first transistor connected to a second transistor that supplies a basic voltage output.

(9) In item 7, the Wa style R imager has two gates connected R1! The reference circuit has a field effect transistor.

(10) The reference circuit according to clause 8, wherein the first transistor and the second transistor are bibolar transistors.

(11) The reference circuit according to item 7, wherein the current/voltage conversion circuit includes an operational amplifier.

(12) In paragraph 11, the operational amplifier is B i
The reference circuit is a CMOS operation 1rJ device.

(13) In paragraph 11, the operational amplifier has a differential amplifier and a field effect TEPCO i source connected to the differential amplifier, and the N'tI1111 operates to load the differential amplifier. The reference circuit serves as a.

(14) In item 13, the electric field effect 1! ! The reference circuit, wherein a current source operates to mirror the reference JR flow from the reference current generator.

(15) A method for generating a reference ICE for a circuit that requires a constant reference voltage for proper operation, the method comprising the steps of generating a global reference voltage and controlling a reference Ti current obtained from the global reference voltage. A method for generating the reference voltage, comprising: generating the constant reference voltage obtained from the reference current to the circuit.

(16). A B i CMOS current m reference circuit is disclosed that is free from the effects of DC power supply voltage drop during operation of an ECL circuit. The present invention provides VLS [E
Putting CL design technology into practice! It is fundamentally important when doing i. ，Electric! Using the source circuit, the reference voltage is generated locally so that the ECL voltage reference is properly based on the local power supply voltage. High precision on-chip4. Band gap that is not sensitive to M sources for connecting voltage references and current sources! Three quasi-generators are used. This band
Gap circuits use both MOSI-transistors and bibolar transistors, and are much simpler than similar circuits using only bibolar transistors.

[Brief Description of the Drawings] Figure 1 is the fEJ path diagram of a standard ECL gate, Figure 2 is the physical layout of the vCC and VEE power supply pads on the semiconductor chip and its related graph, and Figure 3 is the standard target JDEC
1 of the S scale AM designed to fit inside the package.
Figure 9 shows two embodiments in which the vCC power line is minimized by allocating more area to the vccrrtm line, and Figure 9 shows a standard band gap base tP.
- Circuit diagram, FIG. 10 is a B i CM used in the present invention.
OS band gap circuit diagram, FIG. 11 is an output diagram of the band cap circuit of the present invention for vcct pressures from 3 volts to 7 volts, FIG. 12 is a circuit diagram of the reference current to voltage converter of the present invention, FIG. Figure 13 is an OP1!1 width unit drive circuit diagram, and Figure 14 is a block diagram of the basic single circuit.

Claims (2)

[Claims] (1) A voltage reference circuit that generates a reference voltage by its operation, a reference current generator that operates in conjunction with the reference circuit and generates a reference current derived from the reference voltage, and a constant reference voltage for proper operation. 1. A reference circuit comprising: at least one sub-circuit requiring: at least one voltage generating circuit operative to produce the constant reference voltage based on the reference current to the sub-circuit. (2) A method for generating a reference voltage for a circuit that requires a constant reference voltage for proper operation, comprising the steps of generating a global reference voltage and generating a reference current obtained from the global reference voltage. and supplying the constant reference voltage obtained from the reference current to the circuit.