JPH03159165A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a capacitor having higher capacity than that of a normal stacked capacitor in high yield by laminating a first conductive layer, a first insulating film, a second conductive layer, a second insulating film and a third conductive layer, forming contact holes, forming an insulating film, and then anisotropically etching it. CONSTITUTION:A first conductive layer 27 is deposited on the entire surface of a semiconductor substrate 21, a first capacitor insulating film 28 is formed thereon, a second conductive layer 29 is further deposited thereon, and the layer 27, the film 28 and the layer 29 remain only on a predetermined region. Then, a second capacitor insulating film 30 is formed on the layer 29, a third conductive layer 31 covering the region is formed, a contact hole H' reaching the layer 27 is formed substantially the center of the region, and an insulating film 32 is formed on the layer 31 in the hole H'. Thereafter, the film 32 is anisotropically etched to substantially remove the film 32 on the layer 31 and the film 32 in the bottom of the hole H', the hole H' is then buried, and a fourth conductive layer 33 to be connected to the layer 31 is formed.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device including a capacitor formed on a semiconductor substrate, and more specifically, a method for manufacturing a semiconductor device including a capacitor formed on a semiconductor substrate. The present invention relates to an improvement in a method for manufacturing a DRAM cell having stacked capacitors.

(b) Prior art In general, there is a method for manufacturing a cylindrical stacked capacitor type DRAM cell, for example, as disclosed in Japanese Patent Application Laid-Open No. 197368/1982. explain.

First, as shown in FIG. 2A, a field insulating film (2) is formed on a P-type semiconductor substrate (1), and then a Si film is formed.

After forming a word line (4) through a film (3), an N3 type source region (5) and an N1 type drain region (6) are formed on the P type semiconductor substrate (1).

Next, a capacitor electrode (7) is formed in contact with the N0 type source region (5), and a cell plate electrode (9) is formed thereon via a first capacitor insulating film (8).

The capacitor formed by the above process is a normal stacked capacitor, and a method for manufacturing a cylindrical stacked capacitor with a higher capacitance will be described below.

As shown in FIG. 2B, a contact hole H1 reaching the capacitor electrode (7) is formed on the cell plate electrode (9) by photoetching.

Next, the surface of the cell plate electrode (9) is oxidized to form a second
A capacitor insulating film (10) is formed.

Subsequently, as shown in FIG. 2C, polysilicon is deposited to fill the contact hole H1, and a polysilicon film (11) covering the cell plate electrode (9) and the capacitor electrode (7>) is formed by photo-etching. Form.

Here, since the contact hole H1 is filled with polysilicon, the polysilicon film (11) can be connected to the capacitor electrode (7), and the capacitor electrode (
7) The increased effective area increases the capacitance compared to a normal stacked capacitor.

Next, the polysilicon film (1
A film (12) of Sin is formed on the surface of 1).

Next, as shown in the second diagram, PSG is deposited on the entire surface and PSG is applied.
After forming the film (13) and planarizing its surface, the N
Contact hole H2 reaching + type drain region (6)
form.

Next, after evaporating aluminum over the entire surface and filling the contact hole H2, a bit line (14) is formed by photo-etching, and PSG is deposited thereon to form a passivation film (15) to complete the DRAM cell. Was.

(c) Problems to be Solved by the Invention In the method for manufacturing the cylindrical stacked-passita type DR'AM cell described above, a contact hole H1 reaching the capacitor electrode (7) is formed on the cell plate electrode (9). The manufacturing process involved oxidizing the surface of the cell plate electrode (9) to form a second capacitor insulating film (10), and then depositing polysilicon to fill the contact hole H1.

However, when the surface of the cell plate electrode (9) is oxidized, an oxide film is inevitably formed on the capacitor electrode (7) at the bottom of the contact hold 1.
Even if polysilicon is subsequently buried, it is extremely difficult to electrically connect the capacitor electrode (7) and the polysilicon film (11).

Therefore, it has been difficult to obtain the effect of the invention of increasing the capacitance compared to the conventional method using this manufacturing method.

Here, if this oxide film is subjected to anisotropic etching to remove the oxide film on the capacitor electrode (7) at the bottom of the mounting hold 1, the second oxide film on the cell plate electrode (9) will be removed. Since the capacitor insulating film (10) is also removed at the same time, there is also a drawback that leakage of the capacitor occurs.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and as shown in FIGS. 1A to 1G, the cell plate electrode (29) is formed as a second conductive layer. A second capacitor insulating film (30
) After depositing a polysilicon layer (31) as a third conductive layer over the entire surface, the cell plate electrode (29)
A capacitor electrode (27
), a step of forming a contact hole H1 reaching the inside of the contact hole and the polysilicon layer (31
) on the capacitor electrode (27) at the bottom of the contact hole H1. and the S on the polysilicon layer (31)
A step of selectively removing the polysilicon layer (32), burying the contact hole H1, and removing the polysilicon layer (32).
31) and a step of forming an electrically connected polysilicon layer (33) as a fourth conductive layer to solve the above-mentioned problem.

(f) Effect (As mentioned above, the insulating film (32) formed inside the contact hole H1 opened in the cell plate electrode (29)
By performing an anisotropic etching process on the Sing (32) on the capacitor electrode (27), it is possible to selectively remove the Sing (32) on the capacitor electrode (27), and also remove the second capacitor insulating film (30) on the cell plate electrode (29). ) Since the polysilicon layer (31) is deposited on the second capacitor insulating film (30
) can never be completely removed.

Therefore, by subsequently forming a polysilicon layer (33) that fills the contact hole H1 and is electrically connected to the polysilicon layer (31) at the interface, the capacitor electrode (27) and the polysilicon film (33) are formed. ) are electrically and stably connected, and the capacitor electrode (
27) Since the effective area increases, a capacitor with a large capacity can be manufactured at a high yield compared to a normal stacked capacitor.

(f) Example Examples of the present invention will be described in detail below.

First, as shown in FIG. 1A, a field insulating film (22) is formed on a P-type semiconductor substrate (21), and then a Si film is formed.

After forming a word line (24) through a film (23), an N0 type source region is formed on the P type semiconductor substrate (21).
25) and an N0 type drain region (26) are formed.

Next, a capacitor electrode (
27) is formed as a first conductive layer, and a cell plate electrode (29) made of polysilicon containing phosphorus is formed thereon as a second conductive layer via a first capacitor insulating film (28).

Here, the first capacitor insulating film (28) is formed, for example, by depositing a silicon nitride film to a thickness of about 120 nm by LPCVD and then oxidizing it in a 900'' CDryO atmosphere for 30 minutes.

Next, a second capacitor insulating film (30) is formed on the cell plate electrode (29) under similar conditions.

Next, the 113i! As in FB, a polysilicon layer (31) covering the cell plate electrode (29) is deposited as a third conductive layer to a thickness of about 2,000 nm and heated at 900°C.
Then, phosphorus diffusion is performed to lower the sheet resistance of the polysilicon layer (31) to about 40Ω/hole.

Next, as shown in FIG. 1C, a hole H1 reaching the capacitor electrode (27) is formed on the cell plate electrode (29) by photoetching.

Subsequently, as shown in the first diagram, an insulating film of TenoSiO is formed inside the contact hole and on the polysilicon layer (31).
*The film (32) is deposited by LPCVD to a thickness of approximately 1000 mm.

Thereafter, as shown in FIG. 1E, the SiOx film (32) is anisotropically etched to form the contact hole H.
The Sin film (32) on the bottom of the capacitor electrode (27) and on the polysilicon layer (31) is selectively removed.

In this case, the SiOx film (32) remains on the inner side wall of the cell plate electrode (29), so that the cell plate electrode (29) is no longer insulated.

Next, as shown in FIG. 1F, the contact hole H1 is buried and the polysilicon layer (33) connected to the polysilicon layer (31) is formed as a fourth conductive layer by LPCVD to a thickness of about 1000 layers. deposits on. Subsequently, the resistance of the polysilicon layer (33) is lowered by performing phosphorus diffusion under the same conditions, and the resistance of the capacitor electrode (27) is lowered.
) and the polysilicon J (31).

Next, unnecessary portions of the polysilicon layer (31) and polysilicon layer (33) are removed by photoetching, and a SiO2 film (34) is formed on the surface by block oxidation.

The feature of the present invention is that, as described above, the second capacitor insulating film (30) is formed on the cell plate electrode (29).
After depositing the polysilicon layer (31) covering the cell plate electrode (29) through the cell plate electrode (29), a contact hole H1 reaching the capacitor electrode (27) is formed on the cell plate electrode (29), and then S is applied inside the contact hold 1 and on the polysilicon layer (31).
The manufacturing method includes forming an in film (32) and subjecting the in film (32) to an anisotropic etching process.

By such a manufacturing method, a cylindrical stacked capacitor with increased capacitance can be manufactured with high yield, even if it is a normal stacked capacitor.

Next, as shown in Fig. 1G, BPSG is deposited on the entire surface to form BP.
After forming the SG film (35) and planarizing its surface,
A contact hole H2 reaching the N1 type drain region (26) is formed.

Next, after depositing tungsten polycide and filling the contact hole H2, a bit line (36) is formed by photo-etching, and PSG is deposited thereon to form a passivation film (37) to form a DRA.
Complete the M cell.

(G) Effects of the Invention As is clear from the above explanation, when the manufacturing method of the present invention is followed, it is difficult to electrically connect the capacitor electrode and polysilicon in the conventional manufacturing method of a cylindrical stacked capacitor. Since this disadvantage is removed, it is possible to manufacture a cylindrical stacked capacitor with a higher capacitance than a normal stacked capacitor at a high yield.

[Brief explanation of the drawing]

1A to 1G are cross-sectional views for explaining the manufacturing method of the present invention, and FIGS. 2A to 2G are cross-sectional views for explaining the conventional manufacturing method.

Claims (3)

[Claims] (1) A method for manufacturing a semiconductor device including a capacitor formed on a semiconductor substrate, wherein the capacitor includes the steps of: depositing a first conductive layer over the entire surface of the semiconductor substrate; and depositing a first conductive layer on the first conductive layer. forming a first capacitor insulating film; depositing a second conductive layer on the first capacitor insulating film; and depositing the first conductive layer and the first capacitor only in a predetermined region. a step of leaving an insulating film and a second conductive layer; a step of forming a second capacitor insulating film on the surface of the second conductive layer; a step of forming a third conductive layer covering the region; forming a contact hole reaching the first conductive layer approximately in the center of the region; forming an insulating film inside the contact hole and on the third conductive layer; anisotropically etching the insulating film. The third
a step of substantially removing an insulating film on the conductive layer and an insulating film on the bottom of the contact hole; and a fourth conductive layer that fills the contact hole and is electrically connected to the third conductive layer. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device. (2) The insulating film is S deposited by LPCVD method.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the film is an iO_2 film or a Si_3N_4 film. (3) The first conductive layer is deposited after forming a MOS transistor on the semiconductor substrate and exposing a part of the source region of the MOS transistor. 2. The method for manufacturing a semiconductor device according to item 2.