JPH03156536A - Microprocessor - Google Patents

Abstract

PURPOSE:To improve the data processing efficiency by providing a first instruction selecting means which forms a first processing loop, a second instruction selecting means which forms a second processing loop, an address information storage means, etc. CONSTITUTION:A first programmable counter 600 forms the first processing loop and starts a second programmable counter 650, which forms the second processing loop, by a specific instruction of a programmable logic array (PLA) 100. Execution of programs is optimized through a second priority level storage means, a comparing means, a monitor pointer, a first priority level storage means as the program execution learning means, etc., in a window WD 700. That is, the first processing loop starts execution of the next program without waiting for the end of the program of the second processing loop after designation of the execution start address and the priority level of this program, thereby obtaining a microprocessor of high processing efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a new microprocessor configuration, and particularly to providing a microprocessor with high data processing efficiency.

BACKGROUND OF THE INVENTION In recent years, Neumann type microprocessors have been widely used in various fields, and their configuration includes an instruction memory for storing programs, a timing generator for generating instruction execution timing signals, and a processor based on the output of the timing generator. It is characterized by comprising an instruction selection means for selecting a specific instruction stored in the instruction memory and executing the program.

Further, a typical configuration thereof is shown in Japanese Patent Publication No. 58-33584 (hereinafter abbreviated as Document 1).

Problems to be Solved by the Invention Incidentally, since the Neumann microprocessor shown in the above-mentioned document 1 executes data processing according to a predetermined order, as the program becomes huge, the number of asynchronous inputs increases. The problem is that the cycle of importing external data and processing data based on it becomes long. In response to such issues,
Conventionally, interrupts have been used or non-Neumann processors such as data flow machines have been used. However, in the method using interrupt means, as the number of interrupt channels increases, the processor itself spends more time on procedures for starting an interrupt service routine, which deteriorates data processing efficiency.

Furthermore, in a data flow machine, processing information is generally added to numerical data and circulated, resulting in a large-scale system.

Means for Solving the Problems In order to solve the above-mentioned problems, the microprocessor of the present invention includes an instruction memory that stores a program consisting of a group of instructions to be executed sequentially, and a timing generator that generates an instruction execution timing signal. , a first instruction selection means for sequentially selecting instructions stored in the instruction memory based on the output of the timing generator to form a first processing loop; and an instruction selected by the first instruction selection means. a second instruction selection means for selecting the stored instructions from a start position specified by to form a second processing loop having a concurrent relationship with the first processing loop; and address information storage means for storing a plurality of the start positions and program priorities that are successively designated as the loop program is executed; and an empty area of the address information storage means is filled with reservations for unexecuted programs. and a priority comparison means for comparing the priority of the last stored program with the priority of a new program designated upon execution of the program of the first processing loop, and an output from the priority comparison means. The start position and program priority information last stored in the address storage means are discarded in accordance with the signal sent to the address information storage means, and the priority information of the start position tophrogram newly designated upon execution of the program is stored in the address information storage means. comprising address information exchange means for re-storing address information, priority storage means for storing a plurality of priorities of the address storage means, and program execution learning means for optimizing program execution based on the data of the priority storage means, and The first processing loop is a concurrent process configured to specify the execution start address and priority of the program of the second processing loop and then start the execution of the next program without waiting for the end of the program. Has a command.

According to the present invention, a microprocessor with high data processing efficiency can be obtained by the above-described configuration.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the microprocessor of the present invention. This microprocessor consists of an instruction memory that stores a program consisting of a group of instructions to be executed sequentially, and a programmable logic array (indicated by the abbreviation PLA in the figure) that controls the analysis and execution of instructions. (abbreviated) 100, and a random access memory (indicated by the abbreviation RAM' in the figure) that reads and writes digital data.
(abbreviated as RAM) 200, a peripheral device 250 such as communication with peripheral devices and a timer counter, a first arithmetic unit 300 and a second arithmetic unit 350 that perform arithmetic and logical operations on digital data, and the RAM 200. The peripheral device 25
0 and the input/output terminals of the arithmetic units 300 and 350; and a control bus 450 that controls the RAM 200, the peripheral device 250, and the arithmetic units 300 and 350 based on instructions from the PLA 100. , a timing generator (indicated by the abbreviation TL in the figure) 500 that generates a timing signal for program execution based on the clock signal input to the external clock input terminal 10; a first programmable counter (indicated by the abbreviation PCI in the figure) 600 that selects a particular instruction of the PLA 100 based on the timing generator 500 following selection of an instruction by the first programmable counter 600; a second programmable counter (indicated by the abbreviation PC2 in the figure) that selects a specific instruction of the PLA 100 based on the timing of the instruction; A window 700 (indicated by the abbreviation WD in the figure) for storing or rejecting the starting address of the second programmable counter 650, a RAM address decoder 1500 for decoding the address of the RAM 200, and an address of the peripheral device 250. It has an address decoder 1600 that decodes.

FIG. 2 shows connections among the PLA 100, the first programmable counter 600, the second programmable counter 650, and the window 700. The window 700 includes a pointer (
(indicated by the abbreviation PTR in the figure) 710 and a first programmable counter 650 for reserving a starting address of the second programmable counter 650 from the PLA 100 based on the selection of an instruction by the first programmable counter 600. A window buffer (indicated by the abbreviation WDI in the figure) 720 and a second window buffer (
(indicated by the abbreviation WD2 in the figure) 730, and a first priority storage means (indicated by the abbreviation WD2) for storing the priority of the process to be reserved (
) 740 (indicated by the abbreviation PROL in the figure),
When there is no reservation in the second window buffer 730, the information of the first priority storage means is transferred to the second priority storage means (indicated by the abbreviation PRO2 in the figure) 750, and then the second The start address of the second programmable counter 650 is transferred to the window buffer 730 of The priority of the information in the means 750 is determined, and if the priority of the first priority storage means 740 is higher, the information of the first priority storage means is stored in the second priority storage means 750. After transferring the start address of the second programmable counter 650 to the second window buffer 730, the first priority storage means 74
A priority comparing means (indicated by the abbreviation CMP in the figure) 760 and the second programmable counter 65 which refuses to reserve a new process if the priority of 0 is lower.
a window path 77 that transfers the start address reserved for the window 700 to the second programmable counter 650 when processing of the program by 0 is completed;
It has 0.

The microprocessor configured as described above will be explained using figures.

FIG. 3A shows a signal waveform input to the external clock terminal 10. Next, based on this signal, the data bus 400 is output from the timing generator 500.
The timing charts of the direction switching signals of the first programmable counter 60 are shown in FIGS. 3B and 3C.
Timing charts of switching signals of 0 and the second programmable counter 650 are shown in FIG. 3 and FIG. 3E. FIG. 3F shows a timing chart for switching the control bus 450. This is done by the first programmable counter 600.
100 specific instructions are selected and the instructions are sent to the control bus 450 at the timing marked M in FIG. 3F to execute the program, and then the second programmable counter P by 650
This means that a specific command of the LA 100 is selected and the control bus 4504-6 command is sent at the timing marked S in FIG. 3F to execute the program.

The first programmable counter 600 starts executing the program at the same time as resetting the present microprocessor, and starts the second programmable counter 650 by a certain instruction of the PLA 100 (hereinafter, this instruction will be referred to as an FCAL instruction). do). The second programmable counter 650 continues executing at the timing S in FIG. 3F until a specific instruction of the PLA 100 is executed (hereinafter, this instruction will be referred to as an END instruction).

Next, the sequence of reserving the start address for execution of the second programmable counter 650 using the FCAL instruction will be explained according to the flowchart of FIG. In order to simplify the explanation, the first priority storage means 740 is referred to as PROI, the second priority storage means 750 is referred to as PRO2, and the monitoring pointer 710 is referred to as PTR.
The first window buffer 720 will be written as Wpl, the second window buffer 730 as WD2, and the second programmable counter 650 as PO2. PTR is a pointer with a value between "0" and "2", and the execution address is not stored in PO2 (at this time, at timing S in Figure 3 F, this microprocessor issues an END instruction). or "0" if there is no reservation in WDI and WD2, "1" if the start address of PO2 is reserved only in WDl,
When the start address of PO2 is reserved for both WDI and WD2, it is set to "2".

First, in block 1000, the priority of the process reserved for the PC2 is transferred to the PRO2, and then in block 101
0, the processing to the PC2 is reserved by the FCAL command (setting of the start address of PO2). block 1
At 020, it is determined whether the value of the PTR is "2", and if not, the process proceeds to block 1030. In the block 1030, it is determined that it is still possible to reserve processing for the PC2, and the block 1 is sent to the WD2.
Transfer the start address set in 010.

Since there is no reservation in the WD2, there is no need to compare the processing priorities, so in block 1040, the priority of the PRO2 is transferred to the PROI. next,
At block 1050, it is determined whether the value of the PTR is "1", and if not, the process proceeds to block 1060. In the block 1060, since there is no processing reservation in both the WDI and the WD2, the information of the WD2 transferred in the block 1030 is transferred to the WDI again. Next, in block 1070, 1 is added to the value of the PTR to make it "1", and the process ends in block 1080. If the value of the PTR is “1” in the block 1050,
Moving to the block 1070, the value of the PTR is set to "2".
shall be.

If the value of the PTR is “2” in the block 1020, it is not possible to reserve a new process, so the block 109
0, the priority stored in the PROI and the priority stored in the PRO2 are compared. If the priority stored in the PR01 is higher, the processing will not be exchanged and the processing will end at 0 on the 10th day of the block. Said P
If the priority stored in RO2 is higher, block 1
At step 100, the start address set at block 1010 is transferred to the WD2. Next, block 1120
Then, the priority of PRO2 is transferred to PROL, and the process ends at block 1080.

As described above, the PC 2 executes the END command when the PCI does not set an execution address.

The operation of the END command will be explained using the flowchart of FIG. First, at block 1500, the PTR
It is determined whether the value of is "0" or not. If not, the PC
Block 1510 assumes that there is a reservation for processing from I.
Proceed to. In the block 1510, the WDI information is transferred to the PC 2 and used as an execution address. Next, in block 1520, the information of the WD2 is transferred to the WDI, in block 1530, 1 is subtracted from the value of the PTR, and in block 1540, the process ends. The block 1510
In, if the value of the PTR is "0", the PC
Since there is no processing reservation from I, the process ends at block 1540 without performing any operation.

The information in the first priority storage means 740 stores the priority of the process reserved by the FCAL command executed by the first programmable counter, and
1 in the working area set in the RAM 200 depending on the type of processing by the FCAL command each time a CAL command is executed.
By adding up each step, the execution frequency of the process is expressed as a numerical value, and based on this numerical value, the priority of the process is sequentially determined, thereby realizing a program execution learning means for efficiently executing the program.

Effects of the Invention As described above, there is provided an instruction memory that stores a program consisting of a group of instructions to be executed sequentially, a timing generator that generates an instruction execution timing signal, and a program that is stored in the instruction memory based on the output of the timing generator. a first instruction selection means for sequentially selecting instructions to form a first processing loop; and a first instruction selection means for sequentially selecting instructions to form a first processing loop; a second instruction selection means forming a second processing loop that is in a concurrent relationship with the first processing loop; and the start position that is sequentially specified as the program of the first processing loop is executed. and address information storage means for storing a plurality of program priorities;
When the free area of the address information storage means is filled with reservations for unexecuted programs, the priority of the last stored program and a new program specified according to the execution of the program of the first processing loop are determined. and a priority comparing means for comparing the priorities of the program, and discarding the start position and program priority information last stored in the address storage means in accordance with a signal output from the priority comparing means, and starting a new program execution. address information exchange means for re-storing the specified start position and program priority information in the address information storage means; priority storage means for storing a plurality of priorities of the address storage means; and the priority information The first processing loop includes program execution learning means for optimizing program execution based on the data in the storage means, and the first processing loop terminates the program after specifying the execution start address and priority of the program of the second processing loop. A microprocessor with high processing efficiency can be obtained by having a configuration that allows execution of the next program to start without waiting for the next program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the microbe 0 set of the present invention, and FIG. 2 is a block diagram of the main parts of FIG. 1. FIG. 3 shows a timing chart of the main parts of FIG. 4 and 5 are flowcharts of the operation sequence of the microprocessor of the present invention.
O... Timing generator for PLA, 500... 600... First programmable counter, 650... Second programmable counter, 700... Old... Window counter .

Claims (1)

[Claims] an instruction memory that stores a program consisting of a group of instructions to be executed sequentially; a timing generator that generates an instruction execution timing signal; and a timing generator that sequentially selects the instructions stored in the instruction memory based on the output of the timing generator. a first instruction selection means forming one processing loop, and selecting a stored instruction from a start position specified by the instruction selected by the first instruction selection means to the first processing loop; a second instruction selection means forming a second processing loop in a concurrent relationship; and a plurality of start positions and program priorities that are sequentially specified as the program of the first processing loop is executed. When the free area of the address information storage means is filled with reservations of unexecuted programs, the priority of the last stored program and the execution of the program of the first processing loop are determined. a priority comparing means for comparing the priority of a new program designated with the above; and a starting position and program priority information last stored in the address storing means according to a signal output from the priority comparing means. address information exchange means for discarding and re-storing the designated start position and program priority information in the address information storage means upon execution of a new program; and a priority for storing a plurality of priorities of the address storage means. and a program execution learning means for optimizing program execution based on the data of the priority storage means, and the first processing loop has a program execution start address and a priority of the program of the second processing loop. A microprocessor having a concurrent loop having an instruction for starting execution of the next program without waiting for the end of the previous program after specifying the order.