JPH0424828A - Multi-task control system - Google Patents

Abstract

PURPOSE:To switch the tasks at a high speed and to improve the task executing efficiency in a multi-task control system by controlling the tasks after storing the task executing requests, the task states, and the task control resources including the task priority, etc., into a register. CONSTITUTION:When a task executing request is produced, a task control means 3 writes the information on the request into the corresponding storage unit of a task executing request register 1. When the tasks are carried out, the contents of the registers 1 are checked and the task having the highest priority is selected from among those requested tasks. This selected task is decides as the one to be carried out next. Then the means 3 writes the information showing that the task is ready to be executed into a storage unit of a task state register 2 corresponding to the selected task and then instructs the execution of the task. Thus the tasks are switched at a high speed and the task executing efficiency is improved in a multi-task control system.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a multitask management method for controlling task switching of multitasks.

[Conventional technology]

In conventional multitask management methods such as general-purpose multitask monitors, task switching is performed using a table generally called a task control block (TCB) that stores task management resources such as task status and priority. (For example, "Interface" magazine published by CQ Publishing Co., Ltd., January 1990 issue, No. 139-1)
(See page 94). As an example, the task control block is
It is prepared for each task, each task is assigned a unique task number, and defined as an array of structures. The data structure of each task control block includes elements such as a state classification representing the operating state of the task, a pointer to the task program, stack information allocated to the task, and a pointer to the resource list used by the task. It consists of When starting a task, the state classification of the specified task is changed from the stopped state to the standby state, and then a scheduler that controls the task execution order is called. The scheduler searches the task control blocks defined as an array in order from number 1, selects the first task found in a waiting state, that is, the task in a waiting state with the highest priority, and calls the dispatcher. The dispatcher takes control of the selected task, and the task is executed. When a task finishes executing, it changes the state classification of its own task control number block to the stopped state.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, the task control block is developed on memory, and when there are many task management resources in one memory, the task control block is The frequency of memory access required for referencing and updating task control blocks for determining task switching or executing switching processing increases. Therefore, in the conventional technology, the more frequently tasks are switched, the more the ratio of time required for task switching processing to the original task execution time increases, resulting in poor execution efficiency. The present invention aims to eliminate the drawbacks of the prior art described above. That is, an object of the present invention is to provide a multitask management system that can speed up multitask task switching processing by 1li1' and increase task execution efficiency.

[Means for Solving the Problems] The multitask management method of the present invention has a plurality of memory units corresponding to a plurality of tasks, and the arrangement order of the memory units corresponds to the priority order of the tasks. Each unit has a task execution request register (Figure 1) that stores the status of a task execution request, and multiple storage units corresponding to multiple tasks, and the arrangement order of these storage units is determined by the priority of the task. Based on the contents of the task status register (Fig. 1, 2), which stores the task status in each memory unit, and the task request register, it determines which task has the highest priority, and then determines which task has the highest priority. It stores information indicating the execution state in the memory unit of the task state register corresponding to the task, and also includes task management means (FIG. 1, 3) for instructing the execution of the task. [Operation] When a task execution request occurs, the task management means indicates that there is an execution request in the corresponding memory unit (memory bit element) of the task execution request register, that is, the memory unit assigned to the task. Write information (for example, a binary “1”). Further, when the execution of one task is completed, the task management means writes information indicating that there is no execution request (for example, a binary number "0") into the corresponding storage unit of the task execution request register. In this way, the task execution request register is updated in accordance with the generation and disappearance of execution requests, and always holds the status of the latest task execution request. When executing a task, the contents of the task execution request register are checked to find the task with the highest priority among the tasks for which a task execution request has been made, and this is determined as the task to be executed next. Next, the task management means writes information (binary number "1") indicating that the task is in the execution state into the storage unit of the task status register corresponding to the determined task, and instructs the execution of the task. . If there is no execution request for any task, control is passed to a background task that is executed only in that case. Note that the state of a task is, for example: ■ A stopped state where there is no execution request and is not in a running state, ■ A state where an execution request has been made but it has not started execution yet, ■ A state in which a task is being executed or when execution is interrupted. In some cases, the program may be suspended due to some reasons. According to the present invention, tasks are managed by holding task management resources such as task execution requests, task states, and priorities in registers, thereby speeding up multitasking task switching processing and improving task execution efficiency. It can be made higher. In addition, the data structure is simplified by using only the minimum necessary task management resources, which, together with the use of registers that do not require memory access, further increases task execution efficiency. I can do it.

[Examples] The present invention will be described in detail below using examples shown in the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram for explaining the configuration of the register in FIG. 1. As shown in FIG. 1, this embodiment includes a task execution request register 1 that stores execution requests for each task and a task status register 2 that stores the status of each task for each task. It includes a scheduler (task management means) 3 that manages task switching, and a task group 4 that includes a plurality of tasks. Task execution request register 1 and task status register 2
is n corresponding to n+1 tasks #0 to #n, respectively.
It has +1 bit storage location. That is, each bit of the register is associated with a task having a task number equal to the bit number. Therefore, the number of bits that are the sizes of these two registers influences the number of tasks that can be controlled by the method of this embodiment. Further, the value of the task number represents the priority, and the magnitude relationship between the values is expressed as the priority. Each bit of the task execution request register 1 indicates whether there is an execution request for the corresponding task. As shown in Figure 4, "0" indicates that there is no execution request, and '1' indicates that there is an execution request. is interrupted by the execution of ( Pre
It is “l” if it is in the empty state or currently running (Run), and otherwise it is
e, Ready) is “0”. As shown in Figure 3, the status of the task is "Stopped (
Coi+plete)"rReady J
rRun J ``Pree++pted''
There are four states of J. "Stopped" means that there is no execution request, "Waiting" means that an execution request has been issued but the execution right has not been obtained, and "Running" means that the execution right has been acquired and the task is "Suspended" means that it is running.
means a state in which a task that was in an execution state has its processing interrupted due to execution of an interrupt processing routine. The relationship between the above four states and the corresponding bits of each register is that if the value of task execution request register 1 is "0", the state is stopped, and the value of task execution request register 1 is "1" and the value of task status register 2. If the value is "0", it represents a standby state, and if the value of the task execution request register 1 is "1" and the value of the task status register 2 is "1", it represents a suspended state or an execution state. . The scheduler 3 uses the task execution request register 1 and the task status register 2 to control and manage task switching. In each of the following cases (1) (2) (3)
) The processing of the scheduler 3 will be explained separately. (1) Generation of a task execution request The task requesting execution sets the bit corresponding to the requested task in the task execution request register 1 to "1" to notify the scheduler 3 of the generation of an execution request to that task. The scheduler 3 refers to the task execution request register l, and if the priority of the requested task is the highest among the tasks for which an execution request has been issued at that time, the corresponding bit of the task status register 2 is set to "1". ” to indicate that the task is running and then immediately start running the task. In other cases, processing of the task that requested execution is resumed. (2) Termination of task execution When the execution of a certain task is finished, first the scheduler 3
is task execution request register l and task status register 2
The corresponding bits in the two registers are set to "0" to indicate that the requested execution has been completed and the task is in the "stopped" state. In this way, the execution of the task with the highest priority is completed, and the task with the next highest priority is searched for by looking at the two registers 1 and 2. If the state of the task with the highest priority is "suspended" or if there is no task that has an execution request, execute the task that was being executed immediately before the task that finished executing. return rights. Otherwise, if the task in the "standby" state has the highest priority, execution of that task is newly started. (3) Occurrence of interrupt When an interrupt occurs, the interrupt processing routine associated with the interrupt is executed. If there is a task being executed at this time, the state of that task is transitioned from "executing" to "suspended." After the execution of the interrupt processing routine is completed, the tasks that were being executed before the occurrence of the interrupt are returned to the "executing" state. It is also possible to issue an execution request to any task within this interrupt processing routine. In that case, the task to be executed next is determined by the same process as the process at the end of task execution in the previous section (2). The basic operation of this embodiment has been explained above, and now the operation will be explained using a specific example. FIG. 5 is a diagram showing an example of an operation flow. Here, it is assumed that there are two 32-bit registers, and these are assigned as task execution request register 1 and task status register 2, respectively. Furthermore, for the sake of explanation, a configuration of task #1 and task #2 will be defined. The scheduler 3 first initializes the task execution request register 1 and the task status register 2 (step 5 in Figure 5).
1). Assume that an execution request is issued from task #1, which is currently in the execution state, to task #2, which is in the stopped state and has not received any execution request. Then, first, the requesting task indicates that it wants the requested task to be executed by setting the bit of the requested task in the task execution request register 1 to "1" (step 53). Here, the scheduler 3 compares the priorities of the requesting task and the requesting task and transfers the execution right to the task with the higher value (step 54). As a result, if the one with the higher priority is the request source, the request source task continues to be executed without any further steps. Conversely, if the requested task has a higher priority, the bit in the task status register 2 is set to "1" to indicate that the task has entered the execution state (step 56). and,
Start execution of the task (step 57). In the example of FIG. 6, task #2 has a higher priority, so task #2 is executed immediately. When the execution of the task ends, control is passed to the scheduler 3. Here, among the bits in the task execution request register 1 and the task status register 2, the bit corresponding to the task that has finished execution is set to "0", and the presence of the execution request and the indication that it is in the execution state are erased (step 58.59). Then, since there is only one task with an execution request displayed and the highest priority, that is, task #1 in the case of FIG. 6, the execution right is returned to task #1 (step 54).
. If there are no more tasks to execute, control is transferred to a background task and waits for a new task execution request. The above is an example of the basic task switching operation. Next, an example of the operation when an interrupt occurs will be explained. As shown in FIG. 7, it is assumed that an interrupt occurs during the execution of task #1. Control then passes to the interrupt handling routine associated with this interrupt. In this example, task #2 is executed in this interrupt handling routine.
shall be required to carry out the following. For this purpose, the bit of task #2 in task execution request register 1 is set to "1". Thereafter, when this interrupt handling routine ends, the task is scheduled again, and as a result, task #1 that is newly requested to be executed in the interrupt handling routine is given priority over task #1 that was being executed before the interrupt occurred. Since task #2 has a higher priority, it does not return to task #1.
2 is started. [Effects of the Invention] According to the present invention, task management resources such as task execution requests, task states, priorities, etc. are held in registers to manage tasks, thereby speeding up multitasking task switching processing. Task execution efficiency can be increased. In addition, the present invention uses only the minimum necessary resources as task management resources and has an open-circuit data structure, so in conjunction with the use of registers that do not require memory access,
It can further improve task execution efficiency and is useful as a simple task monitor.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram for explaining the configuration of the register in FIG. 1. FIG. 3 is a diagram for explaining the transition of the operational state of a task. FIG. 4 is a diagram showing the correspondence between the state of a task and the value of each register. FIG. 5 is an operation flow diagram showing an example of the operation of the embodiment of the present invention. FIG. 6 is a diagram for explaining task switching. FIG. 7 is a diagram for explaining task switching due to an interrupt. DESCRIPTION OF SYMBOLS 1...Task execution request register, 2...Task status register, 3...Scheduler, 4...Task execution means. Patent Applicant Fuji Xerox Co., Ltd. Agent Patent Attorney Iwatori Figure 1 High priority bit number Low priority Figure 3 Figure 4 Figure 6 Figure 7

Claims (1)

[Claims] A task execution system that has a plurality of memory units corresponding to a plurality of tasks, the arrangement of these memory units corresponds to the priority of the tasks, and the presence or absence of a task execution request is stored in each memory unit. a request register; a task state register having a plurality of storage units corresponding to a plurality of tasks, an arrangement of the storage units corresponding to the priorities of the tasks, and storing the state of the task in each storage unit; Based on the contents of the register, it is determined which task has the highest priority, and information indicating that the task is in the execution state is stored in the memory unit of the task status register corresponding to that task. A multi-task management method characterized by comprising a task management means for instructing execution.