JPH03155367A - Inverter unit - Google Patents

Inverter unit

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Publication number
JPH03155367A
JPH03155367A JP29162289A JP29162289A JPH03155367A JP H03155367 A JPH03155367 A JP H03155367A JP 29162289 A JP29162289 A JP 29162289A JP 29162289 A JP29162289 A JP 29162289A JP H03155367 A JPH03155367 A JP H03155367A
Authority
JP
Japan
Prior art keywords
circuit
pulse
signal
output
drive signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29162289A
Other languages
Japanese (ja)
Inventor
Kazuki Era
和樹 江良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP29162289A priority Critical patent/JPH03155367A/en
Publication of JPH03155367A publication Critical patent/JPH03155367A/en
Pending legal-status Critical Current

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  • Dc-Dc Converters (AREA)

Abstract

PURPOSE:To prevent chopper miss by controlling a chopper circuit through a minimum ON pulse circuit when PWM control is carried out based on a carrier produced on the basis of an AC input to an inverter and an output voltage from the chopper circuit. CONSTITUTION:AC carrier 12 is detected from an AC input power supply through a PT 8 and inputted to the PWM controller 9 for a drive signal generating circuit 7, an ON pulse circuit 15 and a base-up circuit 10. On the other band, a DC signal outputted from a booster chopper circuit 2 is detected 3 and an FB signal 11 is inputted to the PWM controller 9. The PWM controller 9 compares the signals 12, 11 each other to produce a pulse signal 13, and the minimum ON pulse circuit 15 forms a signal 14 in which dead time DT is removed from the carrier 12 then the signal 14 is amplified through the base-up circuit 10 and employed for control of the gate of a transistor Tr 6. By such arrangement, miss chopping of the Tr 6 due to a short pulse can be prevented resulting in a highly accurate inverter.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は順変換器の直流出力をチョッパ回路を介して
負荷に供給するインバータ装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inverter device that supplies DC output of a forward converter to a load via a chopper circuit.

[従来の技術] 第4図は従来のインバータ装置を示すブロック図である
。第4図において、交流入力を直流出力に変換する順変
換器(1)は、その直流出力端子P、N間に昇圧チョッ
パ回路(2)と電圧検出回路(3)が並列に接続されて
いる。
[Prior Art] FIG. 4 is a block diagram showing a conventional inverter device. In Fig. 4, a forward converter (1) that converts AC input into DC output has a boost chopper circuit (2) and a voltage detection circuit (3) connected in parallel between its DC output terminals P and N. .

上記昇圧チョッパ回路(2)は、順変換器(1)と並列
接続したコンデンサ(4)と、このコンデンサ(4)に
リアクタンス(5)を介して並列接続したトランジスタ
(6)と、このトランジスタ(6)のコレクタと電圧検
出回路(3)の接続路に設けたダイオード(29)とで
構成されている。
The step-up chopper circuit (2) includes a capacitor (4) connected in parallel with the forward converter (1), a transistor (6) connected in parallel with this capacitor (4) via a reactance (5), and this transistor ( 6) and a diode (29) provided in the connection path between the voltage detection circuit (3) and the collector.

上記トランジスタ(6)のベースに駆動信号を供給する
駆動信号発生回路(7)は、電圧検出回路(3)の検出
電圧と交流入力を変成したトランス(8)からの搬送波
(12)を比較するPWN制御器(パルス幅制御器)(
9)と、上記搬送波(12)及びPWM制御器(9)か
ら出力された駆動信号(14)電圧を入力するベースア
ンプ回路(10)とで構成されている。
A drive signal generation circuit (7) that supplies a drive signal to the base of the transistor (6) compares the detected voltage of the voltage detection circuit (3) with a carrier wave (12) from a transformer (8) that transforms the AC input. PWN controller (pulse width controller) (
9), and a base amplifier circuit (10) which receives the carrier wave (12) and the drive signal (14) voltage output from the PWM controller (9).

次に動作について説明する。電圧検出回路(3)は直流
出力端子P、 N間の直流出力電圧を検出し、この検出
電圧に基づ< F/B信号(11)をPWM制御器(9
)に供給する。
Next, the operation will be explained. The voltage detection circuit (3) detects the DC output voltage between the DC output terminals P and N, and based on this detected voltage, the F/B signal (11) is sent to the PWM controller (9
).

このPWM制御器(9)は取り込まれたF/B信号(1
1)と、第2図に示す搬送波(12)とをただ単純に比
較してパルス信号(13)を得、このパルス信号13か
ら上記搬送波(12)の下り勾配部の期間(デッドタイ
ム)DTを除いて駆動信号(14)を得ている。
This PWM controller (9) controls the captured F/B signal (1
1) and the carrier wave (12) shown in FIG. 2 are simply compared to obtain a pulse signal (13), and from this pulse signal 13, the period (dead time) DT of the downward slope portion of the carrier wave (12) is calculated. A drive signal (14) is obtained except for.

この駆動信号(14)はベースアップ回路(10)で増
幅された後、トランジスタ(6)のベースに供給されて
該トランジスタを駆動させ、昇圧チョッパ(2)を作動
させ、順変換器(1)の直流出力を昇圧して、直流出力
端子P、Nに接続された負荷(図示せず)に供給する。
This drive signal (14) is amplified by the base up circuit (10) and then supplied to the base of the transistor (6) to drive the transistor, operate the boost chopper (2), and convert the forward converter (1). The DC output is boosted and supplied to a load (not shown) connected to DC output terminals P and N.

[発明が解決しようとする課題] 従来のインバータ装置は以上のように構成されているの
で、電圧検出回路(3)からのF/B信号(11)と搬
送波(12)を比較して得たパルス信号(13)からデ
ッドタイムDTを除くだけである。このため、PWM制
御器(9)からの駆動信号(14)のパルス幅が例えば
駆動信号(14a)のように極く短くなった場合、この
駆動信号(14a)に基づいて駆動信号発生回路(7)
から駆動信号(14)が出力されるにも拘らず、トラン
ジスタ(6)は駆動せず、昇圧チョッパ(2)の動作が
不安定になるという問題点があった。
[Problem to be solved by the invention] Since the conventional inverter device is configured as described above, the F/B signal (11) from the voltage detection circuit (3) and the carrier wave (12) are compared. The dead time DT is simply removed from the pulse signal (13). Therefore, when the pulse width of the drive signal (14) from the PWM controller (9) becomes extremely short, for example, as in the drive signal (14a), the drive signal generation circuit ( 7)
Despite the drive signal (14) being output from the transistor (6), the transistor (6) is not driven, resulting in an unstable operation of the boost chopper (2).

この発明は上記のような問題点を解消することを課題に
なされたもので、PWM制御器から出力される駆動信号
のパルス幅が極く短い場合でも確実にチョッパ回路を動
作させることができる動作の安定したインバータ装置を
得ることを目的とする。
This invention has been made to solve the above-mentioned problems, and has an operation that allows the chopper circuit to operate reliably even when the pulse width of the drive signal output from the PWM controller is extremely short. The purpose is to obtain a stable inverter device.

[課題を解決するための手段] この発明に係るインバータ装置は、チョッパ回路を確実
に動作させるように、PWM制御器がら出力された駆動
信号の最小ON時間を制御する最小ONパルス回路を駆
動信号発生回路に具備したものである。
[Means for Solving the Problems] The inverter device according to the present invention uses a drive signal to control a minimum ON pulse circuit that controls the minimum ON time of a drive signal output from a PWM controller so as to reliably operate a chopper circuit. This is included in the generating circuit.

C作用コ この発明における最小ONパルス回路は、PWM制御器
から出力された駆動信号の最小ON時間をチョッパ回路
を確実に動作させるように制御することにより、出力精
度の高いインバータ装置を得ることを可能とする。
C Effect: The minimum ON pulse circuit in this invention achieves an inverter device with high output accuracy by controlling the minimum ON time of the drive signal output from the PWM controller so as to reliably operate the chopper circuit. possible.

[実施例コ 以下、この発明の実施例を図面について説明する。前記
第4図と同一部分に同一符号を付した第1図において、
最小ONパルス回路(15)はPWM制御器(9)の出
力側に設けられている。
[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIG. 1, in which the same parts as in FIG. 4 are given the same reference numerals,
The minimum ON pulse circuit (15) is provided on the output side of the PWM controller (9).

上記の最小ONパルス回路(15)は第2図に示すよう
に、PWM制御器(9)からのパルス信号を一方の入力
とするオアーゲート(16)と、時定数回路を形成する
抵抗(17)及びコンデンサ(18)、オアーゲート(
16)の出力と時定数回路の出力を入力とするモノステ
ーブルマルチバイブレータ(19)とPWM制御器(9
)の出力とモノステーブルマルチバイブレータ(1つ)
の出力を入力とするEX−ORロジック回路(20)と
、抵抗(21)を介して入力したEX−ORロジック回
路(20)の出力を抵抗22〜25で規定した基準値と
比較するコンパレータ(26)とで構成されている。
As shown in Fig. 2, the above minimum ON pulse circuit (15) consists of an OR gate (16) whose one input is the pulse signal from the PWM controller (9), and a resistor (17) forming a time constant circuit. and capacitor (18), or gate (
A monostable multivibrator (19) and a PWM controller (9) whose inputs are the output of 16) and the output of the time constant circuit.
) output and monostable multivibrator (1)
an EX-OR logic circuit (20) whose input is the output of the EX-OR logic circuit (20), and a comparator ( 26).

次に上記実施例の動作について説明する。順変換器(1
)は交流入力を直流出力に変換して出力する。昇圧チョ
ッパは上記出力を昇圧して負荷に供給する。電圧検出部
(3)は上記昇圧チョッパの出力電圧を検出し、検出電
圧に基づ(F/B信号(11)をPWM制御器(9)に
供給する。このPWM制御器(9)はF/B信号(11
)とトランス(8)で変成した交流入力に基づく搬送波
(12)とを比較しパルス信号(13)を得るとともに
、このパルス信号(13)から搬送波(12)のデッド
タイムDTを除いて駆動信号(14)を出力する。
Next, the operation of the above embodiment will be explained. Forward converter (1
) converts AC input into DC output and outputs it. The boost chopper boosts the output and supplies it to the load. The voltage detection section (3) detects the output voltage of the step-up chopper, and supplies the F/B signal (11) to the PWM controller (9) based on the detected voltage. /B signal (11
) and the carrier wave (12) based on the AC input transformed by the transformer (8) to obtain the pulse signal (13), and remove the dead time DT of the carrier wave (12) from this pulse signal (13) to obtain the drive signal. (14) is output.

この駆動信号(14)はオアーゲート(16)を介して
モノステーブルマルチバイブレーク(19)に入力され
る。このモノステーブルマルチバイブレータ(19)内
においては駆動信号(14)の立上がりエツジにてトリ
ガーをかけ、コンデンサ(17)、抵抗(18)の時定
数回路にて決定されるパルス信号を出力する。このパル
ス信号と別系路にてPWM制御器(9)から供給された
駆動信号(14)とをEX−ORロジック回路(20)
にて論理を行なう。
This drive signal (14) is input to a monostable multi-by-break (19) via an OR gate (16). This monostable multivibrator (19) is triggered at the rising edge of the drive signal (14) and outputs a pulse signal determined by a time constant circuit of a capacitor (17) and a resistor (18). This pulse signal and the drive signal (14) supplied from the PWM controller (9) through a separate path are connected to the EX-OR logic circuit (20).
Do the logic.

これにより、どのように短いパルス幅の駆動信号(14
)であっても、この駆動信号(14)の立ち下がりエッ
ヂを検知して該駆動信号の最小ON時間を制御し、この
制御後の駆動信号をコンパレータ(26)で整形を行な
った後、ベースアップ回路(10)へ出力する。
This shows how the short pulse width drive signal (14
), the falling edge of this drive signal (14) is detected to control the minimum ON time of the drive signal, and the drive signal after this control is shaped by a comparator (26), and then the base Output to up circuit (10).

ベースアンプ回路(10)は入力された駆動信号(14
)を増幅してトランジスタ(6)のベースに供給して該
トランジスタを導通させ、これによって、昇圧チョッパ
回路(2)を作動させて順変換器(1)から出力された
直流出力を昇圧するもので、このベースアンプ回路(1
0)の動作は前記第4図に示す従来例と同じである。
The base amplifier circuit (10) receives the input drive signal (14).
) is amplified and supplied to the base of the transistor (6) to make the transistor conductive, thereby operating the boost chopper circuit (2) and boosting the DC output output from the forward converter (1). So, this bass amplifier circuit (1
0) is the same as the conventional example shown in FIG. 4.

なお、上記実施例では昇圧チョッパ回路を確実に作動さ
せるための駆動信号の最小ON時間を制御する最小ON
パルス回路(15)について説明したが、降圧チョッパ
回路の最小ONパルス回路であってもよい。
In addition, in the above embodiment, the minimum ON time that controls the minimum ON time of the drive signal to reliably operate the boost chopper circuit is
Although the pulse circuit (15) has been described, it may be a minimum ON pulse circuit of a step-down chopper circuit.

また、上記実施例では最小ONパルス回路(15)をモ
ノステーブルマルチバイブレータを用いて構成した場合
について説明したが、前記第2図と同一部分に同一符号
を付した第5図に示すように、フィルタ回路(27)と
ヒステリシス特性を持つコンパレータ(28)との組合
せで構成しても、上記実施例と同様の効果を奏する。
Furthermore, in the above embodiment, the minimum ON pulse circuit (15) was constructed using a monostable multivibrator, but as shown in FIG. 5, in which the same parts as in FIG. 2 are given the same reference numerals, Even if the filter circuit (27) is configured in combination with a comparator (28) having hysteresis characteristics, the same effects as in the above embodiment can be obtained.

[発明の効果] 以上のように、この発明によれば、チョッパ回路を確実
に作動させるパルス幅に駆動信号を制御するように構成
したので、出力精度の高いインバータ装置が得られる効
果がある。
[Effects of the Invention] As described above, according to the present invention, since the drive signal is configured to be controlled to a pulse width that reliably operates the chopper circuit, there is an effect that an inverter device with high output accuracy can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例によるインバータ装置を示
すブロック図、第2図は最小ONパルス回路を示す回路
図、第3図はその最小ONパルス回路の他の例を示す回
路図、第4図は従来のインバータ装置のブロック図、第
5図はPWM制御器の動作を説明する信号波形図である
。 図において、(1)は順変換器、(2)は昇圧チョッパ
回路、(3)は電圧検出回路、(9)はPWM制御器、
(15)は最小ONパルス回路である。 なお、図中同一符号は同一または相当部分を示す。
FIG. 1 is a block diagram showing an inverter device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a minimum ON pulse circuit, FIG. 3 is a circuit diagram showing another example of the minimum ON pulse circuit, and FIG. FIG. 4 is a block diagram of a conventional inverter device, and FIG. 5 is a signal waveform diagram illustrating the operation of a PWM controller. In the figure, (1) is a forward converter, (2) is a boost chopper circuit, (3) is a voltage detection circuit, (9) is a PWM controller,
(15) is a minimum ON pulse circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 交流入力を直流出力に変換する順変換器と、前記直流出
力を断続するチョッパ回路と、 前記チョッパ回路の出力電圧を検出する電圧検出回路と
、 前記電圧検出回路の検出電圧と前記交流入力に基づく搬
送波とを比較することにより駆動信号を出力するPWM
制御器と該駆動信号の最小ON時間を制御する最小ON
パルス回路とを有する駆動信号発生回路とを具備したイ
ンバータ装置。
[Scope of Claims] A forward converter that converts an AC input into a DC output, a chopper circuit that intermittents the DC output, a voltage detection circuit that detects the output voltage of the chopper circuit, and a detection voltage of the voltage detection circuit. and a carrier wave based on the AC input to output a drive signal.
Minimum ON that controls the minimum ON time of the controller and the drive signal
An inverter device comprising a drive signal generation circuit having a pulse circuit.
JP29162289A 1989-11-08 1989-11-08 Inverter unit Pending JPH03155367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29162289A JPH03155367A (en) 1989-11-08 1989-11-08 Inverter unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29162289A JPH03155367A (en) 1989-11-08 1989-11-08 Inverter unit

Publications (1)

Publication Number Publication Date
JPH03155367A true JPH03155367A (en) 1991-07-03

Family

ID=17771341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29162289A Pending JPH03155367A (en) 1989-11-08 1989-11-08 Inverter unit

Country Status (1)

Country Link
JP (1) JPH03155367A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0564451A (en) * 1991-09-04 1993-03-12 Yamaha Corp Power source apparatus
JP2008067502A (en) * 2006-09-07 2008-03-21 Honda Motor Co Ltd Inverter device and inverter device control method
KR101686449B1 (en) * 2016-06-13 2016-12-14 김옥수 Functionality Korean traditional dress

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0564451A (en) * 1991-09-04 1993-03-12 Yamaha Corp Power source apparatus
JP2008067502A (en) * 2006-09-07 2008-03-21 Honda Motor Co Ltd Inverter device and inverter device control method
KR101686449B1 (en) * 2016-06-13 2016-12-14 김옥수 Functionality Korean traditional dress

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