JPH03154572A - Dc reproduction circuit and synchronizing separator circuit and television receiver using either of them - Google Patents

Abstract

PURPOSE:To reduce the response time and to prevent malfunction by detecting a peak value of a synchronizing signal in a composite video signal with a DC bias applied thereto and controlling the applied DC bias in response to the result of comparison between the peak value and a preset object value. CONSTITUTION:A peak value detection means 4 detects a peak value of a synchronizing signal in a composite video signal. The fluctuation of the valve means that the DC level of the composite video signal is fluctuated. Then the peak value is compared with an object value at a comparator means, the DC level fluctuation is detected and the DC bias applied to the composite video signal is controlled in response to the result by a DC bias control means 3 to apply DC reproduction of the composite video signal. Thus, the response time is reduced and malfunction is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DC reproduction circuit for composite video signals, a synchronous separation circuit, and a television receiver having either one of them.

[Conventional technology]

FIG. 6 shows a conventional DC regeneration circuit used to separate a synchronization signal from a composite video signal. A positive polarity composite video signal (No. 8) is input to the input terminal 1, and the output is taken out from the output terminal 5. When the voltage is lower than the voltage generated by the electromotive force 12, the diode 9 charges ONL and the input capacitor 2, increasing the DC bias.When the peak value is higher than the voltage generated by the electromotive force 12, the diode 9
is not turned on, and the electric charge of the input capacitor 2 is discharged by the discharge resistor 8, thereby lowering the DC bias of the output @5. Through the above operations, DC reproduction of the composite video signal is performed.

Further, there is a device that performs the above operation using a transistor, as described in Japanese Patent Laid-Open No. 138884/1984.

However, in both cases, although it is easy to charge the input capacitor 2, discharging is performed only by the discharging resistor 8, so when an input signal that requires prompt discharging is input, it takes a long time to respond. It is difficult to obtain good characteristics.

A circuit that has solved these problems has been proposed for use in television cameras and is described in Japanese Patent Application Laid-Open No. 55-33365. However, this circuit requires clamp pulses and sample pulses that are in phase with the video signal and supplied by a stable timing generator, and is not suitable for use in television receivers.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, when a video signal whose screen brightness suddenly changes is input, the DC bias must be changed in response, but there are problems such as the response takes time and waveform distortion occurs during response. was there.

Moreover, this causes a malfunction of the synchronous circuit connected to the subsequent stage, and there is a problem that good operation of the deflection circuit cannot be obtained or is difficult to obtain. Moreover, for this reason, there have been problems in television receivers having these circuits, such as one screen being distorted.

An object of the present invention is to provide a DC regeneration circuit that does not take much time to respond and can provide good characteristics.

Another object of the present invention is to provide a synchronous circuit that does not malfunction.

Another object of the present invention is to provide a television receiver in which the screen does not become distorted or blurred.

[Means to solve the problem]

In order to achieve the above object, the present invention provides means for inputting a composite video signal to which a DC bias is applied and detecting a peak value of a synchronization signal in the composite video signal; The present invention is configured to include means for comparing a preset target value and means for controlling the DC bias added to the composite video signal in accordance with the comparison result.

[Effect]

The peak value detection means detects the peak value of the synchronization signal in the composite video signal. A change in this value means that the DC level of the composite video signal changes. Therefore, the peak value is compared with the target value by the comparison means to detect DC level fluctuation, and the DC bias applied to the 5 composite video signals is controlled by the control means in accordance with the result. Thereby, the DC level of the composite video signal can be stabilized and DC reproduction can be performed. Therefore, since the DC level is stabilized, the synchronous separation circuit will not malfunction.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

It passes through a capacitor 2 and is input to a peak detection circuit 4.

A peak detection circuit 4 detects the peak value of the composite video signal and inputs it to the DC bias control circuit 3.

A DC bias control circuit 3 compares the peak value signal with a target value, and controls the DC bias applied to the input capacitor 2 according to the comparison result. Through the above operations, a composite video signal reproduced by direct current can be obtained at the output end 5.

The output signal from the output terminal 5 is input to the synchronization separation circuit 6. The synchronization separation circuit 6 slices the input signal according to the slice level, separates the synchronization signal, and outputs it to the synchronization signal output terminal 7.

Next, FIG. 2 shows a specific printing example of the embodiment shown in FIG. 1, and FIG. 3 shows the main signal waveforms thereof.

An input signal is input to input terminal 1. The input signal is input to the peak detection circuit 4 after passing through the input capacitor 2 . The peak detection circuit 4 includes a buffer 13 and a diode 14.1.
5, hold capacitor 20, 21, switch (hereinafter abbreviated as SW) A18, 5WB19, and protective resistor 1
6.17 and a composite video signal are input from the input terminal 1, and the input comp peak detection circuit 4 holds the peak value in the input No. 43 and outputs the hold A (No. 8 3a and hold B signal 3b).
get. And synchronous oscillation timing control 28
Therefore, 5WA18 and 5WB19 are alternately 2 L-I
It turns ON and OFF periodically and is reset. In addition, by alternately switching the hold A signal 3a and hold B signal 3b by 5WC22 for each IH, the peak signal
get c.

Next, the peak signal 3c is input to the DC bias control circuit 3. The DC bias control circuit 3 compares the peak signal 3c with a target value 23 using a comparator 24, and determines the DC bias 3d.
get. Then, a DC bias 3d is applied to the input capacitor 2 via the protective resistor 25 to obtain a DC reproduction output 3e.

Next, the DC reproduction output 3e is input to the synchronous separation circuit 6. The sync separation circuit 6 obtains a sync separation output 3f by comparing the DC reproduction output 3e with a slice level 27 using a comparator 26. Next, the synchronous separation output 3f is outputted from the synchronous separation output terminal 7 and is also input to the synchronous oscillation timing control circuit 28. When the synchronous oscillation timing control circuit 28 receives the synchronous separation output 3f, the 5WA18.5WB19 ON-〇FF signal,
Obtain the control 1-roll signal of 5WC20 and horizontal synchronization.

Obtain vertical synchronization and horizontal synchronization signal output terminal 30. It is output to the vertical synchronization signal output terminal 31.

According to this embodiment, two hold capacitors 20 and 2
1 is reset by 5WA18 and 5WB19, the response speed is fast and a stable DC reproduction output can be obtained, so the comparator 26 in the synchronization separation port vJe does not malfunction, and the output 35 is obtained for good synchronization. Also, 5WA
Since the synchronous oscillation timing control circuit 28 and SW B 19 are turned ON and OFF in 2H cycles, the synchronous oscillation timing control circuit 28 can operate stably even when it is not synchronized with the input signal.

Further, according to this embodiment, except for the input capacitor 2, the I
Since it can be converted into a C, the DC regeneration circuit can be converted into an IC and the number of parts can be reduced.

In addition, in this embodiment, 5WA18 and 5WB for reset
19 is connected to the power supply through the hold capacitor 20.21 and the protective resistor 16.17, but the same effect can be obtained by connecting the diodes 14.15 so as to short-circuit them. Further, the target value 23 may be made variable.

Next, another embodiment of the present invention is shown in FIG. 4, and the main signal waveforms thereof are shown in FIG. 5.

The composite video equal signal input from the input terminal 1 is sent to the adder 23
DC bias is given by (In the embodiment shown in FIG. 1 above, DC bias was applied by charging the input capacitor.) Furthermore, the peak value is detected by the peak detection circuit 34, and the sample and hold times v! 33, and is compared with the target value 23 by the comparator 24 in the DC bias control circuit 36 to obtain an error signal, which is input to the adder 32 as the DC bias 4d to perform DC reproduction. The synchronous separation circuit 6 converts the DC-reproduced composite video equal signal into a synchronous component i.
ff! The sample pulse 4b to be input to the sample hold circuit 33 and the reset pulse 4a to be input to the peak detection circuit 34 are respectively created by the synchronous oscillation timing controller I to roll circuit 35 to improve the stability of the operation. .

In this embodiment, since the peak detection circuit 34 detects the peak value and the sample hold circuit 33 performs the operation of holding it in the same IH cycle, the synchronous oscillation timing control circuit 35 is not synchronized with the input composite video signal. DC regeneration can be performed stably.

〔Effect of the invention〕

As explained above, according to the present invention, since the response time is short and good characteristics are obtained, it is possible to obtain a composite synchronization signal with a stable DC level as the DC reproduction output.

Therefore, by using such a DC reproduction output, the synchronous separation circuit will not malfunction and a stable synchronous separation output can be obtained.

Moreover, for this reason, one screen of a television receiver will not be distorted or distorted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific circuit configuration of the embodiment of FIG. 1, and FIG.
The figure is a waveform diagram showing the main signal waveforms of FIG. 2, and FIG. 4 is another actual M! of the present invention! FIG. 5 is a waveform diagram showing essential signal waveforms in FIG. 4, and FIG. 6 is a circuit diagram showing a conventional DC regeneration circuit. 1...Input end, 2...Input capacitor. 3...DC bias control circuit, 4...Peak detection circuit. 5...Output end, 6...Synchronization part is the circuit. 7... Synchronization signal output terminal.萬子1-・-Input boy? ...Irukakoreko no sa 3-・Naobonno<I7th 帛I) Sankute [Ubi-awn 4--Hi゛-7 Volume Muro ``To 5-Out, Kahai 6, g--1 Interperiod production difficulty red 7--Synchronization No. 1 second audience first solid shoulder section θ~ WAoFF hanging 4 1- input wall 24--one comparison 1 I Mihii Kazuichi/)-1-s

Claims (1)

[Claims] 1. Input a composite video signal to which a DC bias has been added;
means for detecting a peak value of a synchronization signal in the composite video signal; means for comparing the detected peak value with a preset target value; means for controlling the DC bias;
A DC regeneration circuit comprising: 2. Synchronization in the composite video signal is achieved by inputting the composite video signal to which the DC bias is applied in the DC reproduction circuit according to claim 1 and comparing the composite video signal with a certain DC level. A synchronous separation circuit characterized by separating signals. 3. A television receiver comprising the DC regeneration circuit according to claim 1. 4. A television receiver comprising the sync separation circuit according to claim 2.