JPH03154324A - Device and method for pattern exposure - Google Patents

Device and method for pattern exposure

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Publication number
JPH03154324A
JPH03154324A JP1292332A JP29233289A JPH03154324A JP H03154324 A JPH03154324 A JP H03154324A JP 1292332 A JP1292332 A JP 1292332A JP 29233289 A JP29233289 A JP 29233289A JP H03154324 A JPH03154324 A JP H03154324A
Authority
JP
Japan
Prior art keywords
exposure
baking
wafer
pattern
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1292332A
Other languages
Japanese (ja)
Other versions
JP3020523B2 (en
Inventor
Hidenori Yamaguchi
山口 秀範
Osamu Suga
治 須賀
Fumio Murai
二三夫 村井
Shinji Okazaki
信次 岡崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1292332A priority Critical patent/JP3020523B2/en
Publication of JPH03154324A publication Critical patent/JPH03154324A/en
Application granted granted Critical
Publication of JP3020523B2 publication Critical patent/JP3020523B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To eliminate instability of a chemical amplification system resist material by providing a baking device for performing bake treatment continuously during and after exposing a substrate. CONSTITUTION:Each wafer 3 after exposure has the same time up to baking by providing a bake device 4 at the inside of an exposure device 15 or around it. Namely, by performing exposure and bake treatment consistently to each wafer, change of a catalysis within a resist with time can be made to be constant for each wafer, thus enabling fluctuation of pattern dimensions between wafers caused by change of catalysis with time which is proper to a chemical amplification system resist material with a high sensitivity, high resolution, and high dry etching resistance to be avoided.

Description

【発明の詳細な説明】[Detailed description of the invention]

I産業上の利用分野】 本発明はULSI製造などにおけるリソグラフィ技術に
係り、特に化学増幅系レジストを用いた制御性・安定性
の高いリソグラフィープロセスを実現する図形露光装置
とその方法に関する。
I. Field of Industrial Application The present invention relates to lithography technology in ULSI manufacturing, etc., and more particularly to a pattern exposure apparatus and method for realizing a lithography process using a chemically amplified resist with high controllability and stability.

【従来の技術】[Conventional technology]

ULSIの高集積・高密度化は3年に4倍の勢いで進め
られており、厩に4メガビツトd RAMの量産化およ
び16メガビツトdRAMの試作がなされている。これ
に伴って微細加工に要求される寸法は0.8μmから0
.5μm、さら番ご0゜5μm以下へと益々微細化して
いる。 リソグラフィ技術にはこうした素子微細化を牽引する役
割りがある。リソグラフィー技術では光・X線・電子線
等のエネルギー線を用いる。すなわちリソグラフィーは
これらエネルギー線を感光性材料であるレジスト材料に
選択的に照射することによりレジスト内に潜像を形成し
、この後現像工程によりこれら潜像を実像とすることに
よって下地材料を加工するレジストマスクを形成するの
が通常である。 従ってこれに使用されるレジスト材料には、■高解像性
、 ■高感度、 ■高加工耐性。 の性能が要求される。ところが今までの一般のレジスト
材料にはこれら3要素を同時に高いレベルで満足するも
のがなく、用途に応じてレジスト材料を選択せざるをえ
ず、いずれかを犠牲にしていた。しかしながら最近2例
えばジャーナル オブバキューム サイエンス アンド
 テクノロジー (J、 Vac、 Sci、 Tec
hnol、)  B6(1)、 Jan/Feb ’8
8ρp319−322.や、同誌同号pP379−31
13に示されるような触媒の増感反応を利用した化学増
幅系レジストが考案された。 これはエネルギー線の照射によって触媒となる中間物質
が生成され、その後の加熱処理でレジスト反応を効率的
に促進するという、新しい機構を有するレジスト材料で
ある。この結果、従来レジストの高解像度・高加工耐性
は保ったまま、高い感度を実現することができる。これ
はリソグラフィーにとって理想的なレジスト材料である
。また将来的にもこうした化学増幅系レジストはレジス
ト材料の主流としての位置付けがなされている。
The integration and density of ULSI is increasing fourfold in three years, and mass production of 4 megabit dRAM and prototype production of 16 megabit dRAM are underway. Along with this, the dimensions required for microfabrication have increased from 0.8 μm to 0.
.. 5 μm, countersunk is becoming increasingly finer than 0.5 μm. Lithography technology plays a role in driving this miniaturization of devices. Lithography technology uses energy beams such as light, X-rays, and electron beams. In other words, lithography forms latent images in the resist by selectively irradiating these energy rays onto a photosensitive resist material, and then processes the base material by converting these latent images into real images through a development process. Usually, a resist mask is formed. Therefore, the resist materials used for this have the following characteristics: ■High resolution, ■High sensitivity, and ■High processing resistance. performance is required. However, there is no conventional resist material that simultaneously satisfies these three elements at a high level, and resist materials must be selected depending on the application, at the expense of one or the other. However, recently 2 e.g. Journal of Vacuum Science and Technology (J, Vac, Sci, Tec
hnol, ) B6 (1), Jan/Feb '8
8ρp319-322. , the same issue of the same magazine, pP379-31
A chemically amplified resist using a catalytic sensitization reaction as shown in No. 13 has been devised. This is a resist material with a new mechanism in which an intermediate substance that serves as a catalyst is generated by irradiation with energy rays, and the subsequent heat treatment efficiently promotes the resist reaction. As a result, high sensitivity can be achieved while maintaining the high resolution and high processing resistance of conventional resists. This is an ideal resist material for lithography. Moreover, such chemically amplified resists are positioned as mainstream resist materials in the future as well.

【発明が解決しようとする課M】[Problem M that the invention attempts to solve]

ところが上記化学増幅系レジスト材料をULSI等の製
造工程に用いたところ大量枚数のウェハ間で図形寸法の
変動(細り)が生じ、安定で制御性の高いリソグラフィ
ープロセスが実現できないことが判明した。以下第2図
(a)により上記現象を詳細に説明する。 一般にn枚のウェハを格納したカセット2のウェハ#1
が図形露光部15に搬送される1次にウェハ#1上に塗
布されたレジストに所定の図形が露光処理される。この
後ウェハ#lは再びカセット2に搬送・格納される0次
にウェハ#2が選択され上記ウェハ#1と同様に一連の
処理がなされる。これを繰返しウェハ#nまでの全ての
処理が完了することにより1バッチ単位の露光処理が終
了する。この後これらウェハ#1〜#nは第2図(b)
に示す様に露光後ベーク・現像処理を経てレジストパタ
ーンが形成される。ところがこのシーケンスにおいてウ
ェハ#1とウェハ#nとの間で大幅なパターン寸法変化
が生じた。 第3図は各ウェハに露光した微細パターンの寸法設計値
からのズレ量を示したものである。図示したようにウェ
ハ間でパターン寸法に大きな違いがあることを見い出し
た。このことは露光後からベーク処理までの時間がウェ
ハ#1〜#nで必然的に異なることに起因しており、露
光によってレジスト内に発生した触媒に経時変化が生じ
るものと考えられる。化学増幅系レジストは感度・解像
度などの点で極めて高い性能を同時に実現できる理想的
なレジストであるが、上記現象により安定性・再現性を
問われるULSIH造工程には適用できないという問題
が生じた。 本発明は上記現象を踏まえ、上記化学増幅系レジスト材
料の不安定性を取り除き、安定性・再現性の高いULS
I製造工程を実現することを目的とする。
However, when the above-mentioned chemically amplified resist material was used in a manufacturing process such as ULSI, it was found that variations in feature dimensions (thinning) occurred among a large number of wafers, making it impossible to realize a stable and highly controllable lithography process. The above phenomenon will be explained in detail below with reference to FIG. 2(a). Generally, wafer #1 of cassette 2 containing n wafers
The resist coated on the primary wafer #1 is transported to the pattern exposure section 15, and a predetermined pattern is exposed to light. Thereafter, wafer #1 is again transferred and stored in cassette 2. Wafer #2 is selected as the 0th wafer and undergoes a series of processing in the same manner as wafer #1. By repeating this process and completing all the processes up to wafer #n, the exposure process for one batch is completed. After this, these wafers #1 to #n are shown in FIG. 2(b).
As shown in FIG. 3, a resist pattern is formed through a post-exposure bake and development process. However, in this sequence, a significant pattern dimension change occurred between wafer #1 and wafer #n. FIG. 3 shows the amount of deviation from the dimension design value of the fine pattern exposed on each wafer. As shown in the figure, we found that there were large differences in pattern dimensions between wafers. This is due to the fact that the time from exposure to baking is necessarily different for wafers #1 to #n, and it is thought that the catalyst generated in the resist due to exposure changes over time. Chemically amplified resists are ideal resists that can simultaneously achieve extremely high performance in terms of sensitivity and resolution, but due to the above phenomenon, a problem has arisen that they cannot be applied to the ULSIH fabrication process, which requires stability and reproducibility. . Based on the above phenomenon, the present invention eliminates the instability of the chemically amplified resist material and provides ULS with high stability and reproducibility.
The purpose is to realize the I manufacturing process.

【課題を解決するための手段1 上記目的は露光装置内あるいはその周辺にベーク装置を
配し上記レジスト材料の露光後からベーク処理までを各
試料毎に連続処理しこの間の経時変化を露光試料毎に全
て一定時間にすることにより達成される。 【作用】 第1図(a)に示すように露光装置1の内部、あるいは
同図(b)に示すようにその周辺にベーク装置4を設け
ることにより露光後の各ウェハはベークまでの時間を全
て同一とすることができる。すなわち、第1図(c)に
示すように露光とベーク処理とをウェハ毎に一貫して処
理することによりレジスト内の触媒の経時変化をウェハ
毎に一定にすればウェハ間のパターン寸法変動を解消し
安定性・再現性の高い化学増幅系レジスト利用のプロセ
スを実現できる。さらに露光後ベークを行なうまでの経
過時間を短くでき感度・解像度の高いパターニングが可
能となり、上記レジストの高い性能を引き出せることに
もなる。
[Means for Solving the Problem 1] The above purpose is to arrange a baking device in or around the exposure device, to continuously process each sample from the exposure of the resist material to the baking process, and to measure changes over time for each exposed sample during this period. This is achieved by keeping all of the time constant. [Operation] By providing the baking device 4 inside the exposure device 1 as shown in FIG. 1(a) or around it as shown in FIG. 1(b), each wafer after exposure is They can all be the same. In other words, if exposure and baking are performed consistently on each wafer, as shown in Figure 1(c), and the change in the catalyst in the resist over time is made constant for each wafer, pattern size variations between wafers can be reduced. This makes it possible to realize a process using a chemically amplified resist with high stability and reproducibility. Furthermore, the elapsed time before baking after exposure can be shortened, making it possible to perform patterning with high sensitivity and resolution, thereby bringing out the high performance of the resist.

【実施例】【Example】

以下1本発明を実施例を用いて詳細に説明する。 〈実施例1〉 実施例1は電子線露光装置の露光室と交換室との間にホ
ットプレートベーク機能を設けた例である。 第4図に該電子線露光装置の概要を示す、該電子線露光
装置は加速電圧30kVの可変成形ビーム型露光装置で
ある。露光試料は4インチSi基板上にネガ型化学増幅
系レジスト材料5AL601−ER7(シソプレイ・マ
イクロエレクトロニクス社)を0.5μm膜厚で塗膜形
成した。露光子定の1バッチ10枚全ての試料は第4図
に示す試料待機室に設置され、1枚ずつ交換室に搬送さ
れる。 該交換室を〜1μT orr以下の露光室と同程度の高
真空状態にした後、露光ステージへ搬送・固定し、照射
量8μC/cm”で所定の微細パターンを露光し、その
潜像を形成した。露光済みの該1枚目の試料は次にベー
ク装置に搬送され110℃で2分間ベーク処理を行なっ
た。この後該試料を待機室の所定の場所に格納した。2
枚目以降1枚目と同様の手順で処理を行ない、露光子定
の10枚金石の該試料の処理を終了させた。次いで。 現像液MF312(シソプレイ・マイクロエレクトロニ
クス社)にて現像することによりパターン形成した。こ
のレジストパターンの寸法の評価を走査型電子顕微鏡5
6000(日立)を用いて行なったところウェハ間寸法
バラツキで0.02μm710枚の良好な値を得ること
ができた。 (実施例2〉 実施例2は電子線露光装置の露光室と試料特機部との間
にベルト加熱式ベーク機能を設けた場合である。該ベー
タ装置温度を110℃としベルト送り速度を0.15c
m/seaとしたベーク処理により実施例1と同様の結
果を得た。 (実施例3〉 実施例3は波長248nmのK r Fエキシマレーザ
光による光学式露光装置の露光部と試料特機部との間に
赤外線加熱ベーク機能を設けた。該ベーク装置を用いて
10分間ベーク処理を行なったところ、この場合も実施
例1と同様のレジスト特性の経時変化抑制の改善効果を
認めた。 【発明の効果] 本発明によれば、高感度・高解像度・高ドライエツチン
グ耐性を有する化学増幅系レジスト材料固有の触媒の経
時変化現象に起因するウェハ間パターン寸法変動を回避
することができる。このため今後益々高集積化するUL
SI等の半導体素子や超微細デバイスの製造を強力に推
進するものとなる。
The present invention will be explained in detail below using examples. Embodiment 1 Embodiment 1 is an example in which a hot plate baking function is provided between an exposure chamber and an exchange chamber of an electron beam exposure apparatus. FIG. 4 shows an outline of the electron beam exposure apparatus, which is a variable shaped beam type exposure apparatus with an accelerating voltage of 30 kV. For the exposure sample, a negative chemical amplification resist material 5AL601-ER7 (Sisoplay Microelectronics Co., Ltd.) was coated with a thickness of 0.5 μm on a 4-inch Si substrate. All 10 samples in one batch of exposure light are placed in the sample waiting room shown in FIG. 4, and transported one by one to the exchange room. After bringing the exchange chamber to a high vacuum state of ~1 μT orr or less, comparable to that of the exposure chamber, it was transported and fixed to the exposure stage, and a predetermined fine pattern was exposed at a dose of 8 μC/cm, forming a latent image. The exposed first sample was then transferred to a baking device and baked at 110°C for 2 minutes.After this, the sample was stored in a predetermined location in the waiting room.2.
After the first sheet, processing was carried out in the same manner as for the first sheet, and the processing of the 10-sheet goldstone sample with fixed exposure rate was completed. Next. A pattern was formed by developing with developer MF312 (Sisoplay Microelectronics). The dimensions of this resist pattern were evaluated using a scanning electron microscope.
6000 (Hitachi), it was possible to obtain a good value of 0.02 μm for 710 wafers with dimensional variation between wafers. (Example 2) Example 2 is a case in which a belt heating type baking function is provided between the exposure chamber and the sample special equipment section of an electron beam exposure device.The temperature of the beta device is 110°C and the belt feeding speed is 0. .15c
The same results as in Example 1 were obtained by baking at m/sea. (Example 3) In Example 3, an infrared heating baking function was provided between the exposure section of the optical exposure device using KrF excimer laser light with a wavelength of 248 nm and the sample special equipment section. When the baking process was performed for 1 minute, the same improvement effect of suppressing changes in resist properties over time as in Example 1 was observed in this case as well. [Effects of the Invention] According to the present invention, high sensitivity, high resolution, and high dry etching It is possible to avoid wafer-to-wafer pattern size variations caused by the aging phenomenon of the catalyst inherent in chemically amplified resist materials, which have high resistance.This makes it possible to avoid wafer-to-wafer pattern size variations, which are expected to become increasingly highly integrated in the future
This will strongly promote the production of semiconductor elements such as SI and ultrafine devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は本発明の実施例の露光装置の概略側断面
図、第1図(b)は露光周辺部にベーク機能を設けた実
施例を示す概略側断面図、第1図(c)は本発明を用い
た場合のレジストプロセスフローを説明する図、第2図
(a)は露光部と試料特機部からなる従来の露光装置の
概略側断面図、第2図(b)は従来の露光装置を用いた
場合のレジストプロセスフローを示す図、第3図は従来
例において各ウェハに露光した微細パターンの寸法設計
値からのズレ量を示す図、第4図は露光室と試料交換室
との間にホットプレートベーク機能を設けた電子線露光
装置の概略側断面図である。 符号の説明 2・・・カセット、3・・・試料(ウェハ)、4・・・
ベーク装置、5・・・ステージ、6・・・光源、7・・
・電子線露光部。 8・・・試料特機部、9・・・ホットプレート、10・
・・バルブ、11・・・電子銃、15・・・図形露光部
遁 2 日 (す 妬 ( 口(り 葉 ■ (b) 121−
FIG. 1(a) is a schematic side sectional view of an exposure apparatus according to an embodiment of the present invention, FIG. c) is a diagram explaining the resist process flow when using the present invention, FIG. 2(a) is a schematic side sectional view of a conventional exposure apparatus consisting of an exposure section and a sample special section, and FIG. 2(b) Figure 3 shows the resist process flow when using a conventional exposure device, Figure 3 shows the amount of deviation from the dimensional design value of the fine pattern exposed on each wafer in the conventional example, and Figure 4 shows the exposure chamber and FIG. 2 is a schematic side sectional view of an electron beam exposure apparatus provided with a hot plate baking function between it and a sample exchange chamber. Explanation of symbols 2...Cassette, 3...Sample (wafer), 4...
Baking device, 5... stage, 6... light source, 7...
・Electron beam exposure section. 8... Sample special equipment section, 9... Hot plate, 10.
...bulb, 11...electron gun, 15...figure exposure section 2 days

Claims (1)

【特許請求の範囲】 1、電子線あるいはX線もしくは光を用いて所望の図形
を感放射線性材料が被着された基板上に形成する図形露
光装置において、該基板を露光中若しくは露光後連続し
てベーク処理するためのベーク装置を有する図形露光装
置。 2、基板上に塗布した感放射線材料膜に、電子線あるい
はX線もしくは光を用いて所望の図形を形成する図形露
光方法において、該基板を露光中もしくは露光後、連続
してベーク処理する工程を含み、複数の基板間での露光
工程からベーク工程までの経過時間を均等化したことを
特徴とする図形露光方法。 3、上記ベーク処理部がホットプレート式またはベルト
加熱式または熱風循環式または赤外線・遠赤外線式また
は高周波加熱方式であることを特徴とする請求項1記載
の図形露光装置。 4、上記ベーク処理温度が、80〜140℃であること
を特徴とする請求項2記載の図形露光方法。 5、上記感放射線性材料として化学増幅系レジストを用
いることを特徴とする請求項2記載の図形露光方法。 6、上記基板をウェハ若しくはマスク若しくはレチクル
とすることを特徴とする請求項2記載の図形露光方法。
[Scope of Claims] 1. In a pattern exposure device that uses electron beams, X-rays, or light to form desired patterns on a substrate coated with a radiation-sensitive material, the substrate is continuously exposed during or after exposure. A pattern exposure apparatus having a baking device for baking. 2. In a pattern exposure method in which a desired pattern is formed on a radiation-sensitive material film coated on a substrate using electron beams, X-rays, or light, the step of continuously baking the substrate during or after exposure. A pattern exposure method characterized by equalizing the elapsed time from the exposure step to the baking step among a plurality of substrates. 3. The graphic exposure apparatus according to claim 1, wherein the baking section is of a hot plate type, a belt heating type, a hot air circulation type, an infrared/far infrared type, or a high frequency heating type. 4. The graphic exposure method according to claim 2, wherein the baking temperature is 80 to 140°C. 5. The pattern exposure method according to claim 2, wherein a chemically amplified resist is used as the radiation-sensitive material. 6. The pattern exposure method according to claim 2, wherein the substrate is a wafer, a mask, or a reticle.
JP1292332A 1989-11-13 1989-11-13 Figure exposure apparatus and method Expired - Lifetime JP3020523B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1292332A JP3020523B2 (en) 1989-11-13 1989-11-13 Figure exposure apparatus and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1292332A JP3020523B2 (en) 1989-11-13 1989-11-13 Figure exposure apparatus and method

Publications (2)

Publication Number Publication Date
JPH03154324A true JPH03154324A (en) 1991-07-02
JP3020523B2 JP3020523B2 (en) 2000-03-15

Family

ID=17780422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1292332A Expired - Lifetime JP3020523B2 (en) 1989-11-13 1989-11-13 Figure exposure apparatus and method

Country Status (1)

Country Link
JP (1) JP3020523B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297096A (en) * 1994-04-22 1995-11-10 Nec Corp Exposure method and device
US6518548B2 (en) 1997-04-02 2003-02-11 Hitachi, Ltd. Substrate temperature control system and method for controlling temperature of substrate
JP2008098635A (en) * 2006-10-12 2008-04-24 Asml Netherlands Bv Lithographic equipment, combination of lithographic equipment and processing module, and device manufacturing method
JP2008147315A (en) * 2006-12-07 2008-06-26 Canon Inc Exposure device, exposure/development system, and method of manufacturing device
JP2009044131A (en) * 2007-06-06 2009-02-26 Asml Netherlands Bv Integrated post-exposure bake track
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