JPH03154288A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To detect the lowering of the operation margin of a memory cell with a simple test by providing a bit line pair, a sense amplifier an input/output data line pair, a transfer gate pair, and a control signal output means. CONSTITUTION:When the operation margin of the memory cell lowers, the minute potential difference which appears between a bit line pair 1, 1' become smaller than normal times, and the potential difference between the bit line pairs 1, 1' become lower than the normal value even after amplification by a sense amplifier 2. In such a case, a potential difference which is lower than the potential difference between the bit line pair 1, 1' are transmitted to an input/output data line pair 5, 5'. As a result, the possibility of the potential difference which cannot be pre-amplified being transmitted to the input/output data line pair 5, 5' becomes greater, so by the inspection of the normal/defective condition of an output data, the lowering of the operation margin of the memory cell is easily detected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to dynamic RAM (DRAM), for example.
The present invention relates to a semiconductor memory device that reads data by amplifying the potential difference between a pair of bit lines.

[Conventional technology]

FIG. 3 is a schematic circuit diagram showing the periphery of a bit line pair of a conventional DRAM. In the figure, 1° 1' is a bit line pair, and a memory cell (not shown) is connected to a bit line 1 via a selection transistor (not shown). One end of each bit line pair 1.1' is connected to the sense amplifier 2, and the other end is connected to the N-channel transfer gate pair 3, 3'.
is connected to one electrode of the

Sense amplifier 2 is activated or deactivated by sense up activation signal S2, and when activated, bit line pair 1.1
Detect and amplify the potential difference between

A control signal S4 outputted from the control signal output means 4 is applied to both gates of the transfer gate pair 3.3'. The control signal output means 4 selectively outputs a control signal S4 of H level (power supply V level) or L level (ground C level) based on the external human input signal SO.

Further, the input/output data line pair 5.5' is connected to the other electrode of the transfer gate pair 3, 3'.

The input/output data line pair 5, 5' is used to take in input data from the outside and to output output data to the outside.

FIG. 4 is a waveform diagram showing a conventional DRAM operation test situation. The operation test will be explained below with reference to the same figure. First, a predetermined word line WL (not shown) is raised to an H level, and a selection transistor (not shown) inserted between a memory cell (not shown) and the bit line 1 is turned on.
The memory cell and pit line 1, which has already been precharged to 1/2v level, are electrically connected. Then, based on the data stored in the memory cells, a minute potential difference is generated between the bit line pair 1°1'.

Then, the sense amplifier activation signal S2 is raised to H level, and the sense amplifier 2 is activated. Then bit line pair 1
, 1' is amplified.

Next, by applying a predetermined external input signal SO to the control signal generating means 4, the control signal S4 is raised to an H level,
Transfer gate pair 3.3' is turned on. Then,
without reducing the potential difference between bit line pair 1 and 1'.
It appears as it is on the input/output data line pair 5, 5'. The potential difference between the input/output data line pair 5.5' is amplified by a preamplifier (not shown) and output as output data. By verifying the quality of this output data, an operation test of the DRAM is performed.

[Problem to be solved by the invention]

The conventional DRAM is configured as described above, and the electrical connection between the bit line pair 1.1' and the input/output data line pair 5.5' is connected to the gate of the N-channel transfer gate pair 3.3'. Since control of the power supply V level is performed by applying the C signal S4, the potential difference between the bit line pair 1.1' does not become small and appears on the input/output data line pair 5, 5'.

On the other hand, the operating margin of the memory cell may be affected, such as when the capacity of the memory cell becomes smaller than the reference value, or when the threshold voltage of the selection transistor inserted between the memory cell and the bit line pair 1.1' becomes higher than the reference value. When a drop occurs, the minute potential difference that appears between the bit line pair 1.1' becomes smaller than in the normal state. As a result, even after being amplified by the sense amplifier 2, the potential difference between the bit line pair 1 and 1' falls below the normal value.

However, even if the potential difference between bit line pair 1.1' falls below the normal value, transmission between bit line pair 1, 1' and input/output data line pair 5.5' is carried out without deterioration, so A potential difference that can be amplified by the preamplifier is transmitted to the line pair 5, 5'. That is, there is a problem in that it is difficult to detect a slight decrease in the operating margin of the memory cell by the above-mentioned operation test.

Therefore, in order to detect even the decrease in the operating margin of a memory cell as described above, there has been a problem in that a long-cycle complex test must be performed over a long period of time.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that can detect a decrease in the operating margin of a memory cell by a simple test.

[Means to solve the problem]

A semiconductor memory device according to the present invention includes: a bit line pair in which a memory cell is connected to at least one of the bit lines; a sense amplifier connected to the bit line pair and amplifying a potential difference between the bit line pair in an active state; an input/output data line pair for exchanging input/output data with the outside; a transfer gate pair inserted between the bit line pair and the input/output data line pair; Control signal output means is provided for both generators to apply a voltage between the threshold voltage of the transfer gate pair and the voltage for turning on the transfer gate pair during normal operation.

[Effect]

The control signal output means in the present invention applies a voltage between the threshold voltage of the transfer gate pair and the voltage for turning on the transfer gate pair in normal operation to both gates of the transfer gate pair based on an external input signal. In order to output an output, the transfer gate pair can be turned on with a lower transfer capability than during normal operation.

〔Example〕

FIG. 1 is a schematic circuit diagram showing the periphery of a bit line pair of a DRAM according to an embodiment of the present invention. The control signal output means 4' in the same figure differs from the conventional one in that the control signal output means 4' is at H level (power supply V
In addition to the L level (ground level), there is an intermediate level voltage C of about 1/2V that is higher than the threshold voltage of the N-channel C transfer gate pair 3.3' and lower than the power supply V level. The control signal S4' is selectively output based on the external input signal SO'. Note that the other configurations are the same as those of the prior art, so explanations will be omitted.

FIG. 2 is a waveform diagram showing the operational test status of the DRAM shown in FIG. The operation test will be explained below with reference to the same figure. First, a predetermined word line WL (not shown)
is raised to H level, and a selection transistor (not shown) inserted between a memory cell (not shown) and bit line 1 is turned on, and the memory cell and bit line 1, which has already been precharged to 1/2V level, are connected. Connect electrically. Then, based on the data stored in the memory cells, bit line pair 1.1
′ A minute potential difference occurs between the two.

Then, the sense amplifier activation signal S2 is raised to H level, and the sense amplifier 2 is activated. Then bit line pair 1
．． 1' is amplified.

Next, by applying the external input signal SO' to the control signal output means 4', the control signal S4' is raised to the intermediate level H', and the transfer gate pair 3.3' is turned on.

Since the intermediate level H' is, for example, the 1/2v level,
The transfer gate pair C3, 3' is not strongly turned on, and its transfer ability is limited by the control signal S.
4' is V. . Compared to the case where it is at the same level, it deteriorates considerably. Therefore, the potential difference between bit line pair 1 and 1' becomes smaller and appears on input/output data line pair 5 and 5'.

The potential difference between the input/output data line pair 5.5' is amplified by a preamplifier (not shown) and output as output data. By verifying the quality of this output data, D
A RAM operation test is performed.

When the operating margin of memory cells decreases, bit line pair 1
．． The minute potential difference that appears between bit lines 1' and 1' becomes smaller than normal, and even after being amplified by sense amplifier 2, the potential difference between bit line pair 1 and 1' remains below the normal value. In this case, when the above-described DRAM operation test is performed, a potential difference that is even lower than the potential difference between the bit line pair 1 and 1' is transmitted to the input/output data line pair 5.5'.

As a result, if the operational merge of the memory cell decreases, there is a high possibility that a potential difference that cannot be amplified by the preamplifier will be transmitted to the input/output data line pair 5, 5'.
By verifying the quality of the output data, it is possible to detect i below the operating margin of the memory cell. Therefore, in order to detect a decrease in the operating margin of a memory cell,
There is no longer a need to conduct complex long-cycle tests as required in the past.

The on/off of the transfer gate pair 3 and 3' when performing normal read and write operations is based on the external input signal SO', and is output from the control signal output means 4' to the H level (power supply V level)/L level. This is done by outputting a control signal S4' of level C (ground level).

Further, by the operation test in this embodiment, it is possible to detect not only the above-mentioned decrease in the operating margin of the memory cell, but also insufficient capacity of the sense amplifier 2, insufficient capacity of the preamplifier, and the like.

〔Effect of the invention〕

As described above, according to the present invention, the control signal output means applies a threshold voltage of the transfer gate pair and a voltage for turning on the transfer gate pair during normal operation to both gates of the transfer gate pair based on an external input signal. Since it outputs a voltage between 1 and 2, it is possible to turn on the transfer gate pair with a lower transfer capability than during normal operation.

Therefore, since the potential difference between the bit line pair can be reduced and generated between the input/output data line pair, operation tests using the potential difference between the input/output data line pair as verification data can be performed under severe conditions. Become.

As a result, a reduction in the operating margin of a memory cell, such as an insufficient memory capacity of the memory cell, can be detected by a simple test.

[Brief explanation of the drawing]

Fig. 1 is a schematic circuit diagram showing a DRAM which is an embodiment of the present invention, Fig. 2 is a waveform diagram showing an operation test of the DRAM shown in Fig. 1, and Fig. 3 shows a conventional DRAM. The schematic circuit diagram, FIG. 4, is a waveform diagram showing an operation test of the DRAM shown in FIG. In the figure, 1.1' is a bit line pair, 2 is a sense amplifier, 3.3' is a transfer gate pair, 4' is a control signal output means, and 5, 5' is an input/output data line pair. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure Figure 1.1: Bit line pair 5.5: Input/output data line pair

Claims (1)

[Claims] (1) A bit line pair with a memory cell connected to at least one bit line, a sense amplifier connected to the bit line pair and amplifying the potential difference between the bit line pair when in an active state, and a sense amplifier that connects external and input/output data. an input/output data line pair for transmitting and receiving; a transfer gate pair interposed between the bit line pair and the input/output data line pair; A semiconductor memory device comprising control signal output means for applying a voltage between a threshold voltage of a gate pair and a voltage for turning on the transfer gate pair during normal operation.