JPH03149672A - Ic for image processing space filter - Google Patents

Abstract

PURPOSE:To make it possible to constitute two kinds of different space filters only by one IC when the number of bits is small and constitute one space filter by the same IC when the number of bits is large by forming two-channel constitution obtained by connecting a product sum computing part, the 1st delay circuit and the 1st extended adder is series. CONSTITUTION:The IC is provided with the two-channel constitution consisting of the 1st processing block connecting the 1st product sum computing part 2, the 1st delay circuit 3 and the 1st extended adder 4 in series and the 2nd processing block connecting the 2nd product sum computing part 5, the 2nd delay circuit 6 and the 2nd extended adder 7 in series. Input terminals 8 to 10 are used in common by both the blocks and extended input terminals 11, 14 and output terminals 12, 13 are independently used by respective blocks. Thus, the IC can be used in accordance with the number of bits corresponding to circuit size, and in the case of using the IC by a coefficient consisting of the small number of bits, the idle part of the circuit can be effectively utilized for two circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC for image processing spatial filters.

[Prior Art] In the electronic processing of two-dimensional image information, spatial filtering of images is usually performed using a 3×3 mesh window, that is, a vertical
This is executed by multiplying and accumulating a coefficient matrix of rows and three horizontal columns and the image information to be processed. In other words, the coefficient matrix C is (:°.

If Cli" OCll Cl2 - (1), the processed point of interest image is a,..., and the processed point of interest image is..., then bw, y"Coo-ax-*, y-l"Co1°
ax, y-l”CO2°ag+1.y-1”Cl(1
”am-l,y ”CIl”am,y ”CI
2"am+l y"C20"am-l, 7+1"c2
1 “am, y+I”c22°a11+1,yll.

The configuration of a conventional image processing spatial filter IC is schematically shown in FIG.
C20G1, a product-sum calculation unit 21 that performs the product-sum calculation of the above-mentioned formula (2), and N-bit image data a*-+, y, respectively;
-r ~ a x+t, y*I are manually inputted in parallel through three input terminals 24, 25, 26, a delay circuit 22 that provides a predetermined delay to the output from the product-sum operation section 21, and an extended input terminal 27. and an adder 2 that adds the output of the delay circuit 22 and the extension data input manually to the - extension input terminal 27.
3 and an output terminal 28 for taking out the outputs of the adder 23h1 and the like, and the product-sum operation section 21 has a configuration as shown in the block diagram of FIG.

That is, when N-bit image data is input from the input terminals 24, 25, 26 in FIG. 2, the image data passes through the terminals 61, 62, 63 in FIG. ~38 and their outputs are multiplied in multipliers 50-58 with nine coefficients C0°-C22 of M bits whose maximum number of bits is given below by nine coefficient registers 40-48. The outputs of each multiplier are added in an adder 60, and the final product sum output is sent to a terminal 6.
4 to N+M+4 bit data. This output passes through the delay circuit 22 shown in FIG.
The extended adder 23 adds the N+M+4-bit data manually inputted from 7 and outputs it from the output terminal 28 as N+M+5-bit data. The expansion adder 23 is used when a plurality of ICs are connected in parallel to perform expanded operation. There are three types of expansion operations: processing of 2N-bit image data, expansion of coefficients to 2M (>K) bits, and expansion to a 6-by-6 spatial filter by using four ICs in parallel. Further, the delay circuit 22 is used to adjust the timing of this expansion operation.

[Problem to be solved by the invention] The configuration of the conventional image processing spatial filter IC as described above (
In this case, the maximum number of bits of the coefficient register for coefficients C0° to C22 is fixed. This number of bits is designed to match the case with the largest number of bits among the expected applications. The circuit scale of C for the spatial filter is proportional to the sum N0M of the number N of bits of image data and the number M of bits of coefficients.

In image processing applications, the number of coefficient bits is often 2 to 3 bits, but in conventional spatial filter ICs, the maximum number of bits K in the coefficient register is set to 8 to expand the range of applications.
Generally, it is on the order of bits, and such I
When C is used for image processing where a 2- to 3-bit coefficient is sufficient, there is a waste in terms of circuit scale.

The present invention was made in view of these conventional problems, and it is possible not only to use the number of bits according to the circuit scale, but also to effectively utilize idle parts of the circuit when using coefficients with a small number of bits. Image processing spatial filter IC
The purpose is to provide the following.

[Means for Solving the Problems] In order to achieve the above-mentioned problems, the image processing spatial filter IC of the present invention includes a first product-sum operation section, a first delay circuit, and a first expansion adder. It has a two-channel configuration consisting of a first processing block in which are connected in cascade, and a second processing block in which a second product-sum operation section, a second delay circuit, and a second expansion adder are connected in cascade, It has a common data input terminal commonly connected to the first and second product-sum operation sections, an expansion input terminal for each channel, and an output terminal for each channel.

[Function] The function of the spatial filter IC of the present invention having the above-described configuration will be described below with reference to FIGS. 1 and 4 corresponding to the embodiment.

As shown in FIG. 1, the image processing spatial filter IC of the present invention performs first processing in which a first product-sum operation section 2, a first delay circuit 3, and a first expansion adder 4 are connected in cascade. It has a two-channel configuration consisting of a second processing block in which a second product-sum calculation unit 5, a second delay circuit 6, and a second expansion adder 7 are connected in cascade, and an input terminal 8. ，
9.10 is common to both blocks, expansion input terminal 11.14
and output terminals 12 and 13 are independent for each block.

The product-sum calculation section 2.5 in FIG. 1 basically has the same configuration as that shown in FIG. 3. However, the maximum number of bits of each coefficient register is set to M/2 when the maximum number of bits of a coefficient of a predicted application is M. For example, if the maximum number of coefficients in the predicted application is 8 bits,
The bit configuration of the coefficient register of each product-sum operation unit 2.5 is 4 bits, so that one channel can be used for coefficients of 5 to 8 bits, and 2 can be used for coefficients of 1 to 4 bits.
The channel can be used for any purpose.

When M is an odd number, the coefficient register of one product-sum calculation section has a bit number of (M+1)/2, and the coefficient register of the other product-sum calculation section has a bit number of (M-1)/2.

Also, when a coefficient takes a positive or negative value, conventionally, 1 bit was assigned to the sign bit and M-1 bits were assigned to the absolute value.
In the present invention, when M-1 is an even number, both product-sum calculation units 2 and 5 have 1 bit for the sign bit and (M-1)7 for the absolute value.
2 bits are assigned, and if M-1 is an odd number, one of the product-sum calculation units 2 and 5 is assigned a sign 1 bit and an absolute value M/2 bit, and the other is assigned a sign 1 bit and an absolute value CM-2)/2. bits will be allocated.

The following explanation will be given for the case where the coefficient registers of the product-sum calculation units 2 and 5 each have M72 bits, but the same applies to other cases.

The number of bits of input image data is N, and the number of coefficient bits is M/2.
Then, the output of the product-sum calculation section 2.5 in FIG. 1 is N+M/
2+4 bits, and this output passes through delay circuits 3 and 6 and is N+M/2+4 input from expansion input terminal 11.14.
After being added to the bit extension data in the extension adder 4.7, the data is output from the output terminal 12.13 as N+M/2+5 bit data.

In this way, the present invention has two channels of processing blocks for product-sum calculations and is configured to operate independently.
The number of bits in the coefficient register of the product-sum operation section of each channel is designed to be half the maximum number of bits of the coefficient in the predicted application. Therefore, in applications with a small number of bits below M72, Processing can be performed using only one channel, and the coefficients of the product-sum operation section of the other channel can be independently changed to different coefficient values and used for other processing.

This is effective, for example, when simultaneously processing the vertical differential of an image on one channel and the horizontal differential on the other channel.

If the number of bits of the coefficient is greater than M/2, the upper N+5 bits of the output terminal 12 are connected to the lower N+5 bits of the expansion input terminal 14, as shown by the broken line in FIG. In this case, the lower M72 bits of the coefficient are set in the coefficient unit of one product-sum calculation unit 2, and the remaining bits after removing the lower M72 bits from the coefficient are set in the coefficient unit of the other product-sum calculation unit 5. set.

Dividing the coefficient CiJ into the upper M 2 bits elj and the lower M 72 bits dlJ, we get Ct4: 2"2X e lJ + d Ij- (3)
becomes. The calculation result is ×(2″/2 e, j4 dth), where, b x, y ” 2 ””, A x, 31 ”
BX, F ・-(7). This AM
, y are the outputs of one product-sum calculation unit 5, and B, , , are the outputs of the other product-sum calculation unit 2.

Here, the upper N+5 bits of B, , are E 11, F
%If the lower N+5 bits are F, , then bx, ,
= 2”” Ax, + 2” EM, 1 + F)
1.11=2”(A x, y + E x, y) + F
x, y...(8).

80, +Ex, is the output OUT2 generated at the output terminal 13 in Fig. 1, and F and I5y are the output terminals 12 in Fig. 4.
&: It is taken from the resulting output OUTI, so the output O
F x, y of UTl, lower M/2 bits, output OUT2
A M, F −+ E ) 1.2 to upper N+M/2
+5 bits, and the combined N+M+5 bits are the final output b8. ．． becomes. Note that 0 is manually input to the expansion input terminal 11 in FIG. 1, and the timing is adjusted by adjusting the delay circuit 3.6.

Therefore, with the configuration shown in FIG. 1, a spatial filter IC can be used that can perform product-sum calculations of M-bit coefficients as in the past, and can also be applied to product-sum calculations of M/2-bit independent two-channels.
It turns out that it can be achieved.

An uninvented embodiment will be described below with reference to the drawings.

[Embodiment] FIG. 1 shows a first embodiment of the present invention, in which N-bit image data of each of three adjacent pixels is manually inputted from three input terminals 8, 9, and 10. When two-dimensional image data is given in the form of a raster scan, input terminal 9 receives, for example, image data delayed from input terminal 8 by an amount of - as shown in FIG. further inputs image data delayed by a certain amount through another similar FIFO 16.

The product-sum calculation units 2.5 in FIG. 1 each have a structure as shown in FIG. 3. Image data applied to input terminals 8, 9.10 enters from terminals 61, 62.63 in FIG. 3 and is stored in each D-flip-flop 30-38. The image data stored here is expressed as a,
−l ~a x+1. This is 9 data of go1.

Multipliers 50-58 calculate the products of these data and M/2-bit coefficients C22-C0° stored in coefficient registers 40-48 in FIG. The sum of the products is calculated by the adder 60 and outputted from the terminal 64 as a product-sum operation result of N+M/2+4 bits.

The product-sum output from each product-sum calculation unit 2.5 passes through a delay circuit 3.6 in FIG. 1 and is inputted to an extended adder 4.7. When not performing extended addition, input “0” to the extended input terminals 11.14.
”, and when performing extended addition, enter the extended human power 1.
1. Input N+M/2+4 bit data into 14.

The output of each expansion adder is taken from a respective output terminal 12.13.

If the coefficients of the spatial filter for image processing need not exceed m72 bits, the two-channel calculations shown in FIG. 1 can be performed independently. For example, next to two-dimensional image data (
When calculating the differential in the row) direction and the differential in the vertical (column) direction, the coefficient matrix CiJ of the product-sum calculation section 2 is set as C"Ij=1 0 1 ・" (1), and the product-sum calculation section 5 coefficient matrix C”, C2*J=
It may be set as OOQ ・−(10).

When the coefficients are set in this way, the differential image data output OUT taken out from the output terminal 12 of one channel
1. ．． ．． is OUT 1 . I, y = a x + s, y - t +
ax+1. y+ a go1.1+1-(a ll
-@, F-l +a II-1,2+ a r-t,
y*t ) ”・(11), which is the differential image data in the X direction, and the differential image data output OUT2 taken out from the output terminal 13 of the other channel is OUT 2 m1.31 = a g-l , go1-
+ a 11.31111+ a go1. y+I
(a z-, y-1+a X, F-l + a
Xl)1. The differential image data in the y direction is F−l)”=(12).

If the coefficient of the spatial filter is insufficient at M/2 bits, as shown in FIG. The lower m72 bits of the coefficient of the spatial filter are set for the coefficient of No. 2, and the remaining bits are set for the coefficient of the other product-sum operation section 5. Further, "0" is input to the expansion input terminal 11.

In this case, for example, when N is 8 and M is 8, the binary representation of the coefficient 00° of the spatial filter is Coo=101
Assuming 01100 (8 bits) - (13),
Coefficient cl of product-sum calculation unit 2. . is C”oo =1100
(lower 4 bits) - (14), which is the coefficient C2° of the product-sum calculation unit 5. is C2°. =toto(upper 4 bits)·-(1!+). 8+8/2 for output terminal 12
An output of +5=17 bits appears, and this binary value B becomes B=
OOOOI Go t 0000 1 1 1
00 (16), then the upper 8+5=13 bits of B, ie, ooootootootoot, are manually input to the lower 13 bits of the 16-bit expansion input terminal 14. In other words, the expansion input terminal 14km is E=000
0000100100001...(17) is input.

If the 16-bit output A of the product-sum calculation unit 5 of the image data at the same position is A=0001 100000001 1 10, it is delayed by the number of locks necessary in the delay circuit 6 and expanded with the previous 16-bit E. Added by adder 7. Therefore, A+E=0001100100101111・-(19
) appears at terminal 13. By adding the lower 5 bits 11100 of B to the lower order of this output, a 21-bit operation result of 0001100100IC)111111100 is obtained.

Note that the calculation result of the spatial filter in the embodiment described above is N+M+5 bits, but if you want to match the number of bits of this output with the number of bits of input image data, you must discard the M+5 bits in the output. In this case, it is sufficient to add a circuit that extracts any consecutive N bits out of the N+M+5 bits of the output and an output terminal for the extracted data of the N bits.However, in this case, the significant upper bits An error will occur if this is not extracted, so it is necessary to issue an error flag in such cases.

Further, in the above-mentioned embodiment, the stage before the extended adder 7 performs N+M+4 bit operations, and the extended adder 4.7 performs N+M+5 bit operations. Therefore, it is wasteful to configure the entire IC with N+M+5 bits, and it is better to configure the stage before the extended adder with N+M+4 bits, and the stage after the extended adder with N+M+5 bits.In this case, the connection parts with different numbers of bits , the N+M+4 bits from the previous stage are directly connected to the lower N+M+4 bits of the extended adder's manual input (N+M+5 bits), and the N+M+5th bit of the expanded adder's manual input is the N+M
It is sufficient to continue with +4th bit.

[Effects of the Invention] As described above, according to the present invention, when the number of bits of the coefficients of the image processing spatial filter is small, two types of separate spatial filters can be configured with one IC. If the number is large, one type of spatial filter can be configured.

When using two separate conventional ICs to filter 2 channels of N-bit image data using M-bit coefficients, two ICs are required because the size of one IC is proportional to N+M. In this case, the scale is 2N+2M, but in the present invention, one IC has two blocks of scale N+M/2.
Since there are 3 pieces, the total size is 2N+M in the same case, which has the advantage that the size can be made smaller by M than in the past.

Also, when processing two channels with separate ICs,
If the input terminals and control circuit portions each require an ICk, and if the number of chips becomes two, there will be a problem in terms of space for mounting on a printed circuit board, but the present invention is advantageous because it can be configured with one chip.

Furthermore, if the IC of the present invention is used, when the coefficient is M/2 bits, a 6-by-6 spatial filter, which conventionally required four, can be realized with two ICs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a spatial filter IC according to the present invention;
FIG. 2 is a block diagram of a conventional spatial filter IC, FIG. 3 is a block diagram of a product-sum operation section, and FIG. 4 is a block diagram of an application example of the spatial filter IC according to the present invention. [Explanation of symbols of main parts] l... Spatial filter IC, 2, 5-... Product-sum calculation unit,
3.6...Slow circuit, 4. Fu...Extended adder, 8~
10... Input terminal, 11.14-... Extension input terminal,
12.13...Output terminal %30-38...D-flip-flop, 40-48...Coefficient register, 50-
58... Multiplier, 60... Adder, 61-63...
・Input terminal, 64...Output terminal, 15.16・-FI
FO memory, 1 FO... image data input terminal, 18.1
9...Output terminal. Agent: Patent Attorney Masatoshi Sato (r 112, Mi) ~” 1, 1.1, Shimi) 1

Claims (1)

[Claims] A first processing block in which a first product-sum calculation unit, a first delay circuit, and a first expansion adder are connected in cascade, and a second product-sum calculation unit, a second delay circuit, and a second extension. It has a two-channel configuration consisting of a second processing block connected in cascade with an adder, a common data input terminal commonly connected to the first and second product-sum operation sections, and an expansion input for each channel. An image processing spatial filter IC characterized by having a terminal and an output terminal for each channel.