JPH03148830A - Darlington transistor - Google Patents

Abstract

PURPOSE:To prevent a drive circuit from being broken due to the erroneous operation and erroneous turn-ON of the circuit by a method wherein the time of reverse recovery of a speed-up diode connected between the base and the emitter of the first-stage transistor is made longer. CONSTITUTION:A Darlington Tr with a reversed speed-up diode SUD 3 connected between a base and an emitter of a preceding-stage transistor Tr1 is brought into a reverse-biased state at the time of turn-OFF. At this time, a current flows from an emitter terminal 12 to a base terminal 11. When a base current is turned-ON, the SUD 3 is brought into a state of reverse recovery, the base current does not flow in the Tr1 until carriers in the SUD 3 are annihilated and a collector current from a terminal 13 to the terminal 12 does not flow. Accordingly, the longer the time of reverse recovery of the SUD 3 is made, the longer a turn-ON delay time becomes. Thereby, the erroneous operation and erroneous turn-ON of a drive circuit can be prevented from generating.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a Darlington transistor formed by sequentially connecting a plurality of transistors w11vt. [Prior Art] In a transistor, especially a power transistor, in order to prevent the drive circuit from malfunctioning due to dv/dt that occurs at turn-on, or from being destroyed due to erroneous turn-on due to noise, etc., the base of the transistor 21 is connected as shown in FIG.・A measure to delay the rise of the collector current by connecting the capacitor 22 between the emitters, that is, to delay the rise of the collector current 34 when the base current 33 flows through the transistor in the off state 11831 as shown in FIG. It has been attempted to lengthen the turn-on delay time 32. The well-known Darlington transistor used to increase the current amplification factor also has a capacitor 2 between the base of the front transistor 1 and the emitter of the rear transistor 2 for the same purpose, as shown in FIG.
It was done to connect 2. On the other hand, in the Darlington transistor, in order to shorten the turn-off time, as shown in Figure 1, a speed-up diode 3 is connected between the base and emitter of the preceding transistor 10, which serves to extract carriers from the base of the subsequent transistor 2. Connecting is done. Note that the resistor 4 connected between the base and emitter of the subsequent transistor 2 is for balancing the fine structure and suppressing reverse bias. [Problem to be solved by the invention] As mentioned above, the capacitor between the base and emitter, which is conventionally used as a countermeasure for dv/dtll1M and erroneous turn-on, is
A capacitor must be prepared separately, and its connection is time-consuming, resulting in an increase in costs. SUMMARY OF THE INVENTION An object of the present invention is to provide a low-cost Darlington transistor that delays the rise of collector current for dv/dt suppression and false turn-on countermeasures without requiring connection of a capacitor.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a speed up diode in which a speed up diode whose junction direction is opposite to the base emitter junction is connected between the base and emitter of at least the first stage transistor. It is assumed that the reverse recovery time of the up diode is amped so that it has a long reverse recovery time. (Function) When the Darlington transistor is off, the base and emitter are in a reverse bias state.In the Darlington transistor shown in FIG.
A current flows from the base terminal 11 to the base terminal 11 via a 4° resistor and a speed up diode (SUD) 3. When the base current is turned on from this state, the SUD 3 enters a reverse recovery state, and the base current does not flow into the transistor l until the carriers of the SUD disappear, and the collector current does not flow from the collector terminal 13 to the emitter terminal 12. , S
The longer the reverse recovery time (trr) of the UD, the longer the turn-on delay time (td). That is, by performing lifetime control to lengthen the rr of the SUD, the td can be lengthened, and dma/dt can be suppressed and erroneous turn-on can be prevented. [Example] Between the base and emitter of a two-stage Darlington transistor, a base current of 0.1 A flows for turn-on.
When an SUD with a trr of 1 μsec or more was connected, erroneous turn-on operations could be prevented. Also, trr is 3 ps
When an SUD of ec or higher was connected, dv/dt could be effectively suppressed. However, if the rr of the SUD becomes too long, the td becomes too long and the turn-on loss increases, so it has been found that it is effective to connect an SUD with a trr of 3 to 4 ua@c. such a long t
Since rr can be realized, for example, by thickening the layer on the high resistance side of the SUD, it can also be implemented in a Darlington transistor with a built-in SUD. In addition, when using an external SUD, it is sufficient to use an SUD made using silicon single crystal, which has a long lifetime.
In Darlington transistors with three or more stages, the SUD is also connected between the base and emitter of the transistors in the second stage and below, but in that case, at least the one with a long trr is connected to the SUD connected between the base and emitter of the first stage transistor. It is necessary to use [Effects of the Invention] According to the present invention, in order to shorten the turn-off time of a Darlington transistor, the distance between the base and emitter of the SUD connected between the base and emitter of the first stage transistor is increased by simply lengthening the rr. dv/dt suppression equivalent to when connecting a capacitor. It has the effect of preventing erroneous turn-on, is advantageous in both cost and man-hours, and has the effect of shortening turn-off time, making it possible to obtain a transistor at low cost.

[Brief explanation of the drawing]

Fig. 1 is an equivalent circuit diagram of a Darlington transistor according to the present invention, Fig. 2 is an equivalent circuit diagram of a conventional capacitor-connected transistor, Fig. 3 is a current waveform diagram when the transistor is turned on, and Fig. 4 is an equivalent circuit diagram of a conventional capacitor-connected transistor. FIG. 2 is an equivalent circuit diagram of a conventional capacitor-connected Darlington transistor.

Claims (1)

[Claims] 1) At least in the case where a speed-up diode whose junction direction is opposite to the base-emitter junction is connected between the base and emitter of the first-stage transistor,
A Darlington transistor characterized by a speed-up diode whose reverse recovery time is controlled to be long.