JP2999268B2 - Pulse variable delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly, to a variable pulse delay circuit used for variable pulse delay.

[0003]

FIG. 3 shows a conventional pulse variable delay circuit. In the figure, a variable pulse delay circuit includes transistors Q1 and Q2, a constant current source I1, and resistors R1 and R2.
, An emitter follower including a transistor Q3 and a constant current source I2, a load capacitance CL, an operation comparator CMP1, and a D / A converter (voltage output) DAC1. This circuit uses D / A
By controlling the data DATA input to the converter DAC1, the delay amount of the rise of the input pulse PULSE is varied.

Next, the detailed operation principle of this circuit will be described based on the voltage waveform shown in FIG. Here, FIG.
Consider a case where an input pulse PULSE (positive pulse) as shown in FIG. At this time, the potential of the emitter of the transistor Q3 (point A in the figure) is changed from the potential ΔV _CC −V _BE (Q3) from the time when the rising edge t = t0 of the input pulse PULSE as shown in FIG. )｝ Than potential ｛V _CC -I1
・ It falls to R1-V _BE (Q3)｝ with dV / dt = I2 / CL. Further, when the input pulse PULSE is t = t2
Falls at the point of time, the potential at the point A becomes the potential ΔV _CC -I1
・ From R1-V _BE (Q3)｝ potential {V _CC -V _BE (Q
3) Get up quickly to ①. At this time, the output (QQ bar) voltage of the comparator CMP1, which uses the output voltage V0 of the D / A converter DAC1 as a threshold voltage, is t = t1 (falling) as shown in FIG. A positive pulse rises at the potential of the point A = time of the voltage V0) and falls at t = t3 (the potential of the point A at the time of the rise = time of the voltage V0). That is, the rise of the output (QQ ▲) pulse of the comparator CMP1 takes time Δt
= T1-t0 and therefore D / A
The delay time Δt can be made variable by changing the output voltage V0 of the converter DAC1, that is, by changing the data DATA input to the D / A converter DAC1. However, the comparator CM
The pulse width of the output of P1 (QQ bar) is Wt0-Wt1 = t2-t0- (t3-t1) = t1-
t0− (t3−t2) ▲ about ▼ Δt. If the pulse width becomes too short, a problem such as malfunction of a subsequent circuit occurs.

[0005]

As described above, in the conventional pulse variable delay circuit, the pulse width of the output pulse is determined by the threshold voltage, and in some cases, the pulse width is shortened to cause malfunction of the subsequent circuit. There was a drawback that it became an incentive.

The present invention solves the above problems,
An object of the present invention is to provide a pulse variable delay circuit that can variably delay an input pulse without substantially changing the pulse width of an output pulse.

[Structure of the Invention]

[0008]

In order to solve the above-mentioned problem, the feature of the present invention is to provide a constant current source I1 as shown in FIG.
Differential amplifier composed of a transistor and transistors Q1 and Q2
And a constant current source I with one output of the differential amplifier as an input.
An emitter follower constituted by 2 and the transistor Q3, and the capacitive load CL connected to the emitter of the transistor Q3 of the emitter follower, the emitter Roman
A first pulse variable delay circuit comprising: a comparator CMP1 connected to the emitter of the transistor Q3; and a second pulse variable delay circuits which are cascade-connected to said first pulse variable delay circuit in the same configuration as the first pulse variable delay circuit, the second pulse Friendly
The polarity of the differential input of the variable delay circuit is the first pulse variable delay.
This is the opposite of the polarity of the differential input of the extension circuit .

[0009]

[0010]

According to the pulse variable delay circuit of the present invention, the input pulse P
When the ULSE (positive pulse) is input, the potential of the emitter of the transistor Q3 is changed from the potential {V _CC -V _BE (Q3)} to the potential {V _CC -I1 · R1− from the rising edge of the input pulse PULSE. DV / d to V _BE (Q3)｝
It falls at a slope of t = I2 / CL. Also, the input pulse P
When ULSE falls, the rise of the emitter follower composed of the transistor Q3 and the constant current source I2 is steep, so that the potential of the emitter of the transistor Q3 becomes potential ｛V
_{From CC-} I1 · R1-V _BE (Q3)｝, the potential is V _CC -V _BE
(Q3) Stand up quickly to ①. Accordingly, the output (Q1-Q1 ▲) voltage of the comparator CMP1 that uses the output voltage of the D / A converter DAC1 as a threshold voltage is a positive pulse obtained by delaying the input pulse PULSE.

When the output voltage of the comparator CMP1 is input to the second pulse delay circuit, the potential of the emitter of the transistor Q6 becomes higher than the potential ΔV _CC − I1
・ R3-V _BE (Q6)} to potential {V _CC -V _BE (Q
6) Stand up steeply to｝. Also, the transistor Q6
From the falling point of the input pulse of the second pulse delay circuit at a slope of dV / dt = I2 / CL. Therefore, the output voltage of the comparator CMP2, which uses the output voltage of the D / A converter DAC1 as a threshold voltage, is a positive pulse having the same pulse width as the input pulse delayed from the input pulse of the second pulse delay circuit.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. FIG. 1 is a circuit diagram of a variable pulse delay circuit according to the embodiment. In FIG. 1, parts that are the same as in FIG. 3 (conventional example) are given the same reference numerals, and descriptions thereof are omitted.

In FIG. 1, a pulse variable delay circuit includes transistors Q1 and Q2, a constant current source I1, and a resistor R1.
, R2, an emitter follower including a transistor Q3 and a constant current source I2, and a load capacitance CL.
, An operation comparator CMP1 and a D / A converter (voltage output) DAC1, a first pulse delay circuit, and a second pulse delay circuit cascade-connected to the first pulse delay circuit. Note that the second pulse delay circuit is
Transistors Q4 and Q5, constant current source I1, and resistor R
3 and R4, an emitter follower including a transistor Q6 and a constant current source I2, and a load capacitance C
L, an operation comparator CMP2, and a D / A converter DAC1 common to the first pulse delay circuit.

Next, the detailed operation principle of the present circuit will be described based on the voltage waveform shown in FIG. Here, FIG.
Consider a case where an input pulse PULSE (positive pulse) as shown in FIG. At this time, the potential of the emitter of the transistor Q3 (point A in the figure) changes from the potential {V _CC -V _BE (Q3)} from the rising edge t = t0 of the input pulse PULSE, as shown in FIG. The potential ΔV _CC -I1
・ It falls to R1-V _BE (Q3)｝ with dV / dt = I2 / CL. Further, when the input pulse PULSE is t = t3
Falls at the point of time, the transistor Q3 and the constant current source I
2 rises sharply, the potential at point A is equal to the potential ΔV _CC -I1 · R1-V _BE (Q
3) Quickly rises from {} to the potential {V _CC -V _BE (Q3)}. Therefore, the comparator CMP1 which uses the output voltage V0 of the D / A converter DAC1 as a threshold voltage
Is a positive pulse having a pulse width Wt1 obtained by delaying the input pulse PULSE by Δt1, as shown in FIG.

The output of the comparator CMP1 (Q1-
Q1 bar) When the voltage is input to the second pulse delay circuit, the potential of the emitter of the transistor Q6 (point B in the figure)
As shown in FIG. 4D, the potential {V _CC −I1 · R3-V _BE (Q6)} is applied to the potential { V
It rises steeply to _CC- V _BE (Q6)｝. At this time, since the resistance R1 = R3, the potential ΔV _CC −I1 · R3
−V _BE (Q6)} is the potential {V _CC -I1 · R1-V _BE (Q
3)}, and the potential {V _CC -V _BE (Q6)} is equal to the potential {V _CC -V _BE (Q3)}. Further, the potential at the point B falls with a gradient of dV / dt = I2 / CL from t = t4, that is, from the falling point of the input pulse of the second pulse delay circuit. Therefore, the comparator CMP using the output voltage V0 of the D / A converter DAC1 as a threshold voltage
The output (Q2-Q2) voltage of the second pulse delay circuit is represented by Δt2 = Δt, as shown in FIG.
This is a positive pulse having a pulse width Wt2 delayed by 1+ (t2-t1). here, Since t2−t1 ▲ about ▼ 0, the output pulse of the pulse delay circuit according to the present embodiment is the input pulse PULSE
Is delayed by approximately Δt1, and the pulse width is the same as the input pulse.

[0017]

As described above, according to the present invention, the variable pulse delay circuit is a two-stage cascade connection of the first variable pulse delay circuit and the second variable pulse delay circuit, and the second variable pulse delay circuit The polarity of the differential input of the first variable pulse delay circuit is opposite to the polarity of the differential input of the first variable pulse delay circuit, so that a pulse variable delay circuit capable of outputting a pulse having almost the same pulse width as the input pulse regardless of the threshold voltage. realizable.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a variable pulse delay circuit according to an embodiment of the present invention.

FIG. 2 is a voltage waveform diagram of each part of the variable pulse delay circuit according to the embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional pulse variable delay circuit.

FIG. 4 is a voltage waveform diagram of each part of a conventional variable pulse delay circuit.

[Explanation of symbols]

 Q1 to Q6 Transistor I1 to I2 Constant current source CL Capacitive load R1 to R4 Resistance CMP1, CMP2 Comparator DAC1 D / A converter PULSE Input pulse

Claims (1)

(57) [Claims] 1. A circuit comprising a constant current source and two transistors.
A differential amplifier to be formed and one output of the differential amplifier
As an emitter follower constituted by the constant current source and the transistor, and a capacitive load connected to the emitter of the transistor of the emitter follower, the emitter Roman
A first pulse variable delay circuit comprising: a comparator connected to an emitter of a transistor of the second circuit; a D / A converter connected to the comparator for supplying and controlling a reference potential of the comparator; have a second pulse variable delay circuits which are cascade-connected to said first pulse variable delay circuit in the same configuration as the delay circuit, wherein
The polarity of the differential input of the second pulse variable delay circuit is the first pulse variable delay circuit.
Wherein the polarity of the differential input of the pulse variable delay circuit is opposite to the polarity of the differential input .