JPH03146886A - Semiconductor integrated device - Google Patents

Abstract

PURPOSE:To attain an efficient operation test for device available for general purpose by interrupting the control from a CPU at the testing time and sending a signal circuit for test into a control register direct from a test mode generating circuit. CONSTITUTION:When a normal operation is performed, i.e. at the time of non- test mode, a test mode control circuit 15 is subjected to become non-operative condition, and a WR signal (3) come from the CPU 11 is made effective and inputted to the control register 13 provided in a peripheral function circuit part 12 to make an inside circuit 22 to ENABLE, thereby the inside circuit in the peripheral function circuit part 12 is operated by data signal (2) of the CPU 11. At the test mode time, on the other hand, the connection between the CPU 11 and the control register 13 is interrupted by the test mode signal come from the test mode signal generating circuit 20, e.g. '0', and at the same time, by exerting the test mode control circuit 15, a control signal for control register outputted from the test mode generating circuit 14 is inputted to the said control register 13 to operate the peripheral function circuit part 12. With this arrangement, the efficient operation test available for general purpose is attained.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor integrated device in which a microcomputer and a peripheral function circuit are configured on one chip, and the present invention aims to efficiently perform a test to discover initial failures of the semiconductor integrated device. (1) A peripheral function circuit section, a test mode generation circuit, and a control register that controls the microcomputer in the test mode. The chip is configured to include a test mode control circuit which is controlled by a control signal from the test mode generation circuit.

[Industrial application field]

The present invention relates to a semiconductor integrated device in which a microcomputer and a plurality of peripheral function circuits are formed on one chip.

[Conventional technology]

In recent years, semiconductor integrated circuits, generally referred to as one-chip microcomputers, in which a microcomputer and multiple peripheral function circuits are formed on a single chip, have become increasingly dense and integrated, making it difficult to ship these products. We conduct so-called burn-in tests or accelerated tests to detect initial defects on the product and eliminate defective products before the shipping test, which is carried out when the product is shipped. There is a growing demand for this. However, in such a semiconductor integrated device, there may be a contact failure or other problem in a part of the circuit of the product.
If there is a short-circuited part, there is a risk that the device will not work or will be destroyed, so it is necessary to remove the product with such a defective part at an early stage before shipment testing. Although it is a test,
Conventionally, a microcomputer (hereinafter referred to as CPU) provided on a chip has been used to test whether or not a peripheral function circuit section operates.

FIG. 3 shows a specific example of a conventional semiconductor integrated device, that is, a one-chip microcomputer, in which a chip 1 includes a CP[I 31, a RAM 32 which is a read/write memory, and a RUM 3 which is a read-only memory.
3, and a plurality of peripheral function circuit units 3 called resources.
4 to 36 are provided, and each is electrically connected by an internal bus 37.

The chip is provided with a clock input section 38 for operating the one-chip microcomputer (3) and a reset signal input section 39 for initializing the internal circuit.

Conventionally, when attempting to perform the above-described test on a semiconductor integrated device having such a structure, it is necessary to store a test instruction code for operating the CPU 31 in the ROM. However, the CPU instruction code may differ depending on the semiconductor device.
Each time, it is necessary to rewrite the instruction code and input it into the ROM.

This is a complicated task and also involves a large loss of time.

Furthermore, since the circuit configuration and number of peripheral function circuits differ depending on the product, it is necessary to change the instruction code and the capacity of the ROM, resulting in lack of versatility and low test efficiency.

[Problem to be solved by the invention]

The purpose of the present invention is to improve the above-mentioned drawbacks of the prior art, and to provide a semiconductor integrated device with a built-in test circuit that is versatile and capable of simultaneously and efficiently testing the operation of a large number of semiconductor integrated devices. This is what I am trying to do.

[Means to solve the problem]

The semiconductor integrated device according to the present invention employs the following technical configuration in order to achieve the above-mentioned object. That is, a microcomputer section 11, a peripheral function circuit section 12 having a plurality of control registers 13 connected to the microcomputer section, a test mode generation circuit 14,
This semiconductor integrated device includes a test mode control circuit 15 in a chip, which separates the control register 13 from the control of the microcomputer in the test mode and controls it by a control signal from a test mode generation circuit.

[For production]

In the semiconductor integrated device of the present invention, when testing whether a peripheral function circuit is operating or not, control from the CP[I built in the computer is cut off, and (5) each peripheral function circuit section is directly controlled from the test mode generation circuit. Since the test is performed by sending a test signal to the control register that has the CPU, there is no need to create a different test program and store it in the ROM 17 etc. each time the CPU is changed, and there is also a large amount of It is possible to simultaneously test multiple semiconductor integrated devices in a general-purpose manner.

〔Example〕

Hereinafter, specific examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of the principle of the present invention.
[I 11, peripheral function circuit section 12, ROM 17, RA
M18, a test mode generation circuit 14, a test mode control circuit 15 are provided, and a peripheral function circuit section 12
A control register section 13 and an internal circuit 22 are provided.

- The test mode control circuit and control register section have a circuit configuration as shown in FIG. 2, for example. Further, the test mode generation circuit section 14 has a test mode signal generation section 20 and a (6) control register control signal generation section 21 in the test mode.

During normal operation (that is, non-test mode), the test mode control circuit 15 is in a non-operating state and the W from CPt1 is
The R signal section is enabled, the WR signal section is input to the control register 13 in the peripheral function circuit section 12, the internal circuit 22 is enabled, and the data signal ■ of CP[I is input to the control register 13 in the peripheral function circuit section 12.
operate the internal circuits within. On the other hand, in the test mode, the test mode signal from the test mode generator, for example “0
”, the connection between the CP[I 11 and the control register 13 is cut off, and the test mode control circuit 15 is activated so that the control register control signal outputted from the test mode generator is inputted to the control register 13 to control the peripheral function circuit. This is to operate the section 12.

FIG. 2 shows an example of the internal circuit configuration of the test mode control circuit 15 and control register 13 used in the present invention. That is, the test mode control circuit 15
Consisting of a D circuit 16 and a switching control circuit 19, one input of the NAND circuit 16 receives input from the WR signal section of the CPU 11, and the other input receives a signal from the test mode signal generation section 20 of the test mode generation circuit (7) 14. The output test signal ■ is input. On the other hand, the switching control circuit 19 receives the test signal ■ via the inverter 23 at one input, and receives the control register control signal ■ from the control register control signal generator 21 of the test mode generation circuit 14 at the other input.
The NOR gate 25 is comprised of a NAND gate 24 to which is input the test signal 2, and a NOR gate 25 to which the test signal 2 is input to one input and the control signal 2 is input to the other input. - the force control register 13 includes a first control circuit section 13-1 controlled by the NAND gate circuit 16;
a second control circuit section 132 controlled by the output of the switching control circuit 19; and an inverter circuit 13 having a feedback circuit.
-3, and the first control circuit section includes a high potential power source V,. Two P-type MOs are connected between
3FE! T (TllT2) and two N-type MO3FEITs
(T3.T,) are connected in series in this order,
A NAND gate circuit 1 is connected to the gate of the transistor T+.
6 is input, and the same output is input to the gate of the transistor T4 via an inverter. -Power test run (8>) CPU data (■) is commonly input to the gates of registers T2 and T.

On the other hand, the second control circuit section 13-2 is connected to a high potential power source V. P-type and N-type MO3FETs (T
s, Ta) are arranged in series, and the output of the first control circuit section 13-1 is input to the connection section between both transistors. Further, the gate of the transistor T5 is connected to the NAN
The gate of the transistor T6 is connected to the output of the NOR gate 25, and the gate of the transistor T6 is connected to the output of the NOR gate 25.

The third control circuit section 13-3 is inserted so as to maintain the voltage at a constant level even when the first and second control circuits are in a floating state.

Further, in the present invention, the signal output from the control register control signal generating section 21 in the test mode generating circuit section 14 is not particularly limited, but is used to at least determine whether or not the peripheral function circuit section is operating. For example, it may be a clock signal obtained by dividing the clock signal as appropriate.

(9) Next, the operation of the above circuit will be explained.

In this specific example, when the output signal ■ from the test signal generator 20 is "1", that is, "H", it is the normal operation mode, and when it is "0", that is, "L", it is the test mode. I'll decide.

Therefore, if the signal output (■) is set to "H" to set the normal operation mode by an external signal, the switching control circuit 19
Since the NANO gate circuit 24 receives an "L" signal at one input via the inverter 23, it outputs an "H" level regardless of the level of the other input. Therefore, the second control circuit 13-2 of the control register 13
The transistor T5 is turned off. Since the NOR gate circuit 25 of the one-way circuit 19 receives an "H" level signal at one input, it outputs an "L" level regardless of the level of the other input. Therefore, the transistor T6 of the second control circuit 13-2 is turned off.

Therefore, the second control circuit 13-2 is in a floating state. - The "H" level output of the power output signal ■ is input to one input terminal of the NANO gate circuit 16 (10).Therefore, when the CPU 11 outputs a "H" level signal on the WR signal, the NAND The output of the gate circuit 16 becomes "L" level, thereby turning on the transistor T+ in the first control circuit 13-1 of the control register 13, and turning on the transistor T by the inverter.
Since the H'' level signal is input, the transistors T2 and T3 turn on. Therefore, the transistors T2 and T3 have an inverter function, and a signal obtained by inverting the data ■ signal from the CPU is output from the first control circuit 13-1. This is the second
through the third control circuit 13-2, and the third control circuit 13-3.
Therefore, the output of the third control circuit 13-3 is C
An output signal identical to the data of the PU 11 is obtained, and the internal circuit of the peripheral function circuit section 12 is activated by this signal.

Next, when testing this semiconductor integrated device, the output signal of the test mode generating section of the test mode generating circuit 14 is set to the "L" level by appropriate external means. NAND
Since an "L" level signal is input to one input terminal of the gate circuit 16, the NA is input regardless of the level of the WR signal.
Since the output of the ND gate becomes "H" (11), transistors T+ and T4 in the first control circuit 13-1 are turned off, so that the data of CP[I11 passes through the first control circuit even if it is input manually. I can't do it. In other words, the connection between the control register and the CPU is cut off.

On the other hand, in the switching control circuit 19, the NAN[] gate 2
An “H” level signal is input to one input of N4.
Since the "L" level signal is input to one input of the OR gate 25, the control register control signal generator 2
If the control register control signal ■ from 1 is “H”, NA
An "L" signal is output from the ND gate 24, and the transistor T5 of the second control circuit 13-2 is turned on, while the N
Since the OR gate 25 also outputs an "L" signal, the transistor T6 of the control circuit 13-2 is turned off, and as a result, the output of the second control circuit 13-2 becomes "H".

- When the right control signal (2) is "L", the completely opposite relationship to the above is established, and the output of the second control circuit 13-2 becomes "L". Therefore, the output of the second control circuit 13-2 becomes the same signal as the control register control signal (1), which is inverted by the (12>3rd control circuit 13-3) to operate the peripheral function circuit section.

That is, in the test mode, the peripheral function circuit section is separated from the CPU 11, and the test mode signal output from the test mode generation section 14 provided separately from the CPU and the control register that controls the control registers in the peripheral function circuit section during the test mode are used. The peripheral function circuit section is operated by the control signal. In this specific example, an example in which only one peripheral function circuit section 12 is provided on one chip in FIG. It is also preferable that each peripheral function circuit section has a built-in control register.

One test mode generation circuit section 14 in the present invention may be provided on one chip, and may be connected to each peripheral function circuit section in sequence by appropriate addressing means. Similarly to the test mode generation circuit section 14, the switching control circuit section 19 may also be provided on one chip and connected to each peripheral function circuit section through address means. The test at this stage in (13) of the present invention does not test whether each output terminal of the peripheral function circuit operates according to a specified program, but rather simply tests whether the peripheral function circuit operates. Since it is sufficient to test only whether or not the control register control signal is set, a simple program is sufficient.

Also, in order to check whether each peripheral function circuit is operating using this program, for example, there is a method of placing a detector on a specific output terminal of the peripheral function circuit and measuring its voltage. It can be used. The test mode generation circuit section and its operation program in the present invention are described in CP.
[I 11 may be executed.

〔effect〕

In the present invention, by adopting the above configuration, the peripheral function circuits in a one-chip microcomputer etc. can be operated separately from the CPU in the test mode, so that the CP[
Even if the I and the instruction system (14) are different, there is no need to rewrite the test program, and the peripheral function circuit can be operated for testing with only specific signals. Since there is no need to change the instruction code of the ROM even if the number of functional circuit units differs, the test work is simplified and the test can be executed at low cost and with high efficiency.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the structure and principle of a semiconductor integrated device according to the present invention. FIG. 2 is a diagram showing an example of a circuit configuration of a control register and a switching control circuit in a semiconductor integrated device according to the present invention. FIG. 3 is a diagram showing an example of a conventional semiconductor integrated device. 1... Semiconductor integrated device, 11, 31... Microcomputer, CPU12
, 34 , 35 , 36 ... peripheral function circuit section, 13
... Control register, 14... Test mode generation circuit section, 15... Test mode control circuit, (15) 16... NANO gate circuit, 17, 33...
ROM. 18, 32... RAM, 19... Switching control section, 20... Test mode signal generation section, 21... Control register control signal generation section, 22... Internal circuit of peripheral function circuit section, 23...Inverter,
24...NAND gate circuit, 25...NOR
Gate circuit, 13-1... First control circuit, 13-2... Second control circuit, 13-3... Third control circuit, 37... Internal bus, 38... Clock input terminal, 39
...External signal input terminal. (16)

Claims (1)

[Claims] A microcomputer section, a peripheral function circuit section connected to the microcomputer section and having a plurality of control registers, a test mode generation circuit, and a test mode generation circuit for separating the control registers from the control of the microcomputer during the test mode. 1. A semiconductor integrated device comprising, within a chip, a test mode control circuit that performs control based on control signals from a semiconductor integrated device.