JPH03146885A - Testing device for integrated circuit - Google Patents

Abstract

PURPOSE:To enable other normal testing even in the case a test pattern or handler is in faulty state by making the timing for index completion of handler and test start to coincide, and supplying the test pattern signal. CONSTITUTION:The testing is made to start when a switching part 20 is operated by a control signal Sc according to an AND of the timing signal S outputted from a test controller 4 and the test starting signal S outputted from a handler controller 19 to supply the test pattern Sp to a driver circuit 9. Then, the test is finished by the control signal Sc in the manner of making the operation to be OFF with a test ending signal S. In a main body of the tester, the test is automatically repeated and the test pattern signal Sp is supplied to a station 12 by making the timing for the index completion of handler 19 and the test start to coincide. By this arrangement, even in the case the station 12 or handler 19 is faulty, other normal tests can be made since only the test station can be cut off from the main body of tester.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an integrated circuit testing device, and particularly to an IC testing device (hereinafter referred to as an IC tester) for performing an operation test of an integrated circuit (hereinafter referred to as an IC). .

[Conventional technology]

Forming device 3. A test device main body 5 having a tester controller 4 etc. is connected to the test device main body 5 by a signal cable 6 for transmitting the test pattern Sp generated in the test device main body 5, and the test signal 7 is transmitted to the IC under test (
A driver circuit 9 and an output signal S of the DUT 8 are applied to the DUT 8 (hereinafter referred to as DUT). The test circuit 12 includes a comparator circuit 11 and the like for comparing the value with an expected value.

[Problem to be solved by the invention]

In conventional testers, as shown in Figure 4, the I
A handling device 13 (hereinafter referred to as a handler) of C is connected to the test station 12 and supplies a test pattern signal SP to the DUT 8.

The handler 13 sequentially indexes a plurality of DUTs, and issues a test start signal Ss when the supply of the test pattern signal Sp to the DUT 8 is completed.

The tester body 5 starts a test upon receiving the test start signal Ss, and issues a test end signal S8 to the handler 13 when the test is completed.

The handler 13 receives the test end signal S8 and sends the DUT8
index.

In general, in the mass production of memory ICs, the processing power improves as the number of memory IC testers that can be simultaneously measured in parallel increases, so the number of memory ICs increases year by year from 4 to 8 to 16 to 32. .

Conventional testers usually have two test stations, and the above-mentioned increase in the number of test pieces is dealt with by increasing the number of test pieces per station.

The number of parallel measurements will continue to increase, and as the number of parallel measurements increases, the test station will naturally become larger.

In this case, the transmission path of the test signal from the driver to the DUT becomes long, leading to a decrease in measurement accuracy due to deterioration of the waveform.

For this reason, it is possible to increase the number of parallel measurements without increasing the size of the test stations by increasing the number of test stations from conventionally two to four or more.

When a large number of test stations are connected to one tester in this way, if one test station breaks down, the entire tester must be stopped, which has a large impact on operating time. I'll give it away.

Also, in testers with a large number of test stations,
The handler connected to each test station is DU
The speed at which T is indexed varies from handler to handler.

Therefore, in order to start parallel measurements on all test stations at the same time, it is necessary to wait for the test start signal of the handler with the slowest index.

Normally, a wait time is set according to the handler with the slowest index, and if the test start signals of all handlers come during that time, the wait time will be set according to the handler with the slowest index.
Also, if all the items are not collected during the waiting time, the tester starts the test when the waiting time expires.

At this time, if one handler stops, the test start signal is not output from this handler, so the tester always waits for the waiting time before starting the test.

This results in wasted time compared to when all handlers are operating, and this affects the processing capacity of other handlers of the tester to which the corresponding handler is connected.

[Means to solve the problem]

The test station of the tester of the present invention includes a test device main body having a timing generator, a pattern generator, and a waveform shaper, a switch section that connects or disconnects a test pattern signal output from the test device main body according to a control signal, and a a driver 5- for supplying the test pattern signal to the test integrated circuit; and a control section for outputting a pattern start timing signal from the test device main body and a test start signal upon index completion from the hattling device as a control signal for the switch section. It is composed of:

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIGS. 1(a) and 1(b) are a block diagram of an embodiment of the tester of the present invention and a circuit diagram of a station controller.

The integrated circuit testing apparatus includes a tester main body 5 having a timing generator 1, a pattern generator 2, a waveform shaper 3, and a tester control 4 for supplying test control signals to each of the devices 1 to 3; The test pattern signal SP to be output is the control signal S. The driver circuit 9 supplies the test pattern signal SP to the switch unit 20 which controls on/off operation by the DUT 8, the timing signal ST output from the tester controller 4, and the output 6 of the hunt run roller 19.
- The control signal S rises at the AND output of the test start signal S8 and is reset by the test end signal S6. and a test station 12 having a station controller 18 that outputs.

The controller 4 controls the pattern generator, the timing generator cloud, and the waveform shaper 3, and constantly repeats the test.

There is a waiting time between tests that are constantly repeated.

Before the test starts, the timing signal ST
is output from the tester controller 4.

The test station 12 is the station controller 1
8, the handler 13 indexes the DUT 8,
When measurement is possible, controller 1
The flip-flop FF is driven by the logical product of the test start signal S8 outputted by the circuit 9 and the above-mentioned timing signal ST, and the switch unit 20 is controlled by the control signal S. is turned on, and the test pattern signal S output from the tester main body 5 is supplied to the driver 9.

In addition, the flip-flop FF receives a test end signal S8.
to turn off.

Similarly, the result S□ of the output 10 of the DUT 8 determined by the comparator circuit 11 is also supplied to the tester body 5.

FIG. 2 is a timing chart of signals of each part for explaining the operation of the blocks in FIG. 1.

Timing signal S output from tester controller 4
A control signal S is a logical product of T and a test start signal S8 output from the handler controller 19. When the switch unit 20 operates and the test pattern SP is supplied to the driver circuit 9, the test starts.

Next, the control signal S. As a result, the test end signal S8 is turned off and the test ends.

In the tester of this embodiment, the tester itself automatically repeats the test, and the test pattern signal is supplied to the test station at the same time as the completion of indexing of the handler and the start of the test.

In addition, in the above-mentioned embodiment, the tester main body 5 and the driver circuit 9
Even if the switch unit 20 installed between 0 and the DUT 8 of the driver circuit 9 is installed, the function and expected effect will be the same.
This is equivalent to the embodiment.

〔Effect of the invention〕

As explained above, the tester body of the IC tester of the present invention automatically repeats the test and supplies the test pattern signal to the test station at the same timing as the completion of the index of the handler and the start of the test. Even if one test station is stopped due to a failure of the handler or a failure of the handler, only that test station can be separated from the tester main body, so the test of other normal test stations will not be affected.

Furthermore, as the number of parallel measurements increases, a tester can be constructed by connecting a large number of test stations for decimal parallel measurements.

In this case, the main body of the tester that generates the pattern is 19-, and the required number of test stations can be connected to the test pattern output from it.

In this case, the tester of the present invention allows the test station to be disconnected without affecting the operation of the tester itself and other test stations.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a block diagram of an embodiment of the present invention and a circuit diagram of a station controller, and FIG. 2 is a timing diagram of signals of each part to explain the operation of the blocks in FIG. 1. 3 is a block diagram of an example of a conventional tester, and FIG. 4 is a block diagram for explaining a case where the conventional tester is connected to a handler. 1... Timing generator, 2... Pattern generator, 3... Waveform shaper, 4...
・Tester controller, 5...Test device body, 6...Signal cable, 8...DUT
, 9...driver circuit, 10...DU
Output of T8, 11... Comparator circuit, 12
... lO- ... Test station, 13 ... Handler, 18 ... Station controller, 19.
...Handler controller, 20...Switch section. Sl...Test end signal, sl...Index signal, SP...Test pattern signal, Ss...Test start signal, ST...
...Timing signal.

Claims (1)

[Claims] A test device main body including a timing generator, a pattern generator, and a waveform shaper, a switch unit that connects or disconnects a test pattern signal output from the test device main body according to a control signal, and a switch unit that connects or disconnects a test pattern signal output from the test device main body, and connects or disconnects the test pattern signal to an integrated circuit under test. An integrated circuit testing device comprising: a driver that supplies a pattern start signal from a test device main body; and a control section that outputs a pattern start timing signal from a test device main body and a test start signal upon index completion from a handling device as a control signal for a switch section. .