JPH03144841A - Data processing system - Google Patents

Abstract

PURPOSE:To attain the asynchronous transfer of data between a main storage and an extension storage without using a channel processor by using an instruction processor kept in a wait state to perform the asynchronous transfer of data between the main storage and the extension storage. CONSTITUTION:A data processing system consists of plural instruction processors 1A - 1D, a storage controller 2, the input/output processors 3A - 3D, a main storage MS 4, and an extension storage ES 5. The data are transferred between the MS 4 and the ES 5 with the transfer instructions. These instructions includes the synchronous and asynchronous instructions, and an instruction code, an MS address, an ES address, and the data transfer quantity are designated to each of both instructions. In such a constitution, no channel processor is required for an asynchronous process and therefore the data transfer ability of a channel is never deteriorated when data are transferred between an external storage and the MS 4. Then the same throughput as a synchronous transfer system is secured for transfer of data between the MS 4 and the ES 5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing system, and particularly to a data processing system having a plurality of instruction processors, an input/output processing device, a main storage device, and an extended storage device. be.

[Prior art]

Conventionally, as a data transfer method between a main storage device (MS) and an expanded storage device (ES), there are a synchronous transfer method and an asynchronous transfer method, as described in Japanese Patent Laid-Open No. 58-9276.

The synchronous transfer method immediately executes data transfer between the MS and ES according to the MS address and ES address specified by a synchronization command.

In contrast, the asynchronous transfer method uses an instruction processor (I
After P) starts up the channel processor by executing an input/output instruction, the channel processor learns the starting address of the channel program from the channel address word (CAW) and executes the channel program in order.

A channel program is a list of channel control words (CCW), and the CCW describes the request type, MS address, and ES address.The channel processor continuously decodes and executes the CCW, thereby
Transfers data between MS and ES.

This data transfer is a process instructed by an IP input/output command, but is called asynchronous transfer because it is executed independently without synchronization with the IP after the IP input/output command is completed.

[Problem to be solved by the invention]

Three-media transfer is an effect of having a channel processor perform asynchronous transfer between MS and ES (for example, Japanese Patent Laid-Open No. 58-9276).

Three-media transfer means that when a channel is activated by a single input/output command and a channel program is executed, data is transferred successively to external storage (DASD) MS and ES using a command chain.

However, if the MS has sufficient capacity, transfer between DASD and ES is possible without the need for three-media transfer.
This can be achieved by combining transfers between

However, if the channel processor does not support three-media transfer but only supports asynchronous transfer between MS and ES,
There are the following problems.

(1) To support the asynchronous transfer method between MS and ES, when activated from IP, the channel processor
Know the start address of the CCW from W, fetch the CCW, decode the CCW, and if the sequence of CCW indicates data transfer between MS and ES, send the MS address and ES address to the storage controller ('sc). Transfer to MS,
Executes data transfer between ESs. Therefore, special hardware is required for the above processing, and special hardware is also required on the SC side to receive these addresses and execute data transfer between the MS and ES.

(2) Select a specific channel for asynchronous transfer between the MS and ES, and use an external storage device (DA) for this channel.
SD) is not connected and the channel processor is a dedicated processor for asynchronous transfer between MS and ES, DA
The channels available for normal data transfer between SD and MS are reduced accordingly.

Furthermore, if one channel allows data transfer between a normal DASD and an MS, and data transfer between an MS and an ES, not only will the structure of the channel processor become complicated, but the two processes will overlap. This may result in high channel utilization and degraded system performance.

(3) If the channel processor supports the asynchronous transfer method, the channel processor
and that the processing by the channel processor is
Since it is slower than P, overhead occurs in the process of transmitting addresses and control signals to the MS and ES, resulting in a lower overall data transfer throughput than the synchronous method, resulting in poor performance. be.

The present invention has been made to solve the above problems.

It is an object of the invention to
, an object of the present invention is to provide a data processing system that enables asynchronous transfer between ESs.

[Means to solve the problem]

To achieve the above objective, a plurality of instruction processors;
In a data processing system having a main storage device and an expanded storage device, an instruction processor in a wait state executes asynchronous transfer between the main storage device and the expanded storage device.

[For production]

Main memory (MS) from the instruction processor (IP)
Processing of an instruction that instructs data transfer between an ES and an extended storage device (ES) is performed by all IPs in the system, including the type of data transfer, MS address, ES address, and amount of data transferred, depending on the IP that first issued the instruction. Store in a retrievable register or storage device. The IP that performs data transfer processing between the MS and ES is one IP out of all the IPs in the system.
P is determined by the selecting circuit and a data transfer request is sent to the selected IP.

The IP transfers activation information from the register or storage device into its own IP, and uses this activation information to
Transfer data between

After the data transfer between MS and ES is completed, the completion report is sent to all IPs in the system as a traffic interruption request, and one IP
P performs interrupt processing.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a block diagram of a data processing system according to an embodiment of the present invention.

As shown in FIG. 1, this data processing system includes a plurality of instruction processors (IP) IA-ID.

Storage control unit (SC) 2, input/output processing unit (IOP) 3
A to 3D, main memory (MS)4. and an expanded storage device (ES) 5.

Data transfer between MS and ES is performed by a transfer command. The instructions include synchronous instructions and asynchronous instructions, and both instructions specify an instruction code, MS address, same S address, and data transfer amount.

Figure 2 shows the main memory (MS) and expanded storage (ES).
FIG. 3 is a diagram illustrating an example of the format of a transfer command (asynchronous) for transferring data between. This instruction is an asynchronous instruction, and the processing of the instruction and the actual processing do not need to be synchronized.

As shown in FIG. 2, an instruction for transferring data between an MS and an ES is an instruction code 11.
MS address 12. The configuration includes an ES address 13 and a transfer block number 14 indicating the amount of data transfer.

Figure 3 shows the main memory (MS) and expanded storage (ES).
12 is a flowchart showing the processing of an instruction processor (rp) on the instruction issuing side for an instruction that transfers data between two computers.

Here, as types of commands, a data transfer command from MS to ES (WRITE ES) and a data transfer command from ES to MS (READ ES) are shown.

When the IP is instructed to start processing a data transfer command between the MS and ES, the IP accesses the hardware dedicated access area (
Hardware System Area: HS
A) Lock the upper ES startup queue (step 301).

Next, check whether there is already one or more data transfer requests between the MS and ES in the ES activation queue (step 302).
, if there is already one or more, nothing is done, but in the case of O, it is assumed that the above-mentioned request has newly occurred and Ill is set in the latch (latch 21 in FIG. 4) indicating that the above-mentioned request exists (step 303).

Next, create ES startup information from the data set up inside the IP, enqueue it to the ES startup queue (step 304), and release the lock (step 305).
), the processing of the instruction issuing IP ends.

Of course, the location where the ES activation information is set may not be in the H3A, but in a dedicated register that can be accessed by all IPs in the system.

Figure 4 shows the main memory (MS) and extended storage (E, S).
) is the most suitable instruction processor (I) for data transfer between
FIG. 3 is a diagram showing a circuit for selecting P).

When there is a data transfer request between the MS and ES, “1” is set in the latch 21 via the OR gate 22.

From each IP, signals indicating a wait state (23A-D) and a stop state (24A-D) are sent to the storage control device i[(
SC) 2, the former is input via OR gates 25A to 25D, and the latter is input as is to AND gates 26A to 26D. The outputs of configuration control registers 27A-D are input to AND gates 26A-D.

The output of the AND gates 26A-D is (1) IP is S
(2) When the IP is connected to the SC and is not in the stop state, and the output of the latch 21 becomes 1', the counter indicates that a predetermined time has elapsed. If the decoder 29 detects the output of 28, it becomes '1'.

When the output of the AND gates 26A-D is 1' and the output of the latch 21 is 11', the output of the AND gates h30A-D is 1'', which is input to the selection circuit 31.Selection circuit 31
If there are a plurality of input signals of 1' from the AND gates 30A-D, one IP is selected according to a predetermined priority order. For example, select the lowest IP number.

Only one of the output signals 32A-D of the selection circuit becomes 1', and the selected IP breaks in to perform data transfer between the MS and ES.

To summarize the conditions for selecting an IP here, in the case of (1) above, if you select an IP that is in the wait state, not in the stop state, and in the connected state with the SC, the MS, ES This shows that there is no loss in performance even when data is transferred between

In the case of (2) above, since the above-mentioned IP is not found, the system is designed to be equivalent to the case where a predetermined period of time has elapsed after the latch 21 is set, and the system is forcibly placed in a wait state. The signal line 33 becomes '1' and the OR gate 25
It is input to A-D.

The time at which the output of the decoder 29 becomes '1' after a predetermined period of time has elapsed varies depending on the system. This shows that even if there is no waiting IP, the request will always be accepted after a certain amount of time.

The output signal of the selection circuit passes through an OR gate 34 and a delay circuit 35 to reset the counter 28. The latch 21 is for each IP
It can be reset from Also, 36 is an or gate.

Figure 5 shows the main memory (MS) and expanded storage (ES).
12 is a flowchart showing the processing of an instruction processor (rp) that takes over and executes an instruction for data transfer between two computers from an instruction issuing side.

The IP that took over the data transfer request between the MS and ES is )I
Lock the ES startup queue area on SA (step 5ol).

A data transfer request between the MS and the ES is dequeued from the ES activation queue (step 502).

If the queue is empty after dequeuing (step 503
), the latch 21 is reset (step 504).

Next, fetch the boot information from H5A and send it to MS.

Data transfer between ESs is executed (step 505).

After the data transfer is completed, the ES activation queue is unlocked (steps 506 and 507).

Next, the I/O interrupt queue on H3A is locked (step 508). Then, it is checked whether the interrupt queue is empty (step 509), and if it is empty, the latch 41
is set to '1' (step 510), this latch indicates that there is one or more I/O interrupt requests.

The end of data transfer between the MS and ES is enqueued in the input/output interrupt queue as one interrupt request (step 51).
1). This queue consists of 1 normal input/output interrupt, MS, ES
An interrupt caused by the end of data transfer (ES access end interrupt) can be registered at the same time. Then, the input/output interrupt queue is unlocked (step 512).

Figure 6 shows the instruction processor (IP), input/output processing unit (
3 is a circuit diagram showing the relationship between IOP) and a latch 41. FIG.

The latch 41 is connected to each Ip (IA-D), each IOP (3A-
D) can be set via the OR gate 42 and reset via the OR gate 43.

Furthermore, the output of the latch 44 is input to each IP.

FIG. 7 is a flowchart showing an outline of the input/output interrupt processing routine. Since this input/output interrupt is a floating interrupt, in the case of a multiprocessor, any IP can handle the interrupt.In response to an interrupt request from the 9 latch 41, one or more IPs break in and enter the interrupt processing routine. .

The IP locks the I/O interrupt queue on the H8A (step 701).

If multiple IPs attempt to lock almost simultaneously, one IP will succeed in locking, and lock requests from other IPs will be forced to wait until unlocking.

That is, the process is serialized.

The IP that has successfully acquired the lock checks whether the input/output interrupt queue is empty (step 702). If it is empty, the lock is released and the process ends without doing anything (step 707).

This means that even if there is one interrupt request and multiple IPs break in for input/output interrupt processing and enter one interrupt processing routine, only one IP will process the interrupt and other IPs will
P indicates to exit this routine without doing anything.

As a process when the input/output interrupt queue is not empty, an interrupt request due to the end of data between the MS and ES (ES access end interrupt) is dequeued from the input/output interrupt queue,
Interrupt processing is performed (steps 703 and 704).

If the queue becomes empty after interrupt processing is executed, latch 4
1 (step 706).

Then, the input/output interrupt queue is unlocked and the process ends (step 7o7).

〔Effect of the invention〕

As described above, according to the present invention, in a data processing system having a plurality of instruction processors, an input/output processing device, a main storage device, and an expansion storage device, data transfer between the main storage device and the expansion storage device is possible. Since it is possible to have one of the plurality of instruction processors described above execute the processing of the asynchronous instruction that performs Control can be simplified.

In addition, since the channel processor is not used for asynchronous processing, when data is transferred between external storage and main storage, the data transfer ability of the channel is not impaired.
Data transfer between the main storage device and the extended storage device can ensure throughput comparable to that of the synchronous transfer method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing system according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the format of a transfer command, and FIG. 3 is a diagram showing an example of the format of a transfer command.
Flowchart showing the processing of the instruction processor on the instruction issuing side. FIG. 4 is a diagram showing a circuit for selecting an instruction processor. FIG. 5 is a flowchart showing the processing of the instruction processor taking over from the instruction issuing side. 5. FIG. 6 is a circuit diagram showing the relationship between the instruction processor, the input/output processing device, and the latch, and FIG. 7 is a flowchart showing the outline of the input/output interrupt processing routine. In the figure, IA-ID...instruction processor, 2... storage control device, 3A-3D... input/output processing device, 4...
Main storage device,...Extended storage device, 21゜41...Latch, 28...Counter, 3! ...Selection circuit.

Claims (1)

[Claims] 1. In a data processing system having a plurality of instruction processors, a main memory device, and an expanded storage device, an instruction processor in a wait state executes asynchronous transfer between the main storage device and the expanded storage device. data processing system.