JPH03144756A - Method for arbitrating bus using right - Google Patents

Abstract

PURPOSE:To almost uniformly allocate the acquisition right of bus using right to respective bus masters by applying the acquisition right from a bus master positioned on the downstream of a bus master cancelling bus using right after previously acquiring the bus using right in the case of arbitrating a new bus using right. CONSTITUTION:When any one of bus masters 51 to 53 requests bus use, a system bus controller 50 simultaneously outputs a bus using right permission available signal to all the bus masters 51 to 53. When the bus master storing bus using right acquisition history receives the bus using right permission available signal, the bus master erases the bus using right acquisition history and transfers the bus using right permission available signal to its lower bus master. Thereby, the bus master generating a bus using request and then receiving the bus using right permission available signal can acquire the bus using right. Consequently, deflection allowing only the specific bus master out of the plural ones 51 to 53 to easily acquire the bus using right can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus usage right arbitration method for arbitrating bus usage rights requested by a plurality of bus masters.

(Prior Art) In a computer system in which a bus is shared by a plurality of bus masters, the bus master starts using the bus after acquiring the right to use the bus. The bus master needs to request the right to use the bus in advance before acquiring the right to use the bus. After requesting the right to use the bus, the right to use the bus can be obtained by receiving permission to use the bus.

Now, each bus master is given a priority order for use of the bus, and consideration has been made so that a bus master with a higher priority order can acquire the right to use the bus more quickly. The method of arbitrating bus use, that is, arbitrating for acquisition of the right to use the bus in consideration of the priority order, will be referred to herein as the bus right arbitration method.

FIG. 2 is a block diagram of a conventional bus right arbitration method.

The figure shows a motherboard 2 configured with a system bus 1, and a system bus controller 10 that arbitrates the right to use the bus. And three bus masters 11.12.13 are shown.

Each bus master is provided with an arbiter 15, 16, and 17 that controls system bus usage requests (bus usage rights requests).

System bus controller 10 and bus master 11.1
2.13 is connected to system bus l.

Arbiters 15, 16.17 have each bus master 11.1.
The system bus request signal (bus usage right request signal) BR, generated in 2.13. , BR201BR30, and the system bus use signal (bus use right acquisition signal) BBSYIO, BBSYIO that is output when the right to use the bus is acquired.
, BBSYso are input. These BRIo,
B Rto, B Rso and BBSY+o, B
BSYzo.

BBSY3゜ is BRI, BRz, BR3 respectively.
They are output to the system bus 1 as BBSY+, BBSYz, and BBSYs.

BRI, BR2, BRs and BBSY+, BBS
Y2.

BBSY3 is wired-ORed on system bus l, and BR, BB are connected to system bus controller lO.
Entered as SY.

Now, the system bus controller 10 sends a bus permission signal (bus permission permission signal) BG in response to BR.
Outputs OUT to system bus l. This BGo
ut is input to the arbiter 15 of the bus master 11 as BGIN+. If the arbiter 15 does not take in this BGI□, it outputs it to the system bus l as BGoutl. This BGout is sent to the arbiter 16 of the 7 bus master 12 as BGf. Close and input. This BGtx
If the arbiter 16 does not take in z, BGout
output to system bus 1 as This BGou
i* is B G 18 to arbiter 17 of 5 bus master 13
Enter as 3.

In this way, BGOUT is the system bus controller 10
A computer system system in which data is sequentially transferred from bus master 11, 12, 13 to bus master 11, 12, 13 is called a daisy chain system.

By the way, if BRl, BRz, and BRs are output in advance, each arbiter 15.16.17 outputs B G +s+
, B G tsz , B G Xns,
It outputs BBSYl, BBSYs, BBSYs to acquire the right to use system bus l, and executes processing using system bus l.

Here, the operation of the conventional bus right arbitration method will be explained with reference to FIGS. 3 and 4. Here, a case where only the bus master 11 outputs a bus right request (BRI) will be described.

3 is a flowchart of the arbiter 15, and FIG. 4 is a flowchart of the system bus controller 10.

First, in FIG. 3, the arbiter 15 is BRI.

is on or off (step Sl)
If this result is on, B
Turn on RI (step S2), then turn on BGIN
It is determined whether it is on or off (step S3). If this result is off, step S3 again
is executed.

Now, moving to FIG. 4, the system bus controller 10 constantly monitors whether the BR is on or off (step 511). If this result is off, step Sll is executed again. Now, when BR is turned on, the result of step Sll is turned on and step S12
Move to. In step S12, it is determined whether BBSY is on or off. If this result is on,
Step S12 is executed again. Also, if the result is off, turn on BG,... (step 513)
, Then, it is determined whether BBSY is on or off (step 514).

If the result is OFF, step S14 is executed again.

As a result, the result of step S3 in FIG. 3 is turned on,
Turn on BGIO (step S4).

Then, BBSYl (BBSYt.) is on, BR, (
BRI. ) is off (step S5).
).

If the result is NO, step S5 is executed again.

Further, if the result of step S5 is YES, BRI, B
Gs. is turned off (step SS), and the process returns to step Sl.

Now, as a result of step S6, step S in FIG.
In step 14, the result is turned on, BGOUT is turned off, step 515), and the process returns to step Sll. In addition, B.G.
By turning off OLIT, BGINI will inevitably
is also turned off.

Now, BR, which is input to the arbiter 15. is off,
The result of step S1 in FIG. 3 is OFF. In this case, the arbiter 15 determines whether B G INI is on or off (step S7). If the result is off, the process returns to step S1. Also, if the result is on, B
Turn on Gout+ (step S8), BGlN
It is determined whether I is on or off (step S9). If the result is on, step S9 is executed again. If the result is off, BGOIJTl is turned off (step 5IO) and the process returns to step S1.

As described above, the bus master 11 acquires the right to use the bus, and if it has not requested the right to use the bus, it transfers the bus right permission signal to other consecutive bus masters (bus master 12, etc.).

Note that the operation described in FIG. 3 is also executed for the bus master 12. Regarding Bus Master 13,
The processes of steps 87 to S10 are omitted, and if the result of step S1 is OFF, a predetermined error process is executed.

By the way, in a case where only the bus master 12 outputs the bus right request signal BRz, for example, in FIG.
From step Sl to step S7, step S8
The following steps are executed, and the bus master 12 acquires the right to use the bus. The operation when the bus master 12 acquires the right to use the bus is the same as the procedure shown in step 5l-36. The same applies to the bus master 13 as well.

Now, in the bus use right arbitration method described above, for example, bus master 11 and bus master 12 simultaneously perform BRI and BRI.
Suppose that R2 is output (execution of step S1). In this case, in the system bus controller IO, B
When R is turned on, BGOUT is turned on. This BGout is input to the arbiter 15 as BG xs+. As a result, the bus master 11 selects BBSY,
The right to use the bus is acquired by turning on B Rl and turning off B Rl. At this time, since the arbiter 15 takes in BGlNI, it does not turn on BGout+. Therefore, the bus master 16 continues to turn on BRa and requests the right to use the bus.

When the bus master 15 relinquishes the right to use the bus, that is, turns off the BBSYs, the system bus controller 10
Output u〒 again. This BGout is arbiter 15
Enter it as BGINI in , but do not import it into BGoty
Turn on t+. As a result, the BG of bus master 16
By turning on fN2 and taking in this signal, the right to use the bus can be acquired.

(Problem to be Solved by the Invention) According to the conventional bus use right arbitration method as described above, when a bus use right is requested from a plurality of bus masters, the bus use right that has a higher priority and is closer to the system bus controller 10, i.e. For example, if bus masters 11 and 13 request the right to use the bus at the same time, the bus master 11 acquires the right to use the bus. It is assumed that after that, while the bus master 11 is acquiring the right to use the bus, the bus master 12 requests the right to use the bus. At this time, there are two bus masters, bus masters 12 and 13, requesting the right to use the bus. bus master 1
If the bus master 1 relinquishes the right to use the bus, the bus master 12, not the bus master 13, can acquire the right to use the bus next time. In this way, the priority is fixedly assigned based on the physical positional relationship on the system bus 1, so a bus master with a low priority and located far from the system bus controller 10, that is, located downstream, acquires the right to use the bus. A difficult problem arose.

In addition, in order to solve the problems that have occurred in the daisy chain computer system, between the system bus controller 10 and each bus master 11, 12, 13,
There is a method of individually transmitting a bus right request signal and a bus right grant signal. In this case, the acquisition of the right to use the bus is not biased towards a particular bus master, but the number of signal lines for system bus 1 increases as the number of bus masters increases.
For example, there is a problem that the motherboard 2 becomes large and it becomes difficult to secure a space for its installation.

The present invention has been made with attention to the above points, and eliminates the bias in which only a specific bus master can easily obtain the right to use the bus, as in the case of the daisy chain system, and furthermore, the number of signal lines for the system bus is significantly increased. The purpose of this invention is to provide a bus usage right arbitration method that does not cause such problems.

(Means for Solving the Problems) The bus use right arbitration method of the present invention is such that when a system bus controller arbitrates the bus use rights of a plurality of bus masters connected in a daisy chain, the system bus controller arbitrates any of the above-mentioned rights immediately after system startup. When there is a bus usage request from a bus master, a bus usage permission signal is transferred from the bus master located most upstream of the bus to the bus master located downstream, and the bus master that made the bus usage request While acquiring the right to use the bus, the bus master in question saves the history of acquiring the right to use the bus, and if any of the above-mentioned bus masters subsequently makes a request to use the bus, the system bus controller simultaneously grants the right to use the bus to all the above-mentioned bus masters. The bus master that outputs the permission valid signal and stores the bus usage right acquisition history receives the bus usage right permission valid signal, erases the bus usage right acquisition history, and transmits the bus usage right permission signal to the downstream bus master. The bus master transmits the bus use request to the bus master and controls the bus master, which receives the bus use permission signal, to acquire the bus use right next time.

(Operation) In the above method, first, when a bus use request is received from any bus master immediately after the system is started up, a bus permission permission signal is sent from the bus master located most upstream of the bus to the bus master located downstream. Transfer towards.

As a result, the bus master who made the bus use request acquires the right to use the bus, and at the same time saves the history of acquiring the right to use the bus. After that, when any of the bus masters makes a bus use request, the system bus controller simultaneously outputs a bus use permission valid signal to all the bus masters. When the bus master that has stored the bus usage right acquisition history receives the bus usage right permission valid signal, it erases the bus usage right acquisition history and transfers the bus usage right permission signal to the downstream bus master. As a result, the bus master that has issued the bus use request and received the bus use right permission signal can acquire the next bus use right. In this case, the bus right permission signal is not output from the system bus controller, but from the bus master that stores the bus right acquisition history and performs the process of erasing it.

(Embodiment) FIG. 1 is a block diagram relating to the bus right arbitration method of the present invention.

The figure shows a motherboard 2 on which a system bus 1 is configured, a system bus controller 50 that arbitrates the right to use the bus, and three bus masters 51, 52, and 53.

The system bus controller 50 is provided with initial allocation storage means 61 and initial allocation setting means 62.

Each bus master is provided with an arbiter 55, 56, and 57 that controls system bus usage requests (bus usage rights requests). In addition, each arbiter 55, 56, 57 has
Bus use storage means 63a, 63b, 63c and bus use permission transfer means 64a, 64b, 64c are provided, respectively.

System bus controller 50 and bus master 51.5
2.53 is connected to system bus 1.

The arbiters 55, 56.57 have each bus master 51.5.
System bus request signal (bus usage right request signal) generated in 2.53 B R10, B R2°.

B.R. and a system bus use signal (bus use right acquisition signal) BBSYs that is output when the right to use the bus is acquired.
. , BBSY,. , BBSYs. is input. These B Rto, B Rao, B Rso and BBSY+o, BBSYzo.

BBSY3° is BR+, BRa, BR3, respectively.
.

They are output to the system bus l as BBSY+, BBSY2, and BBSYs.

BR+, BR2, BRs and BBSY+, BBS
Y2゜BBSYs are wired-ORed on the system bus l, and the BR is connected to the system bus controller 50.
, BBSY.

Now, the system bus controller 50 outputs a bus use permission valid signal (bus use right permission valid signal) BG to the system bus 1 as a response to the BR. This BG
is the arbiter 55, 5 of each bus master 51, 52, 53.
Enter 6.57.

The system bus controller 50 further outputs a bus permission signal (bus permission permission signal) BGouy to the system bus 1.

This BGout is input to the arbiter 55 as BGINII.

If the arbiter 55 does not take in this BGINII, it outputs it to the system bus l as BGoufull. This BGoutsl is input to the arbiter 56 of the bus master 52 as BGrssz. This BGINII
If the arbiter 56 does not take in □, BGouts
A is output to the system bus l. This BGo
uysx sends BGIN to the arbiter 57 of the bus master 53.
Enter as II3. This BG, □, is the arbiter 57
If it is not taken in, it is output to the system bus 1 as BGoutss. This BGouttb3 is input to the 7-bit 55 of the bus master 51 as BG output.

Now, the initial allocation storage means 61 of the system bus controller 50 consists of a register etc. that stores whether or not BGout is output immediately after the system starts up. After the BGout is output, the content "1" is stored. The initial allocation setting means 62 responds to the BR by
When outputting Gout and BG, if the content of the initial allocation storage means 61 is "0", BG is output together with B Gout, and the content of the initial allocation storage means 61 is "l".
In this case, it consists of a gate circuit or the like that performs control to output only BGout.

Bus usage storage means 63 of each bus master 55, 56, 57
a, 63b, and 63c are registers that store the history of whether or not the right to use the bus has been acquired; for example, the content is "0" at reset, the content is "1" when the right to use the bus is acquired, and B G outsa B G out
When outputting sa*B G 0UTIIS, the content "O" is stored again.

The bus use permission transfer means 64a, 64b, and 64c are bus use storage means 63a and 63b, respectively.

Writing to and reading from 63c, as well as B Gouou
It consists of a processor, etc. that controls the output of the TSAB Goutss. Specifically, first, in the case of acquiring the right to use the bus, the content "1" is written to the bus usage storage means, and when the BG is input, the content of the bus usage storage means is read and the content is set to 1. In the case, B G oc+t@tB GouTsz * B
At the same time as Gou and rss are output, control is performed to write the content "O" into the bus-using storage means.

By the way, if BR, BR, BR3 are output in advance, each arbiter 55, 56, 57 outputs B G fssl.
l B G 1811218 G tsss is taken in,
It outputs BBSYI, aasys, and BBSY3 to acquire the right to use system bus l, and executes processing using system bus l.

Now, an outline of the bus use right arbitration method of the present invention in the above configuration will be explained.

First, when starting up the system, the initial allocation storage means 61,
Bus usage storage means 63a, 63b.

63c is reset. That is, it is in an off state with the content "O".

Here, for example, assume that the bus master 51 turns on the BRI. The system controller 50 recognizes that BR is turned on. And initial allocation setting means 62
reads the contents of the initial allocation storage means 61. In this case, the content is "O".

Therefore, the initial allocation setting means 62 determines that the BR is turned on for the first time after startup, and at the same time performs the initial allocation process, stores the content "1" in the initial allocation storage means 61, that is, the content indicating that the initial allocation has been completed. Write, specifically, BG
and turn on BGout. Thereby, each bus master 51, 52, 53 recognizes that BG has been turned on. Furthermore, the bus master 51 recognizes that BGzHs+ has been turned on together with BG.

The permission transfer means 64a of the arbiter 55 first receives that BG is turned on, and then judges whether BR. If 0 or more conditions for recognizing that there is no history of acquisition of the right to use the bus with the content "O" are met, the bus master 51 turns on BBSY and acquires the right to use the bus. Note that the bus use permission transfer means 64a stores the history of bus use right acquisition, that is, the content "l", in the bus use storage means 63a at the same time that BBSY+ is turned on.
Write.

Next, the bus master 51 relinquishes the right to use the bus, and the bus masters 51 and 52 each issue a BR again.

Assume that BR2 is turned on. This recognizes that the BR of the system bus controller 50 has been turned on.

In this case as well, the initial allocation setting means 62 turns on the BG and reads the contents of the initial allocation storage means 61 as in the previous explanation. In this case, since the content of the initial allocation storage means 61 is "1", the system bus controller 50
Leave BGout off. Here, bus master 5
When the bus use permission transfer means 64a of No. 1 recognizes that only BG is on, it reads the contents of the bus use storage means 63a. In this case, since the content of the bus use storage means 63a is "1", BGoutss is turned on and output. Thereafter, in response to the BG being turned off, the bus use permission transfer means 64a stores the content "O" in the bus use storage means 63a.
”.

On the other hand, the bus master 52 has BG and BG1N! 12 are both turned on, and the bus master 51 acquires the right to use the bus in the same way as it acquired the right to use the bus first.

The present invention will now be described in detail with reference to FIGS. 5 and 6.

FIG. 5 is a flowchart of the system bus controller 50 according to the present invention.

First, it is assumed that the system bus controller 50 has completed startup and the contents of the initial allocation storage means 61 have been reset, that is, the contents have been set to "O". In other words, the initial allocation has not been made immediately after startup (
Step 521).

Here, the system bus controller 50 continues to monitor whether BR is on or off (step 522). If the result is off, it executes step S22 again. Also, if the result is on, BB
Determine whether SY is on or off (step 523). If the result is on, that is, if the right to use the bus has been acquired by any bus master, step S23 is executed again. As a result of waiting for the right to use the bus to be relinquished, in step S23, when off is detected,
The initial allocation setting means 62 turns on the BG and outputs it (
Step 524), and further the initial allocation setting means 62:
The contents of the initial allocation storage means 61 are read and it is determined whether the initial allocation has been completed (step 525). If the result is that the initial allocation is unallocated, BGOUT is turned on and output (step 526), and it is further determined whether BBSY is on or off (step 5).
27) If the result is OFF, execute step S27 again. If the result is on, BGo
The content "1", ie, the content indicating that the initial allocation has been completed, is written in the initial allocation storage means 61 (step 529), and the BG is turned off (step 530), and the process returns to step S22.

If the result of step S25 is completed, it is determined whether BBSY is on or off (step S53).
1), if this result is on, step S30
Move to. If the result is OFF, step S31 is executed again.

Next, the operation of the arbiter 55 will be explained using FIG.

FIG. 6 is a flowchart of arbiter 55 according to the present invention.

First, it is assumed that the arbiter 55 has completed its startup and the contents of the bus use storage means 63a have been reset, that is, the contents have been set to "O" (step 551).

In the figure, the arbiter 55 determines whether B Rt o is on or off (step 552), and if the result is on, turns on BRt for the system bus l (step 553). After that, it is determined whether BG is on or off (step 554).
If the result is OFF, step S54 is executed again.

When the result of step S54 turns on, the bus use permission transfer means 64a determines whether the contents of the bus use storage means 63a are on or off, that is, whether the contents are "1" or "O" (
step 555), in this case bus usage storage means 63a
is off.

Therefore, the process moves to step S56. In step S56,
It is determined whether BGxsst is on. If the result is OFF, step S56 is executed again. If the result is on, BG, , is turned on (step 557). And BBSYI (BB
It is determined whether SYI o) is on and BRt (BRto) is off (step 358).

If the result is NO, step 358 is executed again. Further, if the result of step S58 is YES, BRt
, BG, 0 off (step 559), and further B
Determine whether BSYt is on or off (
step 560). If the result is ON, step S60 is executed again. When BBSYI is set to OFF, the bus use permission transfer means 64a turns on the bus use storage means 63a, that is, writes the content "l" (step S
61), the process returns to step S52.

Now, if the result of step S55 is on, B G ,
uT, , is turned on and output (step 562). Further, it is determined whether BGIN 51 is on or off (step 563). If the result is on, B G t. is turned on (step 564).

Then, it is determined whether BBSYIo is on and BRIo is off (step 565). If the result is NO, step S65 is executed again. Also step S
If the result of 65 is YES, BR,.

B G 0UTIII I B G to is turned off (step 566), and it is further determined whether BBSY r is on or off (step 567). If the result of step S67 is on, step S67 is performed again.
Execute. When BBSYI is set to OFF, the bus use permission transfer means 64a turns on the bus use storage means 63a, that is, writes the content "1" (step 568), and returns to step S52.

If the result of step S63 is off, it is determined whether BG is on or off (step 589).

If this result is ON, the process moves to step S63.

If the result is off, turn off BGou Ding Step 5
70) Turn off the contents of the bus usage right storage means 63a, that is, write the contents "O" (step 571), and step S
Moving on to 56.

Now, if the result of step S52 is off, it is determined whether BG is on or off (step 572). If the result is OFF, the process returns to step S52. If the result is on, it is determined whether the contents of the bus use memory 63a are on or off (step 573). If the result is on, BGOUTBI is turned on and output is performed (step 574), and whether BG is on or not. It is determined whether it is off (step 575), and if the result of step S75 is on,
Step S75 is executed again.

If the result is off, turn off BGoutst (step 576), turn off the bus use storage means 63a, that is, write the content "0" (step 577), and step S
Moving on to 52.

If the result of step S73 is off, it is determined whether BGINSl is on or off (step 378). If this result is on, BG, UT, etc. are turned on (step 579), and whether BGrws+ is on or off. A determination is made (step 580). If the result is ON, step S80 is executed again. If this result is off,
Turn off BGouts+ (step 581) and return to step S52. Further, if the result of step 378 is off, it is determined whether BG is on or off (step 58
2). If this result is on, the process returns to step 378. Further, if the result is OFF, the process returns to step S52.

As described above, the bus master 51 acquires the right to use the bus, and if the bus use memory 63a is on, the BGo
Other consecutive bus masters (bus master 1
2) transfers the bus right permission signal to

Note that the operation explained in FIG. 5 is also executed for bus masters 12 and 13.

The present invention is not limited to the above embodiments.

In the embodiment, a case has been described in which three bus masters are connected to the system bus 1, but the number is not particularly limited.

(Effects of the Invention) The bus use right arbitration method of the present invention described above, when arbitrating a new bus use right, transfers the acquired right to the bus master downstream of the bus master who first acquired the bus use right and then relinquished it. Since the bus master located at the system bus controller gives the right to use the bus, it is possible to avoid a situation where a bus master close to the system bus controller can easily obtain the right to use the bus. That is, since the priority of each bus master changes each time the right to use the bus is relinquished, each bus master can be given the right to acquire the right to use the bus almost equally. Furthermore, since the number of control lines constituting the system bus does not increase as the number of bus masters increases, the size of the motherboard or the like on which the system bus is provided does not increase.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the bus right arbitration method of the present invention, FIG. 2 is a block diagram of the conventional bus right arbitration method, FIG. 3 is a flowchart of the arbiter, and FIG. 4 is a flowchart of the system bus controller. , FIG. 5 is a flowchart of the system bus controller according to the present invention, and FIG. 6 is a flowchart of the arrangement according to the present invention. 50...System bus controller, 51.52.5
3-... Bus master, 61... Cultivation season allocation storage means, 62... Initial allocation setting means, 63a, 63b, 63c... Bus use storage means, 64
a, 64b, 64C--Bus use permission transfer means.

Claims (1)

[Scope of Claims] When the system bus controller arbitrates the right to use the bus among a plurality of bus masters connected in a daisy chain, when a bus use request is received from any of the bus masters immediately after the system starts up, A right permission signal is transferred from the bus master located most upstream of the bus to the bus master located downstream, and the bus master that made the bus use request acquires the right to use the bus, while the bus master is not allowed to use the bus. After the right acquisition history is saved, if any of the above bus masters requests to use the bus,
The system bus controller simultaneously outputs a bus use right permission valid signal to all the bus masters, and the bus master that has stored the bus use right acquisition history receives the bus use right permission valid signal and outputs the bus use right acquisition history. and transmits the bus use right permission signal to the downstream bus master, so that the bus master that issues the bus use request and receives the bus use right permission signal acquires the bus use right next time. A bus use right arbitration method characterized by: