JPH03144491A - Image display device - Google Patents

Abstract

PURPOSE:To minimize a flicker of a screen by generating an update address at a writing speed lower than a reading speed corresponding to a screen scanning speed when contents in a frame buffer are updated. CONSTITUTION:The device is provided with an update address generating means 3 which generates the update address at the writing speed lower than the reading speed corresponding to the scanning speed of the screen 7 when contents in the frame buffer 5 are updated. Consequently, a display address inherent in a pixel skipped by the update address is not generated but the most approximate update address smaller than that inherent in the skipped pixel is generated for the display address. Thus, a synthetic screen emerging time and screen flickering can be minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display device, and more particularly to an image display device that can instantly switch from an old image to a new image.

[Prior Art] The operation of a conventional image display device when switching images will be described with reference to FIG.

A period 5a-Sd in FIG. 5 is a period in which a display address Da is generated in order to sequentially read image data from the frame buffer from the first pixel to the last pixel on the screen, and the generation speed, that is, the readout speed is It depends on the scanning speed of the screen. When the display address corresponding to the last pixel is reached, the display returns to the display address corresponding to the first pixel. Then, after the vertical retrace time has elapsed, generation of the display address Da is started again.

Screens Ga-Gd are examples of screens at the end of each period 5a-3d.

The screen is scanned from left to right and top to bottom, so the top left pixel is the first pixel and the bottom right pixel is the last pixel.

The period R is a period in which an update address for updating the contents of the frame buffer is generated, and starts from time t1, reaches the address of the last pixel at time t2, and
The update has finished. The update address generation speed, that is, the write speed, is lower than the write speed of the frame buffer.

- Since the writing speed in the membrane is slower than the reading speed, the image of the opening is partially synthesized before the transition from the old screen Ga to the new screen Gd, as shown in FIG. The screen GbGc on which the synthesized image is displayed is sandwiched between the images. The larger the speed difference, the longer the total time for the composite image to appear.

As a method for minimizing the time during which a composite image appears without depending on the speed difference, as shown in FIG. 6, a pair of frame buffers FA and FB are prepared, and frame buffer F
There is one that reads and displays the old image stored in A, writes a new image to the frame buffer FB, and when the writing is finished, switches the switch Sw to read and display the new image from the frame buffer FB. .

In this case, the screen Ga remains as it is during periods Sb and 5cSd shown in FIG. 5, and after time t2, when the display address returns from the last pixel to the first pixel, the switch Sw is switched and the next New screen Gd when scanning the screen of
It will be switched to.

[Problems to be Solved by the Invention] In the switching as shown in FIG. 5, the appearance time of the composite image becomes long, so there is a problem in that the screen flickers.

On the other hand, in the method of switching between a pair of frame buffers as shown in FIG. 6, the screen flicker can be minimized, but there is a problem in that it requires twice the memory capacity. Another problem is that there is a time delay before a new screen is displayed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image display device that can suppress screen flickering to a minimum, does not require twice the memory capacity, and does not cause a time delay until displaying a new screen. It is about providing.

[Means for Solving the Problems] According to the first aspect, the image display device of the present invention reads out and displays the contents of the frame buffer by reading out the display address at a reading speed that matches the scanning speed of the screen. display address generation means that repeatedly generates a display address; an update address generation means that generates an update address at a write speed slower than the read speed when updating the contents of the frame buffer; The display address is increased by 1 pixel from pixel to the last pixel, and the update address is also increased by 1 pixel, and when the display address is about to overtake the update address while increasing. generates the update address by several pixels at a time up to the last neighborhood or the last pixel so that the update address reaches the last neighborhood or the last pixel earlier than the display address reaches the last pixel. In addition, the display address generating means and the display address generation means are configured to generate, as a display address, the most correctly existing update address smaller than the original display address of that pixel for a pixel in which the update address skips. The configuration is characterized in that it includes address generation control means for controlling update address generation means.

According to a second aspect, the image display device of the present invention provides a display address that repeatedly generates a display address at a read speed that matches the scanning speed of the screen in order to read and display the contents of the frame buffer. When updating the generation means and the contents of the frame buffer, the update address is increased by several pixels at a time so that the update address reaches from the first pixel of the screen to the last pixel or the last pixel in less than the scanning time of one screen. Generate addresses for
Next, update address generating means generates an update address for the entire screen by repeatedly generating update addresses intermittently in the same manner as described above so as not to overlap with previously generated update addresses, and a frame; When updating the contents of the buffer, the update address that is smaller than the original display address of that pixel and that exists most is generated as the display address for the pixel where the update address skips. The present invention is characterized in that it includes address generation control means for controlling the display address generation means.

[Operations] In the image display device of the present invention according to the first aspect, during the period in which the display address increases from the first pixel to the last pixel, both the display address and the update address are initially increased by one pixel. However, when the display address or the update address is about to overtake the display address or the update address, the update address increases rapidly until it reaches the last neighborhood or the last pixel, and the last neighborhood or last pixel is reached faster than the display address. pixels.

At this time, the display address does not generate the original display address of the pixel that has been skipped by the update address, but instead is the smallest and smallest address that is smaller than the original display address of the skipped pixel. Generate a nearby update address.

As a result, everything before the pixel where the display address is about to overtake the update address has been changed to a new image, and everything after that pixel has been stretched and interpolated and changed to a new image. It turns out.

Therefore, the appearance time of the composite screen is minimized, and screen flickering is suppressed to a minimum. Furthermore, the memory capacity is sufficient for one screen. Furthermore, the display of the new image will not be delayed until all the contents of the frame buffer are updated with the data of the new image.

In the image display device of the present invention according to the second aspect, at the time of updating, the update address is increased at random, and frames are jumped from the first pixel of the screen to the last pixel or the last pixel in a time less than the scanning time of one screen. Update the contents of the buffer. Then, in the same manner as above, update addresses are generated intermittently and the contents of the frame buffer are updated, while making sure that they do not overlap with those previously updated, and finally the entire contents of the frame buffer are updated. On the other hand, display addresses are generated repeatedly by increasing the display address by one pixel at a reading speed that matches the screen scanning speed, except when updating, and when updating, pixels whose contents have already been updated are displayed. The original display address of the unupdated pixel is not generated, but instead, the update address that is smaller and closest to the original display address is generated as the display address. .

As a result, when updating, the image is immediately expanded and interpolated to become a new image, and the number of interpolated pixels gradually decreases until a complete new image is displayed.

Therefore, the appearance time of the composite screen is minimized, and screen flickering is suppressed to a minimum. Furthermore, the memory capacity is sufficient for one screen. Furthermore, the display of the new image will not be delayed until all the contents of the frame buffer are updated with the data of the new image.

[Example] Hereinafter, the present invention will be described in more detail based on the example shown in the drawings. Note that this invention is not limited to this.

In the image display device 1 according to the embodiment of the present invention shown in FIG. 1, the control unit 2 receives image data from the CPU 10 and passes it to the frame sofa 5. Also, C
A control signal 12 is output based on the instruction from PU10 and timing information from the timing controller 4 to control the address generation control section 3.

The timing controller 4 generates synchronization signals 14 such as a horizontal synchronization signal, a vertical synchronization signal, and a pixel clock for display on the CRT 9, and sends them to the address generation control section 3 and the CRT interface 6. Also, as mentioned above,
Send timing information to the control section 2.

The address generation control unit 3 generates a display address and a control signal (hereinafter referred to as a display address, etc.) 16 based on the synchronization signal 14, and outputs it to the frame buffer 5. Also, based on the control signal 12 from the control unit 2, an update address and control signal (hereinafter referred to as update address etc.) 18 for updating the contents of the frame buffer 5 are generated and output to the frame buffer 5. do. The details will be described later with reference to FIG.

The frame buffer 5 has a write port and a read port independently, and can perform writing for updating and reading for display independently.

A CRT interface 6 receives a synchronization signal 14 from the timing controller 4 and the frame buffer 5.
A video signal is generated based on the image data output from the CRT 7 and is output to the CRT 7.

The CRT 7 displays images based on the video signal.

Next, FIG. 2 is a block diagram showing details of the address generation control section 3. As shown in FIG.

The control timing generator 2■ is based on the synchronization signal 14 from the timing controller 4, and the address controller 22
and controls the timing of the operation of the address etc. output section 23.

The address control unit 22 controls the address generation operations of the display address generation unit 30 and the update address generation unit 40.

Next, the operation will be explained step by step with reference to FIG.

First, in the period Sa shown in FIG. 3, rlJ is set in the display increase width register 35, and the original display address of the first pixel is set in the display initial value register 36.

The display address controller 31 transfers the value of the display initial value register 36 to the display address etc. output unit 32 via the display multiplexer 33 in order to display the first pixel. Then, the adder 34 adds the display address of the first pixel set in the display address register 32 and the increment width "1" set in the display increment width register 35 to the multiplexer. 33, the display address register 32 is recursively set at a predetermined timing. In the same way, the display address is "1"
It will increase gradually. This display address is output from the address etc. output section 23 to the frame buffer 5 as the display address etc. 18.

The address control section 22 suppresses the output of the update address from the address etc. output section 23 when not updating.

At the start of the update, “1” is set in the update increment width register 45.
is set, and the original display address of the first pixel is also set in the update initial value register 46. Then, the update address controller 41 first sets the value of the update initial value register 46 to the update address register 42 via the update multiplexer 43. As a result, the address etc. output unit 23 outputs the update address etc. 18 to the frame buffer 5. In addition, image data corresponding to the new image is sent from the CPU 10 in synchronization with the generation of the update address. Thus, the image data corresponding to the first pixel will be updated.

Next, the update address controller 41 writes the update address register 4 at a writing speed that is compatible with the frame buffer 5.
The adder 45 adds the value of 2 and the increment width "1" set in the update increment width register 45, and recursively sets it in the update address register 42 via the update multiplexer 43. Generate an update address for the pixel. Thereafter, the update address is incremented by "1" in the same manner.

In addition, in order to avoid conflicts between the display address and the update address, if the two seem to match, the address control unit 2
2 slightly delays the generation of the update address.

As described above, during the period Sa in FIG. 3, the old image is read out from the frame buffer 5 and displayed on the CRT 7 (screen Ga). On the other hand, the contents of frame buffer 5 are
The image data of the first pixel is updated halfway.

During period sb, the display address is r from the first pixel.
Since the image data is increased by lJ and the image data has already been updated from the first pixel to the middle, the new image will be displayed at the top of the screen.

Since the increase speed of the display address is faster than the increase speed of the update address, the display address catches up to and is about to overtake the update address in the middle of the period sb.

The control unit 2 controls vertical synchronization timing.

Based on the update start timing, the original display address of the pixel when the display address catches up with and is about to overtake the update address in the period sb is calculated. Then, the address control unit 22 is notified of the address.

When the address controller 22 reaches the notified address, it instructs the display address controller 31 to maintain the value of the display address register 32.

Further, a predetermined increase width is set in the display increase width register 35 and the update increase width register 45. This predetermined increment width is such that the update address can reach the original display address of the last pixel or the last pixel before the display address.

Therefore, as shown in a stepwise manner by broken lines during period sb in FIG. 3, the update address is increased by a predetermined increment width on the way. The timing at which the update address is increased is notified to the CPU 10 via the control unit 2, and the CPU 10 sends out the image data of the update address to the frame buffer 5 via the control unit 2 in accordance with the timing.

On the other hand, the display address controller 31 maintains the value of the display address register 32, but when the original display address of the pixel to be displayed matches the update address that has already been generated, the display register 32
The adder 34 adds the value held in the display increment width register 35 to the predetermined increment width held in the display increment width register 35, and sets the value in the display address register 32 via the display multiplexer 33. This matches the update address mentioned above. Then, the value of the display address register 32 is
The original display address of the pixel to be displayed is maintained until it matches the already generated update address next time.

In this way, the display address traces the update address as shown in the stepwise solid line during period sb in FIG.

As a result, as shown by screen Gb in FIG. 3, a new image is displayed up to the middle, and a new image that has been expanded and interpolated is displayed from the middle.

The periods Sc and Sd shown in FIG. 3 are also the same as above. Then, in the period Se, a complete new image screen Ge is obtained.

As understood from the above explanation, this image display device 1
According to the above, the old image is instantly switched to the new image, and the period during which a composite image in which the old image and the new image are partially composited appears is suppressed to a minimum. Therefore, flickering of the screen can be prevented. Furthermore, the capacity of the frame buffer is reduced, and there is no time delay in displaying a new image.

A modification of the above embodiment is to generate update addresses by skipping update addresses whose contents have already been updated.

Next, a second embodiment of the present invention will be described, and its basic configuration is the same as that shown in FIGS. 1 and 2 above. Therefore, the explanation of the configuration of each part will be omitted, and the fourth
See the diagram! Let's explain the operation.

As shown by the broken line R in FIG. 4, the update address is generated in multiple steps. In the first time starting from time tl, a predetermined value is set so that the update address reaches from the first pixel to the last pixel or the last pixel in a time less than or equal to the time it takes for the display address to reach from the first pixel to the last pixel. Update addresses are generated intermittently as the increase width increases. When the last pixel or the last pixel is reached, the next time, starting from the smallest original display address of the previously skipped pixel, update addresses are generated intermittently with a predetermined increment in the same way as the previous time. Then, by repeating this process, all the contents of the frame buffer 5 are updated.

On the other hand, regarding the display address at the time of the above update, the original display address of the pixel to be displayed is used from the first one screen scanning period after the update starts until the screen scanning period when the update ends. If it matches an already generated update address, its original display address is generated; if it does not match, the previous and closest update address is used as the display address. In other words, stretching interpolation is performed on pixels that have not been updated. The period 5b-3d in Fig. 4 is such a period, but as the number of update addresses that have already been generated increases, the portion that is stretched and interpolated gradually decreases, and the image gradually approaches a complete new image. I'm going to go.

Even in the second embodiment described above, exactly the same effects as in the first embodiment can be obtained.

[Effects of the Invention] According to the image display device of the present invention, an old image is instantly switched to a new image, and screen flickering can be prevented. In addition, the capacity of the frame buffer is small, and there is no time delay until a new image is displayed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the image display device of the present invention, and FIG. 2 is a block diagram of an embodiment of the image display device of the present invention. A block diagram of the irJ section, FIG. 3 is an explanatory diagram showing the operation of one embodiment of the present invention, FIG. 4 is an explanatory diagram showing the operation of another embodiment of the invention, and FIG. 5 is a conventional image display device. 3 and 6 are block diagrams showing another example of the conventional image display device. (Explanation of symbols) 1... Image display device 2... Control unit 3... Address generation control unit 4... Timing controller 5... Frame buffer 6... CRT interface 7... CRT 10.・CPU21・・
Control timing generation section 22... Address control section 23... Address etc. output section 30... Display address generation section 40... Update address generation section.

Claims (1)

[Claims] 1. Display address generation means for repeatedly generating display addresses at a reading speed matching the screen scanning speed in order to read and display the contents of the frame buffer, and updating the contents of the frame buffer. update address generating means for generating an update address at a write speed slower than the read speed; and at the time of update, the display address is increased by one pixel from the first pixel to the last pixel on the screen. At the same time, the update address is increased by 1 pixel, and when the display address is about to overtake the update address while increasing, the update address is updated faster than when the display address reaches the last pixel. The update address is generated at intervals of several pixels up to the last neighborhood or the last pixel so that the update address reaches the last neighborhood or the last pixel, and for the pixel that the update address skips, the original address of that pixel is generated. address generation control means for controlling the display address generation means and the update address generation means so as to generate an update address that is smaller and closest to the display address of the display address as the display address; An image display device characterized by: 2. Display address generation means that repeatedly generates display addresses at a reading speed that matches the scanning speed of the screen in order to read and display the contents of the frame buffer; Update addresses are generated intermittently by incrementing by several pixels so that the update address reaches from the first pixel to the last pixel or the last pixel on the screen in less than 1 hour, and then an update address generation means for generating an update address for the entire screen by repeatedly generating update addresses intermittently in the same manner as described above and not overlapping with addresses; An address that controls the display address generation means so that, for a pixel whose update address has skipped, an update address that is smaller than the original display address of that pixel and is closest to that pixel is generated as a display address. An image display device comprising a generation control means.