JPH03144382A - Scan test system - Google Patents

Abstract

PURPOSE:To simplify an onboard scan test by switching all clocks of multiple phases to the same phase when a scan test is performed for an LSI. CONSTITUTION:When a scan that of an LSI 10 is executed on a substrate, a scan control section 30, first, inputs a test data into a serial input terminal SI of the LSI 10 to be tested. The scan control section 30 shifts a clock CLK to '1' by one period. When EXC='0', a phase control signal A is selected from a selector 25 to be supplied to a gate 27 as phase control signal of clock CLK-B. As a result, clocks CLK-A and CLK-B are outputted by one clock at the same timing to be supplied to clock input terminals CLKA and CLKB of the LSI 10. Under such a condition, the scan control section 30 shifts out a test data at a serial output terminal SO of the LSI 10 and the data is compared with an expected value to judge quality of the LSI 10.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a scan test method suitable for executing a scan test with an LSI with a scan test function mounted on a board. .

(Prior Art) In recent years, with the increase in the scale of LSIs, a scan test method has been introduced as a method to facilitate testing of LSIs. This scan test method, as shown in Figure 3,
All F//F (flip-flops) 31 inside the SI are connected as a shift register, and test data is set in each F/F 31 by a shift-in operation from the outside via the serial input terminal Sl of the LSI, and the system clock is set. is operated for one clock to set the data passed through the combinational circuit 32 to the next stage F/F 31, and then the data of each F/F 31 is sequentially read from the serial output terminal SO by a shift-out operation, and the expected value is set. The quality of the LSI is determined by comparing it with the actual quality of the LSI.

Now, in the above scan test method, the target LS
For example, when I uses two-phase clocks (CLK-A, CLK-B) supplied to clock input terminals CLKA and CLKB, in order to facilitate the creation of test data,
It is common to use a method in which two-phase clocks are connected externally and treated as clocks of the same phase. However, when the above-mentioned LSI is mounted on a board to configure a desired system, the scan test data created for testing the LSI alone cannot be used because the phases of the system clocks are different.

(Problems to be Solved by the Invention) As mentioned above, conventionally, when an LSI that has a scan test function and uses a multiphase clock is mounted on a board, the phase of the system clock is different, so the LSI alone cannot be used. It was not possible to use the scan data that was simplified to a 1-phase clock for testing, and the L
There was a problem that the SI scan test (onboard scan test) could not be performed. .

This invention was made in view of the above circumstances, and its purpose is to provide an L
To provide a scan test method that allows an SI scan test to be easily performed even when the SI is mounted on a board.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a method for generating the above-mentioned multiphase clock in a system having a board equipped with an LSI that has a scan test function and uses a multiphase clock. A clock generation circuit is provided that makes all multiphase clocks in phase during a scan test, and is mounted on the board using scan data for performing a scan test on an LSI alone using a single phase clock. The present invention is characterized in that it performs a scan test of the LSI that is being used.

(Function) According to the above configuration, the clock generation circuit generates the multiphase tarlock necessary for normal operation of the LSI during normal system operation. On the other hand, the above LSI
During a scan test operation for , the clock generation circuit switches each of the above clocks to clocks of the same phase. As a result, scan test data simplified to a one-phase clock can be used for a scan test of the LSI even after the LSI is mounted on a board.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. In the same figure, IO has a built-in scan test circuit (not shown) and a multiphase clock, for example, a two-phase clock CL.
In the normal state, the LSI 20 that uses K-A and CLK-B uses clocks CLK-A and CLK- that have different phases.
CLK-A during scan test.
.

Clock generation circuit that makes CLK-B in phase, 30 is LS
This is a scan control unit for controlling a scan test on the board (onboard scan test) for I10. The scan control unit 30 inputs/outputs scan test data for the serial input terminal SL and the serial output terminal SO of the LSI10, compares the output data from the terminal SO with an expected value, determines whether the LSI10 is good or not, and also controls the clock. The generator circuit 20 is controlled.

The LSI I0, the clock generation circuit 20, and the scan control section 30 are mounted on a board (not shown).

The clock generation circuit 20 includes an oscillator 21 that generates a clock CLK having twice the frequency of the system clock, an inverter 22 that inverts the level of the clock CLK from the oscillator 21, and further inverts the level of the output signal of the inverter 22. It has an inverter 23. The clock generation circuit 20 also includes a phase control signal generation circuit, for example, an F/ F (flip flop) 24
and one of the phase control signals φA and φB from the F/F 24 (Q output terminal, Q output terminal) is clocked CLK.
-B phase control signal is selected according to the switching signal EXC from the scan control section 30. The clock generation circuit 20 further includes an F/F
24 and the output enable signal ENA from the scan control unit 30, the gate 26 outputs the clock CLK as the clock CLK-A to the LSI10, and the phase control signal (φA) selectively output from the selector 25. or φB) and the above output enable signal ENA,
LSI10 with clock CLK as clock CLK-B
It has a gate 27 for outputting to the output terminal.

Next, the operation of the configuration shown in FIG. 1 will be explained with reference to the timing chart shown in FIG.

First, a clock CLK having twice the frequency of the system clock output from the oscillator 21 is passed through inverters 22 and 23 to a D-type F/F/2 that constitutes a phase control signal generation circuit.
It is supplied to the clock input terminal of F24. This F
The D input terminal of the F/F 24 is connected to the Q output terminal of the F/F 24. As shown in FIG. 2, phase control signals φA and φB having mutually different phases are output from the Q output terminal and Q output terminal of the F/F 24 in synchronization with the clock CLK.

The phase control signal φA from the F/F 24 is supplied to the gate 26 together with the clock CLK whose level has been inverted by the inverter 22 and the output enable signal ENA from the scan control section 30. Further, phase control signals φA and φB from the F/F 24 are supplied to the selector 25. The selector 25 receives a switching signal EX from the scan control section 30.
When C is “O”, phase control signal φA is selected and set to “1”.
', phase control signal φB is selected. The selection output signal of the selector 25 is the clock CLK whose level is inverted by the inverter 22 and the scan control unit 30.
It is supplied to the gate 27 together with the output enable signal ENA from.

Gate 26 receives phase control signal φA and output enable signal EN.
Both A and C clock CLK for a period of 11.
Clock input terminal CLKA of LSI10 as LK-A
Output to. Further, the gate 27 outputs the clock CLK as the clock CLK-B for a period of 1° so that both the selection output signal of the selector 25 and the output enable signal ENA are L S
It is output to the clock input terminal CLKB of Ito.

Now, during normal operation of the system, the scan control unit 30
Both the output permission signal ENA and the switching signal EXC are set to '1'. In the case of EXC-“1”, the phase control signal φB is selected from the selector 25, and the clock CLK-B
is supplied to the gate 27 as a phase control signal. As a result, clocks CLK-A and CLK-B having different phases are outputted from the gates 26 and 27 as shown in FIG. 2 in response to phase control signals φA and φB having different phases, respectively. This game) Clock CLK- from 28.27
A, CLK-B are clock input terminals C of LS110
It is supplied to LKA and CLKB, allowing normal operation of LSI10.

Next, when performing a scan test of the LSI10 on the board, the scan control unit 30 first
Input test data to serial input terminal Sl of LG. This test data is the same as scan data for performing a scan test on the LSI alone using a one-phase clock. Next, the scan control unit 30 sets the switching signal EXC to "0°" as shown in FIG.
Set NA to "1" for one cycle of clock CLK.

In the case of EXC-“0”, the phase control signal φA is selected from the selector 25 and supplied to the gate 27 as the phase control signal of the clock CLK-8. As a result, gate 28
．． From 27 onwards, the clock CLK-A.

CLK-B is the second in accordance with the phase control signal φA.
As shown in the figure, only one clock is output at the same timing, and clock input terminals CLKA and CLK of LSI10 are output.
B is supplied. This in-phase black, Tsuku CLK-A, C
When LK-B is generated for one clock, LSI10
Internally, the output of each F/F (corresponding to F/F 31 in Figure 3) is (corresponding to combinational circuit 32 in Figure 3)
Next stage F/F through combinational circuit (none shown)
latched to. In this state, the scan control unit 30
The test data is shifted out from the serial output terminal SO of I10, and the shifted out data is compared with an expected value to determine the quality of LSI10.

Note that in the embodiment, the clock CLK-A.

An explanation of the case where the phase control signal for the clock CLK-B is switched from the phase control signal φB with b in the clock CLK-B to the phase control signal φA specific to the clock CLK-Al in order to make the clock CLK-B the same phase. However, it is not limited to this. For example, the clock C supplied to the 4-tooth 27
A love story for LK-B.

By fixedly using the six-phase control signal φB specific to the clock CLK-B as a control signal, the gate 27 generates a clock CLK- whose phase is different from that of the clock CLK-A.
Output CLK-B or gate 2.
Clock/3CLK-A from B may be selected by a selector and supplied to the clock input terminal CLKB of LSI10 as the target clock CLK-B.

Further, in the above embodiment, an LSI using a two-phase clock
Although the present invention has been described with reference to an on-board scan test, the present invention is equally applicable to an on-board scan test for LSIs that use multiphase clocks for three or more phases.

[Effects of the Invention] As detailed above, according to the present invention, in a system including a board on which an LSI having a scan test function and using a multiphase clock is mounted, during a scan test targeting the LSI, Since all multiphase clocks are configured to be switched to the same phase, the scan test data simplified to l-phase locking can be used for scan tests of the same LSI even after the LSI is mounted on the board. , on-board scan tests can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation, and FIG.
The figure is a block diagram of the periphery of an LSI scan test circuit that uses multiphase clocks. 10...LSl, 20...Clock generation circuit, 21
...Oscillator, 24...F/F (phase control signal generation circuit), 25...Selector, 26.27...Gate, 3o...Scan control unit.

Claims (1)

[Claims] In a system having a board equipped with an LSI that has a scan test function and uses a multiphase clock, a clock generation circuit for generating the multiphase clock, which is configured to generate all the multiphase clocks during a scan test. A clock generation circuit is provided to make the multi-phase clocks of the multi-phase clocks in phase with each other, and a scan test of the LSI mounted on the board is performed using scan data for performing a scan test of the LSI alone using a single-phase clock. A scan test method characterized by the following.