JPH03143024A - Emitter follower circuit - Google Patents

Abstract

PURPOSE:To decrease the distortion of an emitter follower of a pre-stage connected to a comparator by connecting the emitters of transistors(TRs) of each emitter follower. CONSTITUTION:An analog input signal Vin is fed in common to bases of Tr1-Trn of an emitter follower placed at pre-stage of plural comparators 10-n of a parallel A/D converter and emitter of the Tr1-Trn are connected together. When the level of the comparators 10-n transits from a low to a high level, the reduction in the emitter level of the TRs at the pre-stage of plural comparators 10-n is compensated by the assistance of currents from adjacent TRs. Thus, distortion in vertical asymmetry or asymmetry at the start and the stop of the emitter is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an emitter follower circuit used before the input stage of a comparator of a parallel type analog-to-digital converter, and particularly relates to improvement of its high frequency characteristics.

<Prior Art> A brief explanation of a conventional parallel analog-to-digital converter is as follows. Analog value input voltage V,
n is simultaneously compared with different reference voltages by multiple comparators, and the outputs (binary output) of the multiple comparators are converted to a digital code (binary output) via an encoder.
(usually binary code). In this way,
It converts input analog voltage into digital.

In such a parallel analog-to-digital converter, an emitter follower circuit is usually used before each comparator. FIG. 6 shows a conventional example of this type, and FIG. 7 shows the detailed configuration of IV1. In FIG. It is. The comparator consists of transistors ``r11'' and ``12, and the emitters of both transistors are commonly connected.
It is connected to a constant current circuit CC via a switching transistor T13 which is turned on and off at . The emitter output of the transistor 'r1 of the emitter follower circuit is applied to the base of the transistor 1'11, and the reference voltage Vref2 is applied to the base of the other transistor 1'.

Note that the output of the comparator is normally latched by a latch circuit using a clock obtained by inverting the above clock, but since this is not directly related to such a latch circuit and its operation, illustrations and explanations are omitted here. .

In such a circuit, the switching transistor ′■'
13 is on, when the analog voltage V1゜ increases and the base voltage of the transistor 1'11 exceeds the reference voltage vref, the I transistor 11 turns on, and the transistor 1'11 is turned on from the emitter of the transistor Tr1. Current is injected into the base of transistor 11. A large base current is required when transistor 11 is turned on.

Conversely, when the analog human power V1o becomes low, the current is drawn from the base of the transistor T11.

<Problem to be solved by the invention> However, as the frequency of the analog input signal increases, even if the analog input signal V1n increases, the transistor
Since the current injected into the base of transistor 11 is not large enough, there is a problem that the timing at which transistors 1 and 11 turn on is delayed (the rise is slow).

That is, as shown in FIG. 8, the emitter follower [!
Even when a sine wave is input to the J circuit, the base voltage of the L transistor T11 becomes a waveform that is vertically asymmetrical or has an asymmetrical rise and fall, resulting in the problem of distortion.

SUMMARY OF THE INVENTION An object of the present invention is to provide an emitter follower circuit that can reduce distortion that is vertically asymmetrical or rises and falls asymmetrically.

Means for Solving the Problems> The present invention to achieve such objects is an emitter follower circuit provided in front of each of a plurality of comparators of a parallel type analog-to-digital converter, It is characterized in that an analog input signal is commonly applied to the base of each transistor, and the emitter of each transistor is connected.

By connecting the emitters of each transistor of the emitter follower, the comparator changes from LOW to HIG)
When the comparator transitions to i, the drop in the emitter potential of the transistor in the previous stage of the comparator is compensated for by the aid of current from the adjacent transistor.

<Example> The present invention will be described in detail below with reference to the drawings.

No. 11al is a top diagram showing an embodiment of the emitter follower circuit according to the present invention. In the figure, '■゛1.1゜T 'r, ,,T, is an emitter follower 1.r2'r3' transistor, and its base has an analog input voltage ■, in common. is given. Further, the emitters of each transistor are commonly connected and have the same potential. Note that the collector and emitter of each transistor are each connected to an appropriate voltage line via a resistor.

10.20. , , , n are comparators equivalent to the circuit shown in FIG. 7, and each comparator 10 receives the emitter output of each transistor of the corresponding emitter follower.

The operation in such a configuration will be explained. When the analog power V1n increases and the comparator 20 connected to point B (emitter of transistor Tr2) changes from LOW to HIGH, a large current is applied to the comparator 20.
Therefore, the potential of point H becomes lower than that of point A (emitter of transistor "'r1") and point C (emitter of transistors 1' and 3) on both sides.

However, in this case, current flows into point n from points A and C, causing the comparator 20 to become HIGH.
Transistor ``rl'''''r3 assists in this. This suppresses a drop in the potential at point B, and reduces T, which is vertically asymmetrical or asymmetrical between rising L and falling as seen in the conventional example.

When comparator 20 goes from LOW to 11G], other comparators go LOW or 4I
Since the state transitions do not occur simultaneously, the current change is smaller than that of the comparator 20, and the potentials at points A, C, , , X are equal to the analog input voltage V i! 2 obey.

In addition, the main part II! j is not limited to the configuration of the above embodiment, but can also be configured as follows.

■In Figure 1, each emitter is connected in common, but the second
As shown in the figure, each damper may be connected in series through a resistor. With such a configuration, it is possible to suppress the generation of fixed waves in the high frequency region.

■In Figure 1, point B is both 11T of points A and C! There is current assistance from I, but at point A, right old point B, and at point X, left f+!
The two points at both ends, where current assistance can only be obtained from the IJ point, have different conditions from the other points. To correct this,
As shown in Figure 3, dummy emitter followers' are installed at both ends.
V. , "rn+1" may be added.

(2) Emitters connected to each other are points corresponding to continuous reference voltages Vref, as shown in FIG.

However, if the analog input signal is high frequency, there is a limit to the speed of the comparator, so
Transition to H: Two or more 7 comparators may exist at the same time. These simultaneously transitioning comparators correspond to adjacent reference voltages Vref (eg, comparators 20 and 30 in FIG. 4). therefore,
In a high frequency region where multiple comparators transition at the same time, the continuous reference voltage Vro as shown in Figure 4.
Even if the emitter corresponding to f is connected, it becomes difficult to operate ideally as described above.

Therefore, two consecutive reference voltages V, as shown in FIG.

This can be prevented by arranging the comparators corresponding to ↓6 not consecutively but alternately.

That is, the reference voltage V, as shown in FIG. F is folded back instead of in a straight line, and the comparators are 10, n, 20
．． The comparators are arranged in the order of n-1, 30, . . . so that the comparators corresponding to consecutive reference voltages vref are not adjacent to each other.

Note that the present invention is not limited to these examples, and other configurations may be applied as long as the terminals of each transistor of the emitter follower are connected in some way on the circuit. It is possible.

<Effects of the Invention> As explained in detail above, according to the present invention, by connecting the dummy strands of the transistors of each dummy follower, one comparator in the parallel analog-to-digital converter can be changed from LOW to LOW. This has the effect of reducing the distortion of the preceding emitter follower connected to the comparator, which occurs when transitioning to f I G l-(.

[Brief explanation of the drawing]

FIG. 1 shows one implementation of an emitter follower circuit according to the present invention.
2, 3, and 5 are configuration diagrams of other embodiments of the present invention. FIG. 4 is a configuration diagram for explaining the relationship between the reference voltage and the comparator. A diagram showing an example of a conventional emitter follower circuit, FIG. 7 shows a detailed configuration of one stage of the conventional emitter follower circuit [
1. FIG. 8 is an explanatory diagram for explaining the distortion that occurs in the damper follower circuit. 1゛ Go'f'1.4"rn"'Emitter filter r11r2Ir3・Lower transistor, R...Resistance, 10.2On...
·comparator. Figure 2 Figure 2 Figure 2

Claims (1)

[Claims] An emitter follower circuit provided in front of each of a plurality of comparators of a parallel analog-to-digital converter, the emitter follower circuit commonly applying an analog input signal to the base of each transistor of the emitter follower, and also applying an analog input signal to the base of each transistor of the emitter follower. 1. An emitter follower circuit, characterized in that the emitter is connected to the emitter follower circuit, and the emitter follower circuit is configured to reduce distortion of the emitter output caused by the transition of the state of the comparator.