JPH03142855A - Manufacture of dielectric isolated substrate - Google Patents

Abstract

PURPOSE:To improve the reliability of bonding by polishing and flattening the surface of a filling material, overlapping a supporting substrate on the material, applying a voltage across a semiconductor substrate and the supporting substrate, and performing heat treatment. CONSTITUTION:A polycrystalline silicon film 15 is deposited until element isolating grooves 13 are filled up. The surface of the film is polished and flattened. A supporting substrate 17 which has a thermal oxide film 16 and comprises a silicon substrate is otherwise prepared. The supporting substrate 17 is overlapped on the surface of the flattened polycrystalline silicon film 15, and the substrate and the film and bonded. That is, the devices are heated to 1,100 deg.C at the temperature rising speed of 100-200 deg.C/min. by using a heater 18 under the reduced pressure or of, e.g. 1-5Torr. During the temperature rising, a pulse-shaped voltage of 200-500V is applied from a voltage source 19 that is connected between the silicon substrate 11 and the supporting substrate 17. Thereafter, heat treatment is performed for about one hour at 1,000-1,100 deg.C in inactive gas atmosphere. The electrostatic attracting force generated between both substrates by the application of the voltage enhances the adhesion between both substrates, and the reliability of the bonding by the heat treatment is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a dielectric separation substrate, the purpose is to improve the close adhesion between a supporting substrate and a semiconductor substrate by electrostatic attraction, and to improve the reliability of adhesion. A step of forming an isolation trench in the substrate, a step of depositing an insulating film on the entire surface and selectively forming an opening in the insulating film, and a step of depositing a silicon film or a conductive material on top of this until the device isolation trench is filled. A step of depositing a filling material consisting of a silicon film or a conductive material and bringing the semiconductor substrate into contact with the filling material in the opening, or filling an element isolation trench with an insulating material and then depositing a filling material made of a silicon film or a conductive material thereon. a step of bringing the semiconductor substrate into contact with the filling material in the opening; and a step of polishing and planarizing the surface of the charging material.
The step includes the step of overlaying a support substrate or a support substrate on which an insulating film is formed and heat-treating the semiconductor substrate and the support substrate while applying a voltage between the semiconductor substrate and the support substrate to bond the filling material and the support substrate. Configure it as follows.

[Industrial application field]

The present invention relates to a method for manufacturing a dielectric isolation substrate.

Although a pn junction, which is commonly used for isolation between elements of semiconductor ICs, has the advantage of being formed by a simple process, it has problems such as low breakdown voltage and parasitic transistor action, which limit its application.

Dielectric separation does not have the above-mentioned drawbacks and is used, for example, in high-voltage ICs for telephone exchanges or CMO3, but the problem remains that the process is complicated and reliability is lacking.

[Prior Art] FIGS. 6(a) to 6(d) are process cross-sectional views showing a method of manufacturing a dielectric isolation substrate according to a conventional example.

First, as shown in FIG. 2A, after forming an element isolation groove 13 in a silicon substrate 11, a thermal oxide film 12 is formed on the entire surface. Next, as shown in FIG. 3C, a polycrystalline silicon film 15 is deposited using the usual CVD method until it fills the element isolation trench 13, and then the surface is polished and planarized. Next, as shown in FIG. 2C, a support substrate 17 made of a silicon substrate having a thermal oxide film 16 formed on its surface is superimposed on the polycrystalline silicon film 15 and heated with a heater for bonding. At this time, due to the warpage of the silicon substrate 11 or the support substrate 17, simply stacking them as described above results in poor adhesion and insufficient adhesion by heat treatment. Therefore, a DC or pulsed voltage is applied between the silicon substrate 11 and the support substrate 17 by the voltage source 19,
The electrostatic attraction that acts between them improves the adhesion between the two substrates and improves the reliability of the bond. Next, as shown in FIG. 2D, the silicon substrate 11 is polished until a part of the thermal oxide film 12 is exposed to form an island-shaped single crystal silicon layer lla. The supporting substrate 1 is separated from each other by using the polycrystalline silicon film 15 as an adhesive.
A dielectric isolation substrate supported by 7 can be obtained.

[Problem to be solved by the invention]

The above applied voltage causes the silicon substrate 11 and the support substrate 17 to
The smaller the distance between the two substrates, the stronger the electrostatic attraction acting between them becomes, and the adhesion between the supporting substrate 17 and the polycrystalline silicon film 15 improves. The distance between the two substrates becomes the minimum when the thickness t of the polycrystalline silicon film 15 shown in FIG. 6C becomes zero, and the electrostatic attraction becomes the strongest at this time. However, in the area where the element isolation groove exists, the distance between the silicon substrate 11 and the support substrate 17 is greater than that in other areas by the depth of the element isolation groove, and the electrostatic attraction between them is small. Furthermore, since the element isolation trench usually occupies a large proportion of the area on the silicon substrate 11, the average value of electrostatic attraction becomes small, resulting in a problem of poor adhesion.

Accordingly, an object of the present invention is to improve the adhesion between a support substrate and a semiconductor substrate using electrostatic attraction, thereby improving the reliability of adhesion.

[Means to solve the problem]

The solution to the above problem involves the steps of forming an isolation trench in a semiconductor substrate, depositing an insulating film over the entire surface, selectively forming an opening in the insulating film, and burying the isolation trench on top of this. A step of depositing a filling material made of a silicon film or a conductive material and bringing the semiconductor substrate into contact with the filling material in the opening, a step of polishing and planarizing the surface of the charging material, and a step of depositing a supporting substrate or A dielectric characterized by comprising the step of stacking supporting substrates on which insulating films are formed and bonding the filling material and the supporting substrate by applying a voltage between the semiconductor substrate and the supporting substrate and performing heat treatment. In the method for manufacturing a body isolation substrate or the above method for manufacturing a dielectric isolation substrate, an element isolation trench is filled with an insulating material, and then a filling material made of a silicon film or a conductive material is deposited thereon, and a filling material made of a silicon film or a conductive material is deposited on the trench. This is achieved by a method for manufacturing a dielectric isolation substrate, which includes the step of bringing a semiconductor substrate into contact with the filling material.

[For production]

In the present invention, the semiconductor substrate and the filling material are electrically connected through the opening. Therefore, when a voltage is applied between the semiconductor substrate and the support substrate, electrostatic attraction acts only through the insulating film or gap between the filling material and the support substrate, regardless of the thickness of the filling material. Electrostatic attraction is stronger than before. Therefore, the adhesion between the filling material and the support substrate is improved.

〔Example〕

FIG. 1 is a process sectional view showing a first embodiment of the present invention.

First, as shown in FIG. 2A, element isolation grooves 13 are formed in a silicon substrate 11 using ordinary photolithography, and a thermal oxide film 12 is formed by heat treatment in an oxidizing atmosphere. Subsequently, the thermal oxide film 12 is selectively etched to form an opening 14. The opening 14 is formed in a location where no device will be formed in a subsequent device formation step, such as a scribe line region. Then, as shown in the same figure (b), C
A polycrystalline silicon film 15 is deposited by the VD method until the element isolation groove 13 is filled, and its surface is polished and planarized. Next, as shown in FIG. 2C, a support substrate 17 made of a separately prepared silicon substrate having a thermal oxide film 16 is superimposed on the surface of the flattened polycrystalline silicon film 15, and the support substrate 17 is formed by the following method. Glue. Note that the thermal oxide film 16
It is also possible to use a silicon substrate on which no polycrystalline silicon film 1 is formed as a supporting substrate.
5 and the support substrate 17 are insulated by a gap created by slight warping of the silicon substrate 11 or the support substrate 17.

To perform the bonding, heating is performed to 1100° C. at a rate of 100-b using a heater 18 under a reduced pressure of 1-5 Torr. During this temperature rise, as shown in FIG.
A pulsed voltage of 500 V is applied. Thereafter, heat treatment is performed at 1000 to 1100° C. for about 1 hour in an inert gas atmosphere. The electrostatic attraction generated between the two substrates by the voltage application as described above increases the adhesion between the two substrates and improves the reliability of adhesion by heat treatment. At this time, the semiconductor substrate 1
Since M1 is connected to polycrystalline silicon film 15 through opening 14, the above voltage is applied between polycrystalline silicon M15 and support substrate 17. Therefore, a stronger electrostatic attraction force acts between the polycrystalline silicon film 15 and the support substrate 17 than in the past, and the reliability of adhesion is improved. Furthermore, in the above configuration, even if the insulation film 16 or the gap between the polycrystalline silicon film 15 and the support substrate 17 is dielectrically broken down by the applied voltage, the subsequent device manufacturing process is not affected in any way. Therefore, it is also possible to apply a large voltage to further strengthen the electrostatic attraction. However, in the conventional structure, since a voltage is applied to the insulating film 12, if dielectric breakdown occurs due to an excessively applied voltage, the element isolation function is impaired. Therefore, the magnitude of the applied voltage has been limited.

Note that the polycrystalline silicon film has insulating properties at room temperature when it is not doped with impurities, but becomes conductive at the above heat treatment temperature, and the voltage is applied between the polycrystalline silicon film 15 and the supporting substrate 17. applied in between.

Next, as shown in FIG. 12A, the silicon substrate 11 is polished until a part of the thermal oxide film 12 is exposed, and the silicon substrates 11 are separated from each other to form a single crystal silicon layer 11a.
is formed. Thereafter, elements are formed within this single crystal silicon layer 1a.

Next, FIGS. 2 to 5 are sectional views showing other embodiments in which some steps of the first embodiment are changed.

Each shows the structure of a dielectric isolation substrate corresponding to FIG. 1(d), and parts having the same functions as those in FIG. 1(d) are given the same numbers.

In the second embodiment shown in FIG. 2, only the inside of the element isolation trench is filled with an insulating material 15a such as PSG, and then a polycrystalline silicon film 15 is deposited thereon, and other steps are not performed. It is similar to FIG.

In the third embodiment shown in FIG. 3, an insulating material 15a is deposited over the entire surface including the isolation trenches, and an opening 14 is formed in the insulating material 15a. A polycrystalline silicon film 15 is then deposited. The other steps are the same as those shown in FIG.

In the fourth embodiment shown in FIG. 4, element isolation grooves are formed by forming TOCOS oxide 12a on a semiconductor substrate 11 by a normal thermal oxidation method, and other steps are the same as in FIG. It is. In this example, since shallow element isolation trenches can be formed with high precision, CMO3I
It is suitable for manufacturing ICs including MOS transistors such as C.

In the fifth embodiment shown in FIG. 5, V-shaped element isolation grooves are formed by anisotropically etching a semiconductor substrate having a (100) plane with an etching solution containing a caustic soda solution. The process is the same as that shown in FIG. This embodiment is suitable for manufacturing high-voltage ICs because deep element isolation grooves can be obtained through a simple process.

In any of the above structures, silicon substrate 11 and polycrystalline silicon film 15 are connected through opening 14. Therefore, the voltage applied between the silicon substrate and the support substrate is applied between the support substrate and the polycrystalline silicon film, resulting in a strong electrostatic attraction and improving the reliability of adhesion.

Note that in any of the embodiments described above, a polycrystalline silicon film doped with impurities can also be used. Further, instead of the polycrystalline silicon film, an amorphous silicon film, SiC, a high melting point metal film such as tungsten or molybdenum, or a silicide thereof can be used.

〔Effect of the invention〕

As described above, according to the present invention, the adhesion of the support substrate is improved and a highly reliable dielectric separation substrate can be obtained, which improves the reliability of semiconductor devices such as high voltage ICs and CMO3 ICs using the same. It is beneficial in improving the

[Brief explanation of the drawing]

1(a) to (d) are process sectional views showing the first embodiment, FIG. 2 is a sectional view showing the second embodiment, and FIG. 3 is a sectional view showing the third embodiment. FIG. 4 is a sectional view showing the fourth embodiment, FIG. 5 is a sectional view showing the fifth embodiment, and FIG. 6 is a process sectional view showing problems in the conventional example. In the figure, 11 is a silicon substrate, 11a is a polycrystalline silicon layer, 12 is a thermal oxide film, 12a is a LOCO3 oxide film, 13 is an element isolation trench, 14 is an opening, 15 is a polycrystalline silicon film, 15a is an insulating material, 16 is an insulating film, 17 is a supporting substrate, and 18 is a heater 19, which is a voltage source. '! I/) f2q column 1: Tede-,yx,! L Jj
A nail surface diagram showing the second real 7-A row. Shows the real square color Ita 1 of A Sending section

Claims (2)

[Claims] (1) A step of forming an element isolation trench (13) in a semiconductor substrate (11), depositing an insulating film (12) on the entire surface, and depositing the insulating film (12) on the entire surface.
12) selectively forming an opening (14) in the opening (14); depositing a filling material (15) made of a silicon film or a conductive material thereon until the element isolation trench (13) is filled; 14), a step of bringing the semiconductor substrate (11) and the filling material (15) into contact; and a step of polishing and planarizing the surface of the charging material (15).
A support substrate (17) or a support substrate (17) on which an insulating film (16) is formed is superimposed on this, and heat treatment is performed while applying a voltage between the semiconductor substrate (11) and the support substrate (17). A method for manufacturing a dielectric isolation substrate, characterized in that the method further comprises the step of bonding the filling material (15) and the supporting substrate (17). (2) After filling the element isolation trench (13) with an insulating material (15a), a filling material (15) made of a silicon film or a conductive material is deposited thereon, and the semiconductor substrate ( 11. The method of manufacturing a dielectric isolation substrate according to claim 1, further comprising the step of bringing the filling material (15) into contact with the filler material (11).