JPH03139125A - Digital synchronous parallel-in apparatus - Google Patents

Abstract

PURPOSE:To prevent an apparatus from performing a loop determination and loop holding in error by determining a loop system, only when two loop- determining elements or more differing in a phase difference-measuring interval operate together, and by causing a flip-flop to hold the output of the determining elements. CONSTITUTION:In loop-determining elements 9, 19, e.g. the phase difference theta-measuring interval of the loop-determining element 9 is set to 5 seconds and that of the loop-determining element 19 is set to 5.1 seconds. Further, the difference between the two phase difference theta-measuring intervals 5.1 seconds-5.0 seconds = 0.1 second is selected to take a value which is less than the minimum slip period to be estimated in that system. Then, even if the value of an integral number of times of the slip period is equal to the phase difference theta-measuring interval of one loop-determining element 9(19), it is not equal to that of the other loop-determining element 19(9). Thus, it is possible to prevent both loop- determining elements 9, 19 from performing a loop determination in error simultaneously, whatever value a phase difference theta may take.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a digital synchronous parallelization device used when interconnecting two power systems that are not interconnected.

(Prior Art) FIG. 3 is a block diagram of an example of a synchronous parallel entry device, and FIG. 4 is an example of countries where the synchronous parallel entry device is applied. In FIG. 4, when the bus side voltage VB and the transmission line ffII voltage vL are synchronized, the synchronous parallel connection device outputs a closing command to the breaker CB and connects the bus side system and the power transmission line side system in parallel. In Fig. 3, the synchronous paralleling device is connected to the bus line (111 voltage VB, transmission line side voltage VL
are in the range of 80% or more and 1120% or less of the rated voltage, respectively, the transmission line voltage detection element 1. Bus voltage detection element 2
outputs.

At this point, if a startup command is given to the system parallel device, go to N
O logic 10 outputs. First, input in the case of a loop system as shown in FIG. 5 will be explained.

In this case, the bus line side voltage 8 and the transmission line side voltage VL are always synchronized, and the operations of each element and each logic are as follows. Since the bus line side frequency fB and the power line side frequency fL are equal, the frequency difference detection element 3 outputs. As long as there is no abnormality in the bus line side frequency f8, the frequency lower limit or higher check element 4 outputs. As long as there is no abnormality in the difference between the bus side voltage VB and the transmission line side voltage VL, the voltage difference check port F! ? 15 outputs. If the phase difference θ between the bus line side voltage angle θθ and the power line side voltage angle θL is below a certain value, the phase difference confirmation element 6 outputs.

If the temporal change in the phase difference θ is below a certain value, the loop determination element 9 outputs an output, and the flip-flop 15 holds the output. As a result of the above, the AND logic 11 outputs, the ND logic 13 outputs, the AND logic 16 for loop connection connection outputs, the OR logic 18 for input command outputs,
The synchronous parallel entry device outputs an entry command.

Next, input in the case of different systems as shown in FIG. 6 will be explained. In the case of different systems, the bus side frequency fB and the transmission line side frequency f are different and generally have a slip frequency fs. Therefore, the loop determination element 9 does not output, and the flip-flop 15 also does not output. Since the movement of each element in the loop system described above can be similarly understood, the explanation will be omitted. In this state, synchronization is repeated in a cycle based on the slip frequency fS, and in the process of moving toward the synchronization point, the phase difference θ is in the decreasing direction, so the phase difference decreasing direction confirmation element 8 outputs, and the breaker closing time ( The cuff for predicting zero phase difference, which outputs in consideration of the forward time), outputs an output ahead of the point of zero phase difference by the forward time, and AND logic 12
outputs. Therefore, the AND logic 14 outputs, the inhibit logic 17 for different system input outputs, the OR logic 18 for input command outputs, and the synchronous parallel input device outputs an input command.

The above is an explanation of the configuration and operation of an example of a conventional synchronous parallel entry device.

(Problems to be Solved by the Invention) In FIG. 3, the configuration of the loop determination element 9 is, for example, 0.
Since the value is about 5 degrees/S, due to the resolution limit of the phase difference θ, for example, if the measurement interval of the phase difference θ is 5 seconds, the phase difference θ
A method is used to determine whether or not the change was a 2.5 degree end groove change. However, using this method solves the problem of resolution of the phase difference θ, but as shown in Figure 7, when the integral multiple of the slip period is 5 seconds, there is a change of more than 045 degrees/S. Nevertheless, it is assumed that there is no change, that is, less than 0.5 degrees/S, so the loop determination element 9 outputs and the flip-frog 15 maintains its output. After such a state occurs, even if the above-mentioned conditions for parallel input of different systems are met, the inhibit logic 17 for inputting different systems
The problem arises in that it cannot be input because it is locked.

The present invention solves the above problem, and aims to provide a digital synchronous parallelization device that does not erroneously hold a loose determination, no matter what value the phase difference θ is.

[Structure of the invention] (Means for solving problems) An explanation will be given based on FIG. 1, which is an embodiment of the present invention.

As shown in FIG.
．． Only when both 19 operate, it is determined that the system is a loop system, and the flip-flop 15 holds the output.

(Function) In this way, even if the integral multiple of the slip period becomes equal to the phase difference θ measurement interval for one loop determination element, it will not be equal for the other loop determination element, so the above-mentioned parallelization of different systems will not be possible. This problem is solved.

(Example) An explanation will be given below based on FIGS. 1 and 2, which are an example of the present invention.

FIG. 2 is an example of a digital synchronous parallel processing device. P.T.
The bus line side voltage 8 inputted from the auxiliary PT 21 is introduced into the filter F22, and the output of the filter F22 is introduced into the sample and hold circuit 23.

Similarly, the power transmission line side voltage input from PT ■L is auxiliary PT
21 to the filter F22, and filter "2" is introduced into the filter F22.
The output of 2 is introduced into a sample hold circuit 23. 2
The outputs of the sample and hold circuits are sent to the multiplexer 24.
will be introduced in The output of multiplexer 24 is introduced into A/D converter 25. The output of the A/D converter 25 is CPt
126. Start command is I10 buffer 30
The output of the I10 buffer 30 is also input to the CPU 26.
Introducing 2. CPU26 ROM27 and RA
Connected to M28 and also I10 buffer 29
It is also connected to the system, and is configured to be able to output a closing command.

Next, the effect will be explained.

In Fig. 2, the bus side voltage VB and the system side voltage vL are each insulated by the auxiliary PT21, and the analog filter [2
2 will be introduced. The analog filter F22 cuts out harmonic components that cause aliasing frequency errors.

Next, each signal is introduced into the sample-and-hold circuit 23, where it is sampled and held at regular intervals (generally, a time angle of 30° is used as the sampling interval). The multiplexer 24 sequentially inputs data from each sample and hold circuit to the input/D converter 25 . A/
The D converter 25 sequentially converts the introduced analog data into digital data and outputs the digital data. The data is CP
It is stored in RAM28 via O26. When the activation command is input to the buffer 30 in this state, the CPU 26 inputs it as a signal and stores it in the RAM 28. The CPU 26 performs calculations in accordance with a program written in advance in the ROM 27, and when the conditions for outputting the inputting command are established, outputting the inputting command via the 170 buffer 29. An example of the contents of a program executed by a CPU is shown in a block diagram as shown in FIG.

This will be explained below based on FIG. The parts in Fig. 1 that are the same as those in Fig. 3, which is a conventional example, are referred to as (prior art).
Since this has already been explained in the section above, the explanation will be omitted.

In FIG. 1, the loop determination element 9.19 has a configuration such that, for example, if the phase difference θ measurement interval of the loop determination element 9 is 5 seconds, the phase difference θ measurement interval of the loop determination element 19 is 5.1 seconds. In addition, the difference between the two phase difference θ measurement intervals is 5.1 seconds -
5.0 seconds = 0.1 seconds shall be selected as a value that is less than the minimum slip period assumed in the system. In this way, even if the integral multiple of the slip period becomes equal to the phase difference θ measurement interval for one loop determination element, it will not be equal for the other loop determination element, so both loose determination elements will mistakenly perform a loose determination at the same time. Never. Therefore, loop determination element 9
and the output of one loop determination element are introduced into the AND logic 20, and only when the AND condition is satisfied, the flip-flop 15 is held and the inhibit logic 17 for inputting a different system is locked, and when the input of a different system is applied, it is locked and the output is not activated. There will be no more saying that you can't do it.

As described above, even though the synchronous parallel entry device is actually in a system state where it can be entered under certain conditions, it will no longer become impossible to make entry.

[Effects of the Invention] As explained above, according to the present invention, the reliability of inputting the synchronous parallel device is improved, and the operation of the power system is further improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a digital synchronous parallel entry device according to the present invention, FIG. 2 shows the hardware configuration of a digital synchronous parallel entry device, and FIG. 3 shows a block diagram of a conventional synchronous parallel entry device. Figure 4 is an example of a system application of a synchronous parallel entry device, Figure 5 is an example of a system with different systems, Figure 6 is an example of a loose system, and Figure 7 is an example of a system with a loose system.
The figure shows an example where the integral multiple of the slip period is 5 seconds. 9.19...Loop system determination element 15...Flip frog

Claims (2)

[Claims] (1) In order to synchronize two power systems, a digital synchronous paralleling device inputs the voltage of each system, verifies their phase difference, frequency difference, and voltage value range to derive a power-on command. It comprises at least a phase difference change detection element that measures a change in the phase difference θ of the voltage of the power system at different time intervals t_1 and t_2, and the time interval difference |t_1−t_2
A digital synchronous parallelization device characterized in that | is less than a minimum slip period of the two power systems assumed on the power system. (2) In order to synchronously connect two power systems, a digital synchronous paralleling device inputs the voltage of each system, verifies their phase difference, frequency difference, and voltage value range to derive a power-on command. It comprises at least a phase difference change detection element that measures a change in the phase difference θ of the voltage of the power system at different time intervals t_1 and t_2, and the time interval difference |t_1−t_2
A digital synchronous parallelization device characterized in that it is set so that a natural number multiple of | is not t_1 or t_2.