JPH03139014A - Ttl/mos level conversion circuit - Google Patents

Abstract

PURPOSE:To decrease a transient through-current and to reduce power consumption by providing an N-channel MOSFET connected between a P channel MOSFET of a CMOS inverter and a power line, and reaching normally ON state in response to a constant voltage. CONSTITUTION:When a TTL input is at an L level, a P-channel MOSFETQ1 is turned on by a voltage applied between the gate and source of the TR of a CMOS inverter and its drain level is nearly VCC when the Pchannel MOSFET is turned on. Since a voltage close to a threshold level is applied between the gate and source of a MOSFETQ2, the TRQ2 is almost turned on. On the other hand, when the TTL input is at H, a voltage turning sufficiently on the FET is applied between the gate and source of the N-channel MOSFETQ2, but since only a low voltage is applied between the gate and source of the TR Q1, the TR Q1 is cut off. Thus, the through-current is sufficiently reduced by cutting off the through-current when the level is at H.

Description

[Detailed Description of the Invention] [Summary] A TTL/MOS level conversion circuit, particularly a circuit provided in an input first stage circuit of a semiconductor device, for converting an external TTL level signal to a logic level for an internal MO3 circuit. Regarding the configuration, with the aim of performing TTL/MOS level conversion with low power consumption, a first power supply line, a second power supply line with a lower potential than the first power supply line, and a TTL level input signal are connected. In response, an n-channel MOS transistor is connected between a complementary MOS inverter connected to the second power supply line, a p-channel MOS transistor of the complementary MOS inverter and the first power supply line, and a constant voltage is applied. The device is configured to include an n-channel MOS transistor that is normally on in response to the above.

[Industrial Application Field] The present invention relates to a TTL/MOS level conversion circuit, and in particular, it is provided in an input first stage circuit of a semiconductor device and converts an external transistor-transistor-logic (TTL) level signal into an internal metal The present invention relates to a circuit configuration for converting to a logic level (MOS level) for an oxide/semiconductor (MOS) circuit.

[Prior art and problems to be solved by the invention]

FIG. 12 shows the configuration of a TTL/MOS level conversion circuit as an example of a conventional type.

The illustrated circuit consists of a p-channel transistor QPO connected in series between a high-potential power supply line Vcc (5V) and a low-potential power supply line νss (OV), and a complementary MO3 ( CMOS)
Inverter (p channel transistor QPI and n channel transistor QN1) and power supply line Vc
c and Vss, and a second CMOS inverter (P-channel transistor QP2 and n-channel transistor N2) connected to the internal circuit in response to the output of the CMOS inverter.

Furthermore, a constant voltage Vss is applied to the gate of the p-channel transistor QPO, thereby placing the transistor in a normally on state. Therefore, the source potential of the p-channel transistor QPI of the CMOS inverter is about 5■. In addition, in order to follow the TTL input 0.8V (“L” level) to 2.4V (“H” level),
Usually, it is set to about the middle value (1.6V) of the threshold level power of the CMOS inverter (QPI, QN1).

In this configuration, when the TTL input signal IN is at the "high" level (0.8V), the voltage between the gate and source of the p-channel transistor QPI of the CMOS inverter is approximately -4.2V.
Since the voltage of V is applied, the transistor is sufficiently turned on, and its drain potential becomes approximately 5V (“H” level). In addition, a voltage close to the threshold level (0
．． 8V), the transistor QNI is also barely turned on.

Therefore, in this case, a through current flows transiently from the power supply line Vcc to the power supply line Vss via the transistors po, qpt, and QNI.

On the other hand, the TTL input signal IN is at “H” level (2.4V)
In this case, voltages of approximately -2.6 V and +2.4 V are applied between the gates and sources of the p-channel transistor QPI and the n-channel transistor QNI, respectively, and both transistors are fully turned on. At this time, n
Focusing on the channel transistor QNI, the bias conditions are a drain potential of approximately 5V, a source potential of 0■, and a gate potential of 2.4■, which results in a large through current (approximately 50-10 in
A through current of about 0 μA) flows.

In any case, a through current flows through the CMOS inverter, and in particular, when the TTL input is at the "11" level, a relatively large amount of through current flows, resulting in a corresponding increase in power consumption. .

The present invention was created in view of the problems in the prior art, and it is possible to use TTL/
It is an object of the present invention to provide a circuit configuration that can perform MOS level conversion with low power consumption.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a TTL/MOS level conversion circuit provided in an input first stage circuit of a semiconductor device, which has a first power supply line and a lower potential than the first power supply line. a second power supply line; a CMOS inverter responsive to a TTL level input signal and having an n-channel MOS transistor connected to the second power supply line; a p-channel MOS transistor of the CMOS inverter; n-channel M, which is connected between the power supply lines of the
A TTL characterized by comprising an OS transistor.
/MOS level conversion circuit is provided.

Also preferably, the n-channel M of the CMOS inverter is
A p-channel MOS transistor that is normally on in response to a constant voltage may be connected between the OS transistor and the second power supply line.

More preferably, the constant voltage applied to the gate of the normally-on p-channel MOS transistor may be directly supplied from a power supply pad for the second power supply line.

In addition, the above-mentioned n-channel MOS which is in the normally on state
N-channel M of transistors and CMOS inverters
Instead of the OS transistor, an npn bipolar transistor that responds to a TTL level input signal may be provided, or an npn bipolar transistor may be provided instead of the n-channel MOS transistor that is normally on.

[Effect]

According to the above-described basic configuration, the source potential of the n-channel MOS transistor of the CMOS inverter is lower than the constant voltage applied to the normally-on n-channel MOS transistor by its threshold level. Therefore, when the TTL input signal is at the "H" level, the voltage applied between the gate and source of the p-channel MOS transistor can be lowered to below its threshold level. At this time, p channel MO3! - Since the transistor is in a cut-off state, no through current flows through the CMOS inverter.

In other words, it is possible to avoid the state in which the maximum through current flows when the TTL power is at the "H" level in the conventional type, thereby making it possible to reduce power consumption.

Furthermore, when a P-channel MOS transistor that is normally on in response to a constant voltage is connected between the n-channel MOS transistor of the CMOS inverter and the second power supply line, the source potential of the n-channel MOS transistor is Since the voltage is increased by the threshold level of the p-channel MOS transistor, the voltage applied between the gate and source of the HK n-channel MOS transistor can be lowered to below the threshold level when the TTL input signal is at the "high" level.

Therefore, in this case, the n-channel MOS transistor is in a cut-off state and no through current flows, making it possible to further reduce power consumption compared to the above basic configuration.

Furthermore, if the constant voltage applied to the gate of the normally-on p-channel MOS transistor is directly supplied from the power supply pad for the second power supply line, high reliability that is not affected by noise can be achieved. You can expect it to work.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows the configuration of a TTL/MOS level conversion circuit as an embodiment of the present invention, and is configured as a part of an input initial stage circuit of a semiconductor memory device, for example.

The TTL/MOS level conversion circuit of this embodiment is a CMOS inverter (p channel M
An n-channel MOS transistor Q3 that is connected between the OS transistor RO and the n-channel MOS transistor RO 2), the high-potential power supply line Vcc (5V), and the CMOS inverter, and becomes normally on in response to the constant voltage v0. and a p-channel MOS transistor Q4, which is connected between the output end of the CMOS inverter and the power supply line Vcc and serves as a feedback circuit that responds to the potential of the node (2), and between the power supply lines Vcc and Vss,
The second in response to the output of the S inverter (port 1, Q2)
(a p-channel MOS transistor R5 and an n-channel MOS transistor Q6), and a constant voltage circuit CV for supplying a constant voltage v8 to the gate of the n-channel MOS transistor Q3.

This constant voltage circuit Cv consists of a resistor R and five silicon diodes DI-D5 connected in series between the power supply lines Vcc and Vss.
The constant voltage v0 is taken out from the connection point. Assuming that the forward voltage drop of each silicon diode is approximately 0°7■,
The constant voltage v0 is set to about 3-5V (see Figure 2). The n-channel MOS transistor RO 3 has this constant voltage v0.
Since it is normally on in response to the CM
The source potential of the p-channel MOS transistor Ro1 of the OS inverter is a potential (approximately 2.6 V) lower than the constant voltage v0 by the threshold level of the transistor Q3.
It becomes.

Note that the CMOS inverter (Q
The gate of the p-channel MOS transistor Ql is connected to the node ■, the source side of the p-channel MOS transistor Ql is connected to the node ■, and the n-channel MO5
) The gate of transistor Q3 is connected to node ■, and CMOS I7 is connected to inverter 1. Q2) (Connect the D output end to the notebook ■, and
Connect the output end of the CMOS inverter (Q5, Q6) to the node ■
FIG. 2 shows operation timing waveforms in each part of the circuit of FIG. 1. As mentioned above, the potential of node ■ is approximately 2
．． 6V, and the potential of the node ■ is kept constant at approximately 3.5V.

As shown in the figure, TTL input (potential of node ■)
is “L” (8V) (7), the gate of the p-channel MOS transistor Ql of the CMOS inverter
Since a voltage of approximately -1.8V is applied between the source and the transistor, the transistor is fully turned on and its drain potential (
The potential of the node (2) becomes approximately at the level of Vcc by turning on the p-channel MOS transistor RO4. Also, n
Since a voltage (0.8 V) close to the threshold level is applied between the gate and source of the channel MOS transistor Q2, the transistor Q2 is also barely turned on. Therefore, in this case, the transistor Q3. A through current flows to the power supply line Vss via Q1 and Q02.

On the other hand, the TTL input (potential of node ■) is at “L” level (
2.4V), a voltage of 2.8V is applied between the gate and source of the n-channel MOS transistor Q2, and the transistor (12 is fully turned on, but the p-channel MOS transistor Q2 is turned on).
There is approximately -0 between the gate and source of the OS transistor Ql.
Since only a voltage of 2V is applied, the transistor Q1 is in a cut-off state. Therefore, in the case of leverage, no through current flows through the CMOS inverters (Ql, Q2).

As mentioned above, originally, more through current flows when the TTL input level is at H level than when it is at L level, but according to the configuration of this embodiment, this TTL input level is at H level. ”Since the through current is cut when the
(to about 9 and several tens of μA per inverter stage). This contributes to reducing power consumption.

FIG. 3 shows a circuit configuration of another embodiment of the present invention.

The difference in configuration between this embodiment and the above embodiment (Fig. 1) is as follows.
(1) Between the n-channel MOS transistor Q2 of the CMOS inverter and the power supply line Vss, the p-channel MOS transistor Q7, which is normally on in response to the constant voltage Vss, is connected. (2) The potential of the node ■ Instead of the p-channel MOS transistor Q4 as a responsive feedback path, a CMOS inverter (p-channel MOS transistor Q8 and n-channel MOS transistor Q9) as a feedback path responsive to the potential of the node
is provided after the CMOS inverter (Q5, Q6).

The other circuit configurations and operations are the same as those in the above embodiment, so their explanation will be omitted.

In this case, a CMOS inverter (Q8.
Q9) has a function to fully swing the potential of node (2) in the range of Vcc=Vss.

In addition, the n-channel MOS transistor Q7 has a constant voltage Vs
Since it is normally on in response to s, C
N-channel MOS transistor Q2 of MOS inverter
The potential on the source side (node ■) of is higher than the constant voltage Vss by the threshold level of the transistor Ω7 (approximately 0.9 V).

FIG. 4 shows the operation timing waveforms of the third circuit.

According to the embodiment shown in FIG. 3, when the TT'L input (potential of node 2) is "0.8 V", the voltage between the gate and source of the lower P-channel MOS transistor of the CMOS inverter is approximately -1, Since the voltage of 8■ is applied, the transistor is sufficiently turned on, and its drain potential (the potential of the node ■) becomes the level of Vcc by turning on the n-channel MOS transistor Q8. -0 between the gate and source of
, 1■ are applied, so the transistor Q2 enters the cut-off state. Therefore, in this case, no through current flows through the CMOS inverters (Ql, Q2).

On the other hand, when the TTL power (potential of node ■) is at the "l(' level (2,4V)), the CM
No through current flows through the OS inverter (Ql, Q2).

In other words, according to the embodiment shown in FIG. 3, it is possible to further reduce power consumption compared to the embodiment of the first IJ.

FIG. 5 shows a circuit configuration of still another embodiment of the present invention, and FIG. 6 shows its operation timing waveform.

This embodiment is structurally different from the above embodiment (Fig. 3) as follows:
(1) A p-channel MOS transistor q4 similar to the embodiment shown in FIG. 1 is provided as a feedback circuit, (2) CMO
S inverter (7) n-channel MOS transistor Q6
and power line VssO, a p-channel MOS transistor 10 which is normally on in response to constant voltage Vss is connected between (3) node ■ and power line V
(4) The output terminal (node ■) of the CMOS inverter (081 port 9) serving as a feedback circuit is connected to the gate of the transistor 11111. For other circuit configurations, functions, and effects, see the above example (Fig. 3).
Since it is the same as that, its explanation will be omitted.

FIG. 7 shows a circuit configuration of a modified example of the embodiment shown in FIG.

This embodiment differs in structure from the embodiment shown in FIG.
and the constant voltage Vss applied to each gate of QIO,
It is directly supplied from the power pad P for the power line Vss. This makes it possible to achieve highly reliable operation without being affected by noise. The other circuit configurations, functions, and effects are the same as those of the above embodiment (FIG. 5), so their explanations will be omitted.

FIGS. 8 and 10 each show a circuit configuration of a modification of the embodiment shown in FIG. 5, and FIGS. 9 and 11 show corresponding operation timing waveforms, respectively.

The embodiment shown in FIG. 8 is structurally different from the embodiment shown in FIG.
An npn bipolar transistor TI that responds to the TTL input signal IN is provided in place of the p-channel MOS transistor lower which is normally on and the n-channel MOS transistor Q2 of the CMOS inverter.

The embodiment of FIG. 10 is structurally different from the embodiment of FIG. 5 in that (1) the p-channel M is in a normally on state
O3) The constant voltage vSS applied to each gate of the transistor Q10 is directly supplied from the power supply pad P for the power supply line Vss, (2) n-channel MOS that is normally on) instead of the transistor Q3. ni npn
This is because a bipolar transistor T2 is provided. The other circuit configurations, functions, and effects are the same as those of the embodiment shown in FIG. 5, so their explanations will be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the transient current flowing through the CMOS inverter in the input first stage circuit of a semiconductor device, thereby making it possible to reduce power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a TTL/MOS level conversion circuit as a first embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the circuit in FIG. 1, and FIG. 3 is a second embodiment of the present invention. 4 is a timing diagram showing the operation of the circuit shown in FIG. 3, and FIG. 5 is a circuit diagram showing the configuration of the TTL/MOS level conversion circuit as the third embodiment. 6 is a timing diagram showing the operation of the circuit in FIG. 5, FIG. 7 is a circuit diagram showing the first modification of the circuit in FIG.
9 is a timing diagram showing the operation of the circuit in FIG. 8, FIG. 1θ is a circuit diagram showing a third modification of the circuit in FIG. FIG. 10 is a timing diagram showing the operation of the circuit, and FIG. 12 is a circuit diagram showing the level configuration of a TTL/MOS level conversion circuit as an example of a conventional type. (Explanation of symbols) Ql, Q7...p channel MOS transistor, Q2
．． Q3...n channel MOS) transistor, T1. T
2...npn bipolar transistor, Vcc, V
ss...power supply line, IN...TTL level input signal, ν. ...Constant voltage, P...Power pad. Figure 5: Circuit diagram showing a first modification of the circuit Figure 5: Circuit diagram showing a third modification of the circuit

Claims (1)

[Claims] 1. TTL/M provided in the input first stage circuit of a semiconductor device
The OS level conversion circuit includes a first power line (Vcc) and a second power line (Vcc) having a lower potential than the first power line.
Vss) and a complementary MOS inverter responsive to a TTL level input signal (IN) and having an n-channel MOS transistor (Q2) connected to the second power supply line;
p-channel MOS transistor (Q1) of the OS inverter
) and the first power supply line, and is connected between the constant voltage (V
A TTL/MOS level conversion circuit characterized by comprising an n-channel MOS transistor (Q3) which becomes normally on state in response to _0). 2. The n-channel MOS transistor (Q2) of the complementary MOS inverter and the second power supply line (Vss)
A p-channel MOS transistor (Q7) which is normally on in response to a constant voltage (Vss) is connected between the TTL/
MOS level conversion circuit. 3. The constant voltage applied to the gate of the p-channel MOS transistor (Q7) that is in the normally on state is directly supplied from the power supply pad (P) for the second power supply line. TTL/MO according to item 2
S level conversion circuit. 4. Instead of the p-channel MOS transistor (Q7) which is in the normally on state and the n-channel MOS transistor (Q2) of the complementary MOS inverter,
Claim 2 characterized in that an npn bipolar transistor (T1) responsive to a TTL level input signal is provided.
The TTL/MOS level conversion circuit described in . 5. The TTL/MOS level conversion circuit according to claim 2, wherein an npn bipolar transistor (T2) is provided in place of the n-channel MOS transistor (Q3) which is in the normally on state.