JPH03136481A - Ccd driving circuit - Google Patents

Abstract

PURPOSE:To obtain a three-times waveheight value to a power supply potential at a maximum and to obtain the clock pulses of the two waveheight values by providing first-third switching circuits and first and second clamp circuits. CONSTITUTION:The clock pulse to be applied from a first switching circuit 20 is clamped to the first potential by a first clamp circuit 50 and applied through an emitter follower circuit to a second clamp circuit 60. The potential of the clock pulse is lowered to a ground potential and a prescribed potential at specified timing by second and third switching circuits 30 and 40. Accordingly, the first waveheight value is set in the first clamp circuit 50 and the second waveheight value is set in the third switching circuit 40. Then, a reference value is set in the second switching circuit 30 and the clock pulses with the two kinds of the waveheight values are obtained from the second clamp circuit 60. Thus, the plural waveheight values are obtained to a single power source and the clock pulse of more than double potential to the power supply potential can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention relates to a CC camera used in a solid-state imaging device such as a television camera.
D relates to a CCD drive circuit that supplies clock pulses to a solid-state image sensor.

(B) Conventional technology Conventionally, in imaging devices such as television cameras using CCD solid-state imaging devices, it has been considered to electronically control exposure by utilizing the operating principle of COD. In JP-A No. 63-24764, the photocharges accumulated in the imaging section are transferred and discharged during the photoelectric conversion period of each vertical scanning period, and the photocharges obtained during the remaining photoelectric conversion period are accumulated to generate video information. It has been shown that it can be obtained. Therefore, by setting the photocharge discharge timing according to the signal level output from the COD, the photoelectric conversion period is controlled to expand or contract according to the exposure state of the CCD.

In such exposure control means, one of the challenges is to efficiently discharge unnecessary photocharges. In addition, a method of draining by applying a high voltage to the substrate in a COD called a vertical overbroad drain structure has been considered.

FIG. 3 is a sectional view of the main part of the CCD, showing the state of the internal potential.

An N-type channel region (2) is formed on a P-type Si substrate (1).
) are provided separated from each other by a channel isolation region (3) by LOGO5. An N-type overbroad in (4) is provided in the channel separation region (3) and is configured to receive photocharges overflowing from the channel region (2). Further, a transfer electrode (6) is formed on the channel region (2) via an insulating film (5),
Furthermore, an insulating film (7) is formed covering the transfer electrode (6).

In such a CCD, when storing photocharges, the gate electrode (6) is fixed at a high potential and the overflow drain (4) is fixed at a low potential, and the channel region (6) is fixed at a low potential as shown by the solid line in FIG. 2) A potential well is formed,
Photocharges are accumulated in this potential well. and,
When transferring photocharges, a clock pulse is applied to the gate electrode (6), and an overflow drain (4) is provided to prevent photocharges from leaking to the overflow drain (4) during the transfer process. , a lower potential is applied than during photocharge accumulation.

On the other hand, when discharging photocharges, the overbroad drain <4> is set to an extremely high potential, for example, 3 times the potential applied to the gate electrode (6) during accumulation, and the gate electrode (6) is The potential barrier between the channel region (2) and the overbroad drain (4) is eliminated as shown by the broken line in FIG.
) is discharged to the overflow drain (4).

According to such a method of discharging photocharges, the photocharges of the imaging section can be discharged simultaneously and in an extremely short time, compared to a method of discharging photocharges using reverse direction transfer.
There is little influence on the signal output from the CCD.

As mentioned above, in order to sufficiently discharge the photocharges in the channel region (2) to the overflow drain (4), it is necessary to apply an extremely high potential of 30 V or more to the overflow drain (4). A drive circuit that generates pulses is required. Incidentally, these CCD drive circuits are generally driven by a power supply of about 16V, so when attempting to obtain a potential of 30V or more, for example, a lamp circuit as shown in FIG. 4 is used.

This clamp circuit consists of a diode (11) connected from the power supply to the output side, a resistor (12) connected in parallel with this diode (11), and a capacitor (13) connected to the output side of the diode (11). A switching circuit is connected to the other end of this capacitor (13). The switching circuit has an emitter grounded, a collector connected to the power supply via a resistor (14), and a base connected to a resistor (14).
5) to which a timing pulse TP is applied via a transistor (16). This switching circuit switches the transistor <16> according to the timing pulse TP.
turns on and off, the power supply potential vDD and the ground potential V
Operates with SS. That is, when the transistor (16) is off, the potential on the collector side of the transistor (16) is V ss, and when the transistor (16) is on, the potential on the collector side of the transistor (16) is up to V ss. A clock pulse CKA which is lowered and repeats the vDIl level and VSS level according to the timing pulse CP as shown in FIG. 5 is applied to the connection point A between the clamp circuit and the switching circuit.

The clamp circuit clamps the potential applied to point A to VDD when it becomes less than the clamp potential v0, and clamps the potential of VSS to VDD for the clock pulse CKA in Fig. 5. do. For the potential of vo of clock pulse CKA, vDD and V
The potential difference (4) with SS is superimposed on the clamp potential, and a lock pulse CKot+t is output as shown in FIG.

For example, when driving VDD with 16V, V, . . . as Ov, a 32V clock pulse can be obtained based on 16. The potential of this clock pulse is vo
and■5. It can be set variably by changing the value of
Variable setting can also be achieved by changing the clamp potential of the clamp circuit, for example by providing a variable resistor on the power supply side of the diode (11) and resistor (12).

(8) Problems to be solved by the invention However, when using the clamp circuit as described above,
Although it is possible to obtain a high potential of 30 V or more, it is not possible to obtain clock pulses having multiple peak values.

Normally, different potentials are applied to the overflow drain (4) of a CCD during the accumulation and discharge of photocharges as well as during transfer, so by providing multiple lamp circuits and power supplies as described above, the respective potentials can be adjusted. configured to obtain clock pulses.

Further, the highest potential of the clock pulse is twice the power supply potential, and for example, when VDD is 16V, the maximum value is 32V. However, when discharging photocharges, it is desired to apply a potential twice or more than that during accumulation to the overbroad drain <4>, and a sufficient potential cannot be obtained with the simple combination of clamp circuits as described above.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a CCp drive circuit that can obtain a plurality of peak values for a single power supply and also obtain a clock pulse having a potential twice or more of the power supply potential.

(d) Means for Solving the Problems The present invention was made to solve the above-mentioned problems. a switching circuit; a first clamp circuit that clamps the output of the first switching circuit to a first potential between a ground potential and a power supply potential;
an emitter follower circuit that receives the output of the first clamp circuit; a second switching circuit that lowers the input potential on the base side of the emitter follower circuit to the ground potential according to a second timing pulse;
a third switching circuit that lowers the potential from the ground potential to a second potential between the first potential according to a timing pulse of
a second clamp circuit that clamps the output of the emitter follower circuit to a third potential between the ground potential and the power supply potential;
The clock pulse is characterized in that it generates a clock pulse having first and second peak values based on the first and second potentials and a reference value depending on the third potential.

(*) Effect According to the present invention, the clock pulse given from the first switching circuit is clamped to the first potential by the first clamp circuit, and the clock pulse after clamping is passed through the emitter follower circuit to the second potential. The potential of the clock pulse is applied to the clamp circuit, and the potential of the clock pulse is lowered to the ground potential and a predetermined potential at specific timing by the second and third switching circuits. Therefore, the first clamp circuit sets the first peak value, the third switching circuit sets the second peak value, the second switching circuit sets the reference value, and the clock pulse has two types of peak values. is the second
obtained from the clamp circuit.

(f) Example Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a CCD driving circuit according to the present invention. This COD drive consists of first to third switching circuits (20) (30) (40), first and second clamp circuits (50) (60), and a voltage dividing circuit (7o),
First to third timing pulses TP,,'rP,,T
Pj and clock pulse CK. Generate LIT.

The first switching circuit (2o) has a pair of transistors (21) and (22) connected in series between a power supply and a ground point, and a capacitor (23) ( 24) can be connected to each other. Also, between the base and emitter of the transistors (21) and (22),
A diode (25
)(26) are connected. And the capacitor (23)
(24) A first timing pulse TP is commonly applied to the other end via a resistor (27). Therefore, with respect to the falling edge of the first timing pulse TPl shown in FIG. D rises and conversely, from vDD to V with respect to the rise of the first timing pulse TP.
Generates a falling clock pulse to SS.

The first clamp circuit (50) has the same configuration as the clamp circuit shown in FIG. 4, including a diode 51) and a resistor (52).
and a capacitor (53). This clamp circuit (
50) clamps the clock pulse given from the first switching circuit (20) to a first clamp potential V from a voltage dividing circuit (70), which will be described later.

Therefore, the potential of VIIS is clamped to vl, and as shown in FIG. 2, the timing of the rise of timing pulse TP is V17! J”) V I+ Vo(V, I=
VDD V3. ) is applied to point A shown in FIG.

The second switching circuit (30) includes a transistor (30).
The emitter of 1) is grounded, and a second timing pulse TP is applied to the base via a resistor (32). Further, the collector of the transistor (31) is connected to the output (point A) of the first clamp circuit (50) via a resistor (33), and receives the second timing pulse TP.

Accordingly, point A is grounded in terms of the circuit. This second timing pulse TP is synchronized with the first timing pulse TP, and the transistor (31) is turned on except between the rising edge and the falling edge of the clock pulse CKA. The potential on the collector side (point B) is lowered to VSS.

On the other hand, in the third switching circuit (40), the emitter of the transistor (41) is grounded via a variable resistor (42), and the third timing pulse TP is applied to the base via a resistor (43). At the same time, the collector is connected to point B. Third timing pulse TP.

has a phase opposite to that of the second timing pulse TP, and turns on the transistor (41) during the period from the fall to the rise of the second timing pulse TPz. When the transistor (41) is turned on, the potential at point B is lowered according to the resistance value of the variable resistor (42). In the second switching circuit (30), a transistor (
Since the emitter of 31) is directly grounded, when the transistor (31) is turned on, the potential at point B is lowered to Vss, whereas when the transistor (41) is turned on, the resistance value of the variable resistor (42) is lowered. V is lowered to a potential higher than Vss by the voltage drop caused by Vss. Therefore, as shown in FIG. 2, from the rise to the fall of the third timing pulse TP, it becomes v3, and the clock pulse CK
A clock pulse CK that becomes V, +V from the rise to the fall of A is obtained from point B.

This point B is a transistor with an emitter-follower connection (
connected to the base of this transistor (80)
The emitter of is connected to the second clamp circuit (60).

The second clamp circuit (60) is connected to the first clamp circuit (
Same configuration as 50), diode (61), resistor (62)
) and a capacitor (63), and a voltage dividing circuit (70)
to the diode (61) and the resistor (62) to the second clamp potential V! is given. Therefore, the clamp circuit (60
) clamps the VSS level of clock pulse CK, to V, and outputs clock pulse CKOUa.

The voltage dividing circuit (70) is composed of variable resistors (71) (72) and capacitors <73> (74), and divides vDD into first and second clamp potentials V, , V, respectively. generating first and second clamp circuits (50) (60)
give to That is, since the reference level and peak value of the clock pulse CKout are determined by the first and second clamp levels VV, in addition to the resistance values of the variable resistors (71) and (72), the third switching circuit (40) variable resistance (42
) by changing the resistance value of clock pulse C
Each level of Kout is variably set.

For example, the peak value of the clock pulse CKOUT obtained according to the first timing pulse TP is vl+v, +
Since there is v14te and the reference value is v, vDD is set to 16
When V and Vss are Ov, ■ and V are 0 to
By changing between 16V, the reference value is 0 to 16V1
The peak value can be continuously varied between 16 and 48V.

Further, since the clock pulse CKOUT obtained according to the third timing pulse CP3 has a peak value of V, +V, by changing the value of the variable resistor (42) from 0 to oo, ■, ~V, +V, It can be set continuously between +V and +I.

By the way, in FIG. 2, the first and third timing pulses TP, , TP are shown to operate alternately, but in reality, when discharging photocharges from the imaging section of the CCD, The third timing pulse TPs is fixed at a low level and only the first and second timing pulses TP, , TP1 are changed, and when transferring photocharges, the first timing pulse TP is fixed at a high level. By providing only the second and third timing pulses TP* and TP, clock pulses CK out and CCD having the same peak value can be obtained.
The operation is controlled so as to supply the

(g) Effects of the Invention According to the present invention, it is possible to obtain a clock pulse having a maximum peak value three times the power supply potential and having two peak values. This type of CCD drive circuit can generate clock pulses applied to the overflow drain and the clock pulses applied to the vertical overflow drain type COD substrate from a single power supply, so the power supply circuit can be simplified. As a result, the circuit scale of the drive circuit can be reduced, and it is possible to reduce the size and weight of the imaging device as well as to reduce the cost.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the CCD drive circuit of the present invention, Fig. 2 is a waveform diagram explaining the operation of Fig. 1, Fig. 3 is a block diagram showing the configuration of the solid-state imaging device, and Fig. 4 is a cross section of the CCD. FIG. 5 is a circuit diagram of a clamp circuit used in a conventional CCD drive circuit. (20)<30)(40)...switching circuit,
(21)(22)(31)(41)...Transistor, (42)...Variable resistor, (50)(60)...
Clamp circuit, (51) (61)...diode,
(53) (63)... Capacitor, (70)...
・Voltage divider circuit, (71) (72)...variable resistance.

Claims (2)

[Claims] (1) A first switching circuit that opens and closes between a power supply potential and a ground potential according to a first timing pulse; A first switching circuit that clamps the output of this switching circuit to a first potential between the ground potential and the power supply potential. an emitter follower circuit that receives the output of this clamp circuit; a second switching circuit that lowers the input potential on the base side of this emitter follower circuit to the ground potential according to a second timing pulse; a third switching circuit that clamps the output of the emitter follower circuit to a third potential between the ground potential and the power supply potential according to a timing pulse of the ground potential to a second potential between the ground potential and the first potential; A clamp circuit, characterized in that it generates a clock pulse having first and second peak values based on the first and second potentials and a reference value depending on the third potential. CCD drive circuit. (2) Claim 1 further comprising power supply means for setting the first and third potentials between a ground potential and a power supply potential, respectively, and supplying the first and second clamp circuits with the power. CCD drive circuit described in Section 1.