JP2645898B2 - CCD drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial application field The present invention relates to a CC used in a solid-state imaging device such as a television camera.
The present invention relates to a CCD drive circuit that supplies a clock pulse to a solid-state imaging device.

(B) Conventional technology Conventionally, in an imaging apparatus such as a television camera using a CCD solid-state imaging device, it has been considered to perform electronic exposure control by utilizing the operation principle of the CCD. For example,
In Japanese Patent Application Laid-Open No. 63-24764, in the middle of a photoelectric conversion period for each vertical scanning period, the photoelectric charges accumulated in the imaging unit up to that time are transferred and discharged, and the photoelectric charges obtained in the remaining photoelectric conversion periods are accumulated to obtain video information. It has been shown. Therefore, by setting the discharge timing of the photocharge according to the signal level output from the CCD, the photoelectric conversion period is controlled to expand and contract according to the exposure state of the CCD.

One of the issues with such an exposure control means is to efficiently discharge unnecessary photocharges. One method is to transfer and discharge photocharges in the opposite direction, or a high voltage is applied to the overflow drain to discharge the photocharges. In addition, a method of applying a high voltage to a substrate and discharging the substrate in a CCD called a vertical overflow drain structure has been considered.

FIG. 3 is a cross-sectional view of a main part of the CCD, showing the state of internal potential.

On a P-type Si substrate (1), an N-type channel region (2) is provided separated from each other by a channel separation region (3) based on LOCOS. An N ⁺ -type overflow drain (4) is provided in the channel isolation region (3), and is configured to receive photocharges overflowing from the channel region (2). A transfer electrode (6) is formed on the channel region (2) via an insulating film (5).
Further, an insulating film (7) is formed to cover the transfer electrode (6).

In such a CCD, when accumulating photocharge, the gate electrode (6) is fixed at a high potential and the overflow drain (4) is fixed at a low potential, and as shown by the solid line in FIG. 2) A potential well is formed,
Photocharges are accumulated in this potential well. And
In the case of driving the transfer of the photocharge, a clock pulse is applied to the gate electrode (6) and the photocharge is prevented from leaking to the overflow drain (4) during the transfer process to the overflow drain (4). A lower potential is applied than during the accumulation of photocharges.

On the other hand, when the photocharge is discharged, the overflow drain (4) is set to an extremely high potential, for example, three times the potential applied to the gate electrode (6) during accumulation, and the gate electrode (6) is set to a low potential. The channel region (2) and the overflow drain (4) as shown by the broken line in FIG.
And the photocharge in the channel region (2) is discharged to the overflow drain (4).

According to such a method of discharging the photocharges, the photocharges of the imaging unit can be discharged simultaneously and in a very short time, so that the output from the CCD is smaller than the method of discharging the photocharges by the reverse transfer. The influence on the signal to be performed is small.

As described above, in order to sufficiently discharge the photocharge of the channel region (2) to the overflow drain (4), it is necessary to apply an extremely high potential of 30 V or more to the overflow drain (4). A driving circuit for generating a pulse is required. By the way, these
Since the driving circuit of the CCD is generally driven by a power supply of about 16 V, a clamp circuit as shown in FIG. 4 is used to obtain a potential of 30 V or more, for example. This clamp circuit consists of a diode (11) connected from the power supply to the output side, a resistor (12) connected in parallel with this diode (11), and a capacitor (13) connected to the output side of the diode (11). The switching circuit is connected to the other end of the capacitor (13). The switching circuit is
It comprises a transistor (16) whose emitter is grounded, whose collector is connected to a power supply via a resistor (14), and whose base receives a timing pulse TP via a resistor (15). This switching circuit operates between the power supply potential V _DD and the ground potential V _SS by turning on / off the transistor (16) according to the timing pulse TP. That is, when the transistor (16) is off, the potential on the collector side of the transistor (16) becomes V _DD , and when the transistor (16) is on, the potential on the collector side of the transistor (16) reaches V _SS. cuts are to provide a clock pulse CK _a repeating the V _DD level and V _SS level in accordance with the timing pulse CP as shown in FIG. 5 to the connection point a between the clamp circuit and the switching circuit.

Clamp circuit, the potential applied to the point A, when it comes to less V _DD of the clamp potential, intended to clamp the potential V _DD, V the potential of V _SS is the clock pulse CK _A of FIG. 5 Clamp to _DD . Then, the clock pulse CK _A
With respect to the potential of V _DD, the potential difference V _H between V _DD and V _SS is superimposed on the clamp potential, and the clock pulse as shown in FIG.
Outputs CK _OUT . For example, in the case of driving the V _DD 16V, the V _SS as 0V may be obtained clock pulses 32V relative to 16V. The potential of this clock pulse is V _DD
And can be variably set by changing the value of V _SS and by changing the clamp potential of the clamp circuit, for example, by providing a variable resistor on the power supply side of the diode (11) and the resistor (12). .

(C) Problems to be Solved by the Invention However, when the above-described clamp circuit is used, a high potential of 32 V or more can be obtained, but a clock pulse having a plurality of peak values cannot be obtained. Usually, the CCD overflow drain (4)
Since different potentials are given at the time of transfer as well as at the time of accumulation and discharge of photocharges, a clock pulse of each potential is obtained by providing a plurality of clamp circuits and power supplies as described above.

The maximum potential of the clock pulse is twice the power supply potential. For example, when V _DD is 16 V, the maximum value is 32 V. However, it is desired to apply a potential twice or more as high as that at the time of accumulation to the overflow drain (4) at the time of discharging the photoelectric charge, and a sufficient potential cannot be obtained by a simple combination of the clamp circuits as described above.

Therefore, an object of the present invention is to provide a CCD drive circuit capable of obtaining a plurality of peak values for a single power supply and obtaining a clock pulse having a potential twice or more the power supply potential.

(D) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and has a first switching for opening and closing between a power supply potential and a ground potential in accordance with a first timing pulse. A first clamp circuit for clamping an output of the first switching circuit to a first potential between a ground potential and a power supply potential; an emitter follower circuit receiving an output of the first clamp circuit; a base of the emitter follower circuit A second switching circuit for lowering the input potential on the side to ground potential according to a second timing pulse, and the input potential on the base side from the ground potential to the first potential in accordance with a third timing pulse;
A third switching circuit for lowering the output of the emitter follower circuit to a second potential between the ground potential and a third potential between the ground potential and the power supply potential; And generating a clock pulse having first and second peak values based on the second potential and a reference value according to the third potential.

(E) Operation According to the present invention, the clock pulse supplied from the first switching circuit is clamped to the first potential by the first clamp circuit, and the clock pulse after the clamp is applied to the second clock via the emitter follower circuit. While being supplied to the clamp circuit, the potential of the clock pulse is reduced to the ground potential and a predetermined potential at a specific timing by the second and third switching circuits. Therefore, a first peak value is set in the first clamp circuit, a second peak value is set in the third switching circuit, a reference value is set in the second switching circuit, and a clock pulse having two types of peak values is set. From the second clamp circuit.

(F) Example An example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a CCD drive circuit according to the present invention. The CCD driving is performed by the first to third switching circuits (20), (30), (40), the first and second clamp circuits (5
0) (60) and a voltage dividing circuit (70).
TP ₁ , TP ₂ , and TP ₃ to generate a clock pulse CK _OUT .

The first switching circuit (20) includes a pair of transistors (21) and (22) connected in series between a power supply and a ground point, and a capacitor (23) ( 24) are connected respectively. Diodes (25) and (26) are connected between the base and emitter of the transistors (21) and (22) in the forward direction with respect to the polarity of the transistors. Then, the capacitor (23) (24) to the other end first timing pulse TP ₁ is commonly supplied to via a resistor (27). Therefore, V from a first timing pulse TP rising from the ground potential V _SS against falling to the power supply potential V _DD of _1, V _DD to the first rising edge of the timing pulse TP ₁ Conversely shown in Figure 2 Generates a clock pulse falling to _SS .

The first clamp circuit (50) has the same configuration as the clamp circuit shown in FIG. 4, and includes a diode (51), a resistor (52), and a capacitor (53). This clamp circuit (50)
Is first clamped to the clamp voltage V ₁ of the voltage divider circuit described later clock pulses generated by the first switching circuit (20) (70). Therefore, the potential of V _SS is clamped to V ₁ and the timing pulse TP is set as shown in FIG.
₁ of rise of V from V ₁ at the timing _{1 + V H (V H =} V DD -
The clock pulse CK _A stand amounts to V _SS) is supplied to a point A shown in Figure 1.

The second switching circuit (30) includes a transistor (3
1 emitters of) is grounded, the second timing pulse TP ₂ is applied through a resistor to the base (32). The collector of the transistor (31) is connected to the first through a resistor (33).
Is connected to the output (point A) of the clamp circuit (50)
Circuit to ground the point A of the in accordance with the timing pulses TP _2. The second timing pulse TP ₂ is synchronized with the first timing pulse TP _1, the transistor (31) is made to turn on the rising edge of the clock pulse CK _A except during falling, transistor (31) potential of the collector side (point B) is pulled down to V _SS. On the other hand, in the third switching circuit (40), the emitter of the transistor (41) is grounded via the variable resistor (42), and the resistor (43) is connected to the base.
And the collector is connected to the point B while the third timing pulse TP ₃ is applied. Third timing pulse TP ₃ has a second timing pulse TP ₂ and opposite phase, to the on-period to the transistor (41) from the second falling edge of the timing pulse TP ₂ to rise. When the transistor (41) is turned on, the potential at the point B is reduced according to the resistance value of the variable resistor (42). Is In the second switching circuit (30), whereas since the emitter of the transistor (31) is grounded directly, the potential at the point B when the transistor (31) is turned on is pulled down to V _SS, Variable resistance (42) when transistor (41) turns on
By the voltage drop due to the resistance value is lowered to V _SS than the high potential V _3. Therefore, V ₃ becomes between the third rising edge of the pulse TP ₃ the as shown in Figure 2 to the fall,
V ₁ + V from the rise of the clock pulse CK _A and before falling
Obtain a clock pulse CK _B which becomes _H from point B.

This point B is connected to the base of an emitter-follower-connected transistor (80), and the emitter of this transistor (80) is connected to the second clamp circuit (60).

The second clamp circuit (60) has the same configuration as the first clamp circuit (50), and includes a diode (61), a resistor (62), and a capacitor (63). ), a second clamping potential V ₂ is applied to the resistor (62). Therefore, the clamp circuit (60) clamps the V _SS level of the clock pulse CK _B to V ₂ and
Outputs CK _OUT .

The voltage dividing circuit (70) is composed of variable resistors (71) and (72) and capacitors (73) and (74). The voltage dividing circuit (70) divides V _{DD, respectively,} to generate first and second clamp potentials V ₁ and V _2. Is generated and supplied to the first and second clamp circuits (50) and (60). That is, since the reference level and peak value of the clock pulse CK _OUT are determined by the first and second clamp levels V ₁ and V ₂ , the third switching is performed in addition to the resistance values of the variable resistors (71) and (72). Each level of the clock pulse CK _OUT is variably set by changing the resistance value of the variable resistor (42) of the circuit (40).

For example, the peak value of the clock pulse CK _OUT obtained according to the first timing pulse TP ₁ is V ₁ + V ₂ + V _H and the reference value is V ₂ , so that V _{DD is set} to 16 V and V _{SS is set} to 0 V. If the V ₁ and V ₂ by changing between 0～16V, reference value 0～16V, wave height can be continuously variably set between 16～48V. Further, since the peak value of the clock pulse CK _OUT obtained according to the third timing pulse CP ₃ is V ₂ + V ₃ , by changing the value of the variable resistor (42) from 0 to ∞, V _{2 to} V ₁ + it can continuously variably set in until V ₂ + V _H.

By the way, FIG. 2 shows that the first and third timing pulses TP ₁ and TP ₃ operate alternately.
Actually, given only the third change of the timing pulse TP ₃ the first and second timing pulses TP and fixed to a low level _1, TP ₂ is when discharging the photocharge of the CCD of the imaging section, the light the second and third timing pulse TP ₂ by fixing the first timing pulse TP ₁ to high level when transferring charge,
By providing only TP _3, operation is controlled so as to supply a clock pulse CK _OUT of uniform respective peak value to the CCD.

(G) Effects of the Invention According to the present invention, a clock pulse having a peak value three times the power supply potential at the maximum and two peak values can be obtained. Such a CCD drive circuit can generate a clock pulse applied to the overflow drain and a clock pulse applied to the substrate of the vertical overflow drain type CCD from a single power supply, simplifying the circuit of the power supply part. The circuit scale of the drive circuit can be reduced,
It is possible to reduce the size and weight of the imaging device and to reduce the cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a CCD drive circuit of the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a block diagram showing a configuration of a solid-state imaging device, and FIG. FIG. 5 is a circuit diagram of a clamp circuit used in a conventional CCD drive circuit. (20) (30) (40) Switching circuit (21) (2
2) (31) (41) ... Transistor, (42) ... Variable resistor, (50) (60) ... Clamp circuit, (51) (61) ...
Diode, (53) (63)… Capacitor, (70) ……
Voltage divider circuit, (71) (72) ... variable resistor.

Claims (2)

(57) [Claims] 1. A first switching circuit that opens and closes between a power supply potential and a ground potential according to a first timing pulse, and clamps an output of the switching circuit to a first potential between the ground potential and the power supply potential. A first clamp circuit, an emitter follower circuit receiving an output of the clamp circuit, a second switching circuit for lowering an input potential on a base side of the emitter follower circuit to a ground potential according to a second timing pulse, A third switching circuit for lowering the ground potential to a second potential between the first potentials in accordance with a third timing pulse, and clamping an output of the emitter follower circuit to a third potential between the ground potential and the power supply potential A second clamp circuit, wherein the first and second peak values based on the first and second potentials and CCD drive circuit, characterized in that for generating a clock pulse having the third and a reference value corresponding to the potential. 2. A power supply means for setting the first and third potentials between a ground potential and a power supply potential and supplying the first and third potentials to the first and second clamp circuits. 2. The CCD driving circuit according to claim 1.