JPH03136116A - Clock supply device - Google Patents

Abstract

PURPOSE:To secure the minimum pulse width so that a malfunction does not occur by providing a clock frequency dividing circuit for supplying a frequency dividing clock which does not break down a phase relation of a clock output control circuit and its fundamental clock, in the case abnormality is generated in a master clock pulse. CONSTITUTION:A clock output control circuit 16 is operated, based on a fault notice from a fault detecting circuit 15, and in the case abnormality is generated in a pulse of a master clock generator 11, a master clock gate 13 is closed and a signal level on a fundamental clock bus 9 is set to a high level. Subsequently, a prescribed signal level transition of a slave clock pulse generated by a slave clock generator 12 is detected and a slave clock gate 14 is opened, and it is started to sent out a clock pulse to the fundamental clock bus 9. In such a way, by securing the minimum pulse width of the clock pulse, and also, bringing clock on the fundamental clock bus to frequency division by a frequency dividing circuit 19, and generating a frequency dividing clock, a phase relation to a fundamental clock is held, and a processor comes not to cause a malfunction.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a clock supply device that supplies clock pulses to a multiprocessor system in which a plurality of processors are interconnected via a common bus.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional clock supply device disclosed in, for example, Japanese Unexamined Patent Publication No. 175913/1983. In the figure, 1a to 1n are a plurality of processor units constituting a multiprocessor system, and 2 is a clock bus through which clock pulses supplied to each processor unit Ia to 1n are transmitted. In addition, within each processor unit 1a to ln, 3
Numerals a to 3n are clock generators that generate clock pulses, and 4a to 4n are failure detection circuits that detect abnormalities in the clock pulses generated by the clock generators 3a to 3n. 5a to 5n are clock gates that control output of clock pulses generated by the clock generators 3a to 3n to the clock bus 2:@. 6a to 6n are processors of each of the processor units 1a to 1n, which operate in response to clock pulses supplied via the clock bus 2. Reference numeral 7 indicates that the fault detection circuits 4a to 4n in each processor unit 1a to 1n generate control signals for opening and closing the clock buses 5a to 5n based on the fault notification generated when an abnormality in the clock pulse is detected. processor unit)
Clock generator 3a (3b~3) in la (lb~in)
The clock pulses generated by n) are connected to the clock bus 2.
This is the controller that sends out the data. Next, the operation will be explained. Each processor unit 1a
-1n, clock pulses are generated by each of the clock generators 3a-3n, and the generated clock pulses are input to the respective failure detection circuits 4a-4n and clock gates 5a-5n. Here, the controller 7 normally turns on only the control signal to the clock gate 5a of the processor unit, for example, the processor unit la. Therefore, only the clock gate 5a in the processor unit la is opened, and the clock pulses generated by the clock generator 3a are sent to the clock bus 2. Each processor unit 1a to 1n
The processors 6a to 6n operate in response to clock pulses sent to the clock bus 2 from the clock generator 3a. In this state, if an abnormality occurs in the clock pulses generated by the clock generator 3a, the fault detection circuit 4a detecting the abnormality generates an abnormality notification and sends it to the controller 7. Upon receiving this abnormality notification, the controller 7 turns off the control signal to the processor unit 1a, and turns on the control signal to other processor units, for example, the processor unit 1b. This closes the clock gate 5a and opens the clock gate 5b instead. Therefore, clock pulses are sent to the clock bus 2 from the clock generator 3b in place of the failed clock generator 3a. Processors 6a-6n of each processor unit 1a-In operate in response to clock pulses sent to clock bus 2 from clock generator 3b.

[Problem to be solved by the invention]

Since the conventional clock supply device is configured as described above, the clock pulses generated by each of the clock generators 3a to 3n are not synchronized, and the failed clock generator 3a is replaced with another normal clock. When switching to the generator 3b, there is a problem that the width of the clock pulse at high level or low level may not satisfy the specified minimum pulse width, which may cause the processors 6a to 6n to malfunction. Ta. The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a clock supply device that ensures a minimum pulse width of clock pulses and does not cause malfunctions of a processor.

[Means to solve the problem]

The clock supply device according to the present invention includes a master clock generator and a slave clock generator, and when an abnormality occurs in the clock pulses generated by the master clock generator, the clock pulses generated by the master clock generator are passed through. After closing the master clock gate that controls the clock bus and setting the signal level on the basic clock bus to high level,
A clock output control circuit is provided that detects a predetermined signal level transition of a clock pulse generated by a slave clock generator and opens a slave clock gate that controls passage of the clock pulse generated by the slave clock generator. .

[For use]

When the clock output control circuit in this invention receives a failure notification from the failure detection circuit, it closes the master clock gate, prohibits the sending of the clock pulses generated by the master clock generator to the basic clock bus, and also prevents the slave clock generator from transmitting the clock pulses generated by the master clock generator to the basic clock bus. The slave clock gate is opened by detecting a predetermined signal level transition of the clock pulse generated by the device, such as high level → low level → high level, and sends the clock pulse generated by the slave clock generator to the basic clock bus. By starting the clock pulse, it is possible to realize a clock supply device that ensures the minimum pulse width of the clock pulse and prevents the processor from malfunctioning.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1a to 1n are processor units corresponding to the conventional processor units given the same reference numerals as in FIG. 3, and 6a to 6n are processor units 1a to ln.
This is the processor within. 8 is this processor 6a-6n
9 is a basic clock bus for transmitting the basic clock pulses, and 10 is a divided clock bus for transmitting the divided clock pulses. Further, in the clock supply device 8, 11 is a master clock generator that generates a master clock pulse;
12 is a slave clock generator that generates slave clock pulses. 13 is a master clock gate that sends the master clock pulse generated by the master clock generator 11 to the basic clock bus 9 as a basic clock pulse, and 14 is a master clock gate that sends the slave clock pulse generated by the slave clock generator 12 as a basic clock pulse. This is a slave clock gate that sends out to the basic clock bus 9. Reference numeral 15 denotes a failure detection circuit that receives master clock pulses generated by the master clock generator 11 and detects abnormalities therein. 16 operates based on the failure notification from the failure detection circuit 15, and when an abnormality occurs in the master clock pulse generated by the master clock generator 11, the master clock gate 13 is closed and the signal on the basic clock bus 9 is The level is set to a predetermined level, that is, a high level, and then a predetermined signal level transition of the slave clock pulse generated by the slave clock generator 12 is detected, for example, a signal level transition from high level to low level to high level, This is a clock output control circuit that opens the slave clock gate 14. 17 and 18 are this clock output control circuit 16
If the master clock gate 13 is closed by
This is a DC power supply and a resistor for setting the signal level on the basic clock bus 9 to the high level. Reference numeral 19 denotes a clock frequency dividing circuit that takes in and frequency-divides the basic clock pulse transmitted on the basic clock bus 9, generates a predetermined frequency-divided clock pulse, and sends it to the frequency-divided clock bus 10. Next, the operation will be explained. Here, FIG. 2 is a time chart showing the states of each signal for explaining the operation. Within the clock supply device 8, a master clock generator 11
and slave clock generator 12 independently generate master clock pulses or slave clock pulses of the same frequency. These master clock pulses and slave clock pulses are supplied to the basic clock bus 9 as basic clock pulses via the master clock gate 13 or the slave clock gate 14. Here, during normal operation, the clock output control circuit 16 turns on the control signal to the master clock gate 13 and turns off the control signal to the slave clock gate 14. Therefore, only the master clock gate 13 is opened, and the master clock pulse from the master clock generator 11 is supplied to the basic clock bus 9 as a basic clock pulse. Further, the basic clock pulse sent to the basic clock bus 9 is taken into the clock frequency dividing circuit 19, frequency-divided to a predetermined frequency, and sent to the frequency-divided clock bus 10 as a frequency-divided clock pulse. Processor 6a in each processor unit 1-1a to In
~6n receives the basic clock pulse and the frequency-divided clock pulse from the basic clock bus 9 and the frequency-divided clock bus 10, and executes a predetermined process 90. Here, the master clock pulse generated by the master clock generator 11 is also sent to the fault detection circuit 15.
The failure detection circuit 15 detects whether or not an abnormality has occurred. That is, when the fault detection circuit 15 detects an abnormality such as a stoppage of the master clock pulse as shown in FIG. 2(a), it generates a fault notification and sends it to the clock output control circuit 16. The clock output control circuit 16 that received the failure notification
As shown in Figure (b), the control signal to the master clock gate 13 is turned off and the master clock gate 13 is closed. When the master clock gate 13 is closed, there is no basic clock pulse supplied on the basic clock bus 9, so that the level of the basic clock bus 9 is changed by the voltage of the DC power supply 17 applied via the resistor 18. 2 The level becomes high as shown in Figure (e). The clock output control circuit 16 also receives slave clock pulses (see FIG. 2) generated by the slave clock generator 12.
C)) and monitor it. After setting the level of the basic clock bus 9 to a high level, the clock output control circuit 16 detects the transition of the signal level of the slave clock pulse from high level to low level to high level, and the signal level shown in FIG. 2(d) is detected. Turn on the control signal to slave clock gate 14 as shown. This opens the slave clock gate 14 and sends the slave clock pulse from the slave clock generator 12 to the basic clock bus 9, and the basic clock pulse on the basic clock bus 9 is changed as shown in FIG. 2(e). The minimum pulse width at high level and low level is fully satisfied. Further, such basic clock pulses on the basic clock bus 9 are taken into the clock frequency dividing circuit 19, frequency-divided, and sent to the frequency-divided clock bus 10 as frequency-divided clock pulses. Here, this clock frequency dividing circuit 19 is composed of, for example, a counter that changes at the rising edge of an input signal, and FIG. 2(f) shows a divided clock by the clock frequency dividing circuit 19 using a binary counter. Pulses are shown. By using the lock frequency divider circuit 19 as described above, it is possible to supply a divided clock pulse that satisfies the minimum pulse width without destroying the phase relationship with the basic clock pulse. Note that in the above embodiment, the processor units 18 to 1n
The basic clock pulse and the divided clock pulse are supplied from the clock supply bag W8, which is configured as a separate device from the above, but it is installed in the processor units Ia to ln and supplied from the processor unit. You can. In that case, the master clock pulse generation section and the slave clock pulse generation section may be installed in separate processor units (la to In), and failure notifications, control signals, etc. may be output onto the bus. These eliminate the need to separately incorporate the clock supply device 8 into the system. Further, in the above embodiment, a case has been described in which a clock frequency dividing circuit is provided and also generates divided clock pulses, but it is also possible to generate only basic clock pulses.
Furthermore, the frequencies of the master clock pulse and slave clock pulse do not necessarily have to be the same; by setting them to different frequencies and forcibly switching between the master clock pulse and slave clock pulse, each processor can The frequency of the supplied clock pulses can also be changed depending on the software or system status.

【Effect of the invention】

As described above, according to the present invention, when an abnormality is detected, the master clock gate is closed and transmission of the master clock pulse to the basic clock bus is prohibited, and a predetermined signal level transition of the slave clock pulse is detected. Now we have configured it to open the slave clock gate and send the slave clock pulses to the basic clock bus.
This has the effect of providing a clock supply device that can easily ensure the minimum pulse width of the clock pulses supplied to each processor unit and that can construct a highly reliable multiprocessor system.

[Brief explanation of the drawing]

3 4- Fig. 1 is a block diagram showing a clock supply device according to an embodiment of the present invention, Fig. 2 is a time chart showing the states of each signal, and Fig. 3 is a block diagram showing a conventional clock supply device. be. 8 is a clock supply device, 9 is a basic clock bus, 11 is a master clock generator, 12 is a slave clock generator, 13 is a master clock gate, 14 is a slave clock gate, 15 is a fault detection circuit, and 16 is a clock output control circuit. . In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A master clock generator and a slave clock generator that each independently generate clock pulses, a master clock gate that controls sending of the clock pulses generated by the master clock generator to a basic clock bus, and the slave clock generator. a slave clock gate for controlling transmission of clock pulses generated by the master clock generator to the basic clock bus; a failure detection circuit for detecting an abnormality in the clock pulses generated by the master clock generator; and a failure notification from the failure detection circuit. If an abnormality occurs in the clock pulses generated by the master clock generator, the slave clock generator closes the master clock gate and sets the signal level on the basic clock bus to a predetermined level. a clock output control circuit that detects a predetermined signal level transition of a clock pulse generated by a slave clock gate and opens the slave clock gate.