JPH03135109A - Semiconductor device - Google Patents

Abstract

PURPOSE:To simulate a function of a living body even when an input signal is either a digital signal or an analog signal by turning on a path transistor (TR) with an output signal to be inputted therethrough in relation to the output signal of a data latch amplifier circuit. CONSTITUTION:An H level input signal S1 given to a path TR 10 is given to an inverter 11, and an input level S2 goes to an H level and an output level goes to an L level and the path TR 10 is turned off. Then the input level S2 is gradually decreased via an internal resistor of an N-channel MOSFET 12 and the output level keeps an L level till the input level reaches a threshold level of the inverter 11 or the like thereby obtaining a dead band period when the device is not responsive even in the entry of the input signal S1. Thus, the input signal S1 is given to the inverter 11 even when the input signal is a digital signal or an analog signal and the non-response period is obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and more specifically, a semiconductor device that simulates the functions of a living body and is suitable for image processing devices such as character recognition and image recognition. This is what we propose.

[Conventional technology]

A neural membrane in a resting state responds nonlinearly to current stimulation, as shown by curve X in FIG. That is, only in response to an outward current stimulus that causes depolarization above the threshold potential, an electrical pulse of approximately constant amplitude, called an action potential or nerve impulse, is generated. The pulse width of the action potential is approximately 1
m5ec, which is significantly slower than the pulses used in typical digital electronic circuits.

Such action potentials are considered to be the basic signals that carry information in the brain, and the process of generating these action potentials is an active nonlinear phenomenon that occurs only when depolarization exceeds a threshold potential. Further, immediately after an action potential is generated, there is a period in which the threshold potential is higher than normal and it is difficult to generate the next action potential, that is, a refractory period.

Note that the response to stimulation below the threshold potential is as shown by curve Y.

By the way, semiconductor devices having the above-mentioned refractory period are described in, for example, "Design of Digital IC Circuits (written by Toshio Yuyama)" published by CG Publishing on March 20, 1988.
74, and FIG. 5 is its circuit diagram. An input signal S is input to one input terminal of the first NOR circuit 1, and its output is input to one input terminal of the second NOR circuit 4 via a capacitor 2 and a resistor 3.

The other input terminal of this NOR circuit 4 is given a ground potential. The NOR circuit 4 outputs an output signal 310 and also feeds back the output signal S16 to the other input terminal of the NOR circuit 1. The voltage of a DC power supply VIID is applied to the connection between the capacitor 2 and the resistor 3 via the resistor 5.

Next, the operation of this semiconductor device will be explained. When the input signal S becomes "H" level, the output of the NOR circuit 1 becomes "L" level and the capacitor 2 is discharged, the input signal of the NOR circuit 4 becomes "■, ° level" and its output signal becomes " Become H Lebel. After that, the capacitor 2 connects to the DC power source ■ via the resistor 5. After a period approximately equal to the time constant of capacitor 2 and resistor 5, N
The input signal of OR circuit 4 becomes H°“ level again and NOR
The output of the circuit 4 becomes "L" level. Also, the output signal S1° of the NOR circuit 4 is fed back to the NOR circuit 1. Then, from then on, when an "H" level input signal is input to the NOR circuit 1, The above-mentioned operation will be performed. After the human input signal S1 once reaches the 11H" level, until the time corresponding to the time constant has elapsed, the output signal S1 in response to the subsequent input signal Sl It does not produce any symptoms and has the refractory period mentioned above.

[Problem to be solved by the invention]

As mentioned above, the conventional semiconductor device uses a NOROR circuit in the input stage of the input signal, so when the input signal is a digital signal, a signal is obtained at the output side of the N0Ru path 1 by logic operation and the required signal is output. Movement provides a refractory period. However, if the input signal is an analog signal, NO
There is a problem in that a required signal cannot be obtained at the output side of the R circuit 1, and therefore a refractory period cannot be obtained.

In view of such problems, an object of the present invention is to provide a semiconductor device in which a signal can be obtained from the input stage of the input signal and a refractory period can be obtained, regardless of whether the human input signal is a digital or analog signal. shall be.

[Means to solve the problem]

A semiconductor device according to the present invention includes a pass transistor to which a signal is input, a data holding/amplifying circuit for holding and amplifying the output of the pass transistor, and seven output buffer circuits to which the output of the data holding/amplifying circuit is input. and a current refresh pass circuit capable of bringing the input J side of the data retention/amplification circuit to a predetermined potential, and configured to conduct the pass transistor in relation to the output signal of the data retention/amplification circuit. characterized by something.

[Effect]

The pass transistor holds the input signal as data.

Give it to the amplifier circuit. When the data holding and amplifying circuit holds the input signal, it turns off the pass transistor.

The current refresh path circuit sets the input side potential of the data retention and amplification circuit to a predetermined potential. The output buffer circuit outputs the input signal held by the data holding and amplifying circuit.

Thereby, the data holding/amplifying circuit holds the input signal regardless of whether the input signal is a digital or analog signal. Further, the period until the input terminal potential of the data retention and amplification circuit drops to a predetermined value is the refractory period.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to drawings showing embodiments thereof.

FIG. 1 is a circuit diagram of a semiconductor device according to the present invention. The input signal SI is input to the drain D of a pass transistor IO made up of an enhancement type MOSFET. A signal output from the source S of the pass transistor 10 is transmitted through an inverter 11 which is a data retention/amplification circuit and a depletion type N-channel MO3F which is a current refresh pass circuit.
Powered by ET12's drain D. N-channel MO
A ground potential is applied to the gate G and source S of the 5FET 12. The output signal of the inverter 11 is input to the gate G of the pass transistor 10 and the gate G of a P-channel MO5FET 13 serving as an output buffer. The output impedance of this P-channel type MO5FET 13 is selected to be a high value so that the influence of its output side does not appear on the pass transistor 10. P-channel type MOSFET1
A DC power supply van is connected to the drain D of 3, and an output signal is obtained from its source S.

The refractory period is equal to the gate capacitance of the inverter 11 and N
It is obtained by multiplying the internal resistance of the channel type MOSFET 12. N-channel type MO5FII! The internal resistance of TI2 is
A desired resistance value is selected by selecting the amount of dopant during ion implantation.

Next, the operation of the semiconductor device configured as described above will be explained with reference to FIG. FIG. 2 is a timing chart of output signals.

The input side potential St of the inverter 11 is an N-channel type MO
Since SFET 12 is connected to the ground potential through the internal resistance, it is at the "L11 level" as shown in FIG. 2(b), and the output side potential S3 of the inverter 11 is at the "L11 level" as shown in FIG.
As shown in the figure, it is at "H" level. As a result, the pass transistor 10 is turned on, while the p-channel MOSFET 13 is turned off.

Here, as shown in FIG. 2(a), when the "H" level human input signal S1 is applied to the pass transistor 10, the input signal SI is applied to the inverter 11, and the inverter
The input side potential S2 of 1 is H”° as shown in Fig. 2(b).
After a time delay for the inverter 11 to operate, its output side potential reaches the "L11 level" as shown in FIG. starts.Then, inverter 1
The input side potential S2 of 1 is the N-channel type MOSFET 12.
will gradually decrease through the internal resistance of The output side potential of the inverter remains at the "L" level until it becomes equal to or lower than the threshold potential vth of the inverter 11.

In this way, the input side potential of the inverter is the threshold potential vt
During the period above h, the "J,°" level output of the inverter 11 is input to the gate G of the pass transistor 10, so during that period the pass transistor 10 continues to be in the off state and cuts off the human input signal S1. Thereafter, when the input side potential S2 of the inverter 11 falls below the threshold potential vth, the output side potential S3 of the inverter 11 is inverted to H'' level with a delay of time for the inverter 11 to operate, and this inverts the P-channel type MO5FET 13 and pass transistor 1
0 to each gate G of P channel type MOS
Ff! T13 turns off at the time of L2 and outputs an output signal S of "°H'level" shown in FIG. turns on again and enters a standby state for inputting the subsequent input signal S1 to the inverter 11,
After that, the above-described operation is repeated. In that way,
The input terminal potential of the inverter 11 is an N-channel MOSFET.
During the period until the leakage current flowing through the internal resistance of ET12 drops below the threshold potential vth, even if an input signal S is generated, the pass transistor 10 blocks it and the output side potential of the inverter 11 is S, does not invert, thereby resulting in a refractory period in which it does not respond to the occurrence of the input signal, S, during the period up to and including time.

As described above, since the semiconductor device of Zero's invention uses the pass transistor 10 in the input stage of the input signal, the human input signal S
1 can be applied to the inverter 11 regardless of whether the input signal S1 is digital or analog.

And you can get a refractory period.

FIG. 3 is a circuit diagram of a semiconductor device showing another embodiment of the present invention. The input signal SI is applied to the gate G of a P-channel MO5FET 13, which is an output buffer circuit, via a pass transistor 10 and an inverter 11 of a data holding/amplifying circuit DH. The input side of the inverter 11 is a current refresh path circuit RP composed of an N-channel MOSFET 12, 16, a resistor 14, and a capacitor 15.
It is connected to the drain D of the N-channel type MO3IiET 12, and the ground potential is applied to the source S thereof. A DC power supply VI is connected to the gate G of the N-channel MOSFET 12.
llIll is connected through a resistor 14, and a capacitor 15 is interposed between its gate G and source S. The gate G and source S of the N-channel MOSFET 12 are connected to the drain D and source S of the N-channel MOSFET 16, respectively.
The gate G of SFET 16 is connected to the drain D of pass transistor 10.

The inverter 11. Inverter 17 and N-channel type MO5Pf! A flip-flop is formed by T18, and a data holding/amplifying circuit DH is configured by them, and a series circuit of an inverter 17 and an N-channel MO3FET 1B is connected in parallel to the inverter 11.

The feedback bus circuit FP includes an inverter 19, whose input side is the gate G of the pass transistor 10, and which is interposed between the gate G and the gate G of the N-channel MOSFET 18. . Furthermore, the gate G of the pass transistor IO is connected to the inverter 11.
connected to the output side of the and the P channel type MOS
The drain D of FET13 is connected to the DC power supply VDD,
An output signal S1° is obtained from the source S.

Next, the operation of this semiconductor device will be explained with reference to FIG.

FIG. 4 is a transition diagram showing potential changes at each node. Now, when the input signal S reaches the HII level, the potential of the drain D of the pass transistor 10 and the gate G of the N-channel MOSFHT 16 of the current refresh pass circuit RP, that is, the potential of the node 2, is indicated by the broken line S in FIG. As shown, the level becomes “°H” at time t1°, and the N-channel MO
SFET 16 is turned on.

Then, the potential of the gate G of the N-channel MOSFET 12, that is, the potential of the node Q, increases as indicated by the solid line S as the capacitor 15 discharges via the on-resistance of the N-channel MOSFET 16. de°°L°
Flip to Lebel. On the other hand, the potential of the node Q becomes the "H11 level" at the point of time as shown by the dashed lines S and I due to the input of the human input signal S of the "°H" level, and the inverter 11
The output side potential of D becomes "L" level, thereby turning off the pass transistor 10 and turning off the data holding and amplifying circuit D.
I holds the human input signal S1 input thereto. After that, when the human input signal SI reaches the "[," level, the potential of the node O changes as shown by the broken line S at time 1. The level is inverted to "L" and the N-channel MOSFET 16 is turned off. Then, a charging current flows from the DC power supply VD11 to the capacitor 15 via the resistor 14, and the voltage of the capacitor 15 rises, and the gate G potential of the N-channel MOSFET 12, that is, the potential of the node Q rises to the threshold potential ■N. Channel type MOSFET 12 turns on and node [F]
As shown by the dashed line Sm, the potential at time t is delayed by the inverter operating time from the time it reaches the threshold potential t5.
2, and flip it to the pare level.Then, the node ■ becomes ``[
," level, the output side potential of the inverter 11 becomes "H" level.
``The P-channel MOSFET 13 and the pass transistor 10 turn on, outputting an output signal S corresponding to the held human input signal S, and holding and amplifying the subsequent input signal S1. It is in a standby state that can be applied to the circuit DH.The data retention/amplification circuit DH uses a flip-flop to further stabilize the potential level of the node O.Furthermore, the feedback bus circuit FP is connected to the N of the data retention/amplification circuit O1l. Channel type MOSFF!T18
is controlled to ensure that the operating state of the data holding and amplifying circuit 011 is returned to its initial state.

In this way, the input signal S is at °゛H'°H'° level,
Current refresh path circuit 1? After the capacitor 15 of P is discharged and the input signal S+ changes to “L” level, the resistor 1
4 and the capacitor 15, a refractory period corresponding to the charging time during which the capacitor 15 is charged is obtained, and an output signal S having a time width corresponding to the refractory period. will be obtained. In this semiconductor device, since the resistor 14 and capacitor 15 for selecting the refractory period can be provided during the manufacturing process of the semiconductor device, the values of the resistor 14 and capacitor 15 can be easily selected with high precision. The refractory period can be selected as appropriate. As a result, the process margin of the semiconductor device is improved, and variations in the characteristics of this type of semiconductor device can be minimized.

In addition, since the output side potential of the inverter 11 at the data retention and amplification port BO) 1 is stable during the refractory period, addition of another signal to the output side potential or waveform shaping of the output side potential, etc. It becomes possible to do.

(Effects of the Invention) As described above in detail, the semiconductor device of the present invention can hold the input signal, whether the input signal is a digital or analog signal, and can obtain a refractory period. According to the present invention, even if the input signal is a digital or analog signal, it is possible to provide a semiconductor device that can simulate the functions of a living body.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor device according to the present invention, FIG. 2 is a timing chart of output signals, FIG. 3 is a circuit diagram of a semiconductor device showing another embodiment of the present invention, and FIG. FIG. 5 is a transition diagram showing potential changes at each node in the circuit, FIG. 5 is a circuit diagram of a conventional semiconductor device, and FIG. 6 is a signal waveform showing the response of a nerve membrane to current stimulation. 10... Pass transistor 11... Inverter
(Data retention, amplifier circuit) 12...N channel type M
O5FET (current refresh path circuit) 13...
P-channel MOSFET (output buffer circuit) 16.
18...N-channel type MO5FETRP...Current lift 1-tush pass circuit FP...Feedback path circuit DH.
・Data retention and amplification circuit diagram

Claims (1)

[Claims] 1. A pass transistor to which a signal is input, a data retention/amplification circuit that retains and amplifies the output of the pass transistor, an output buffer circuit to which the output of the data retention/amplification circuit is input, and the data retention/amplification circuit. and a current refresh path circuit that can bring the input side of the circuit to a predetermined potential,
A semiconductor device characterized in that the pass transistor is made conductive in relation to the output signal of the data holding and amplifying circuit.