JPH03133210A - Delay circuit - Google Patents

Abstract

PURPOSE:To obtain an output with a different delay time even when one tie constant circuit is employed by applying control voltages with different levels equal to the number of steps in matching with the number of steps. CONSTITUTION:When a step voltage is applied to a control terminal 3, the voltage is multiplied by '1' to be amplified by an amplifier 1 and is multiplied by -1 to be amplified by amplifier 2 and an output of the amplifier 2, and the output of the amplifiers 2 and 1 are applied to MP 1 and MN 1 gates of a transmission gate 9, respectively. Thus, it is possible to vary the resistance of the transfer gate 9 at the leading and tailing edge of the input voltage and even when the capacitance is in dispersion, the delay time due to the component dispersion is absorbed by varying the absolute value of the outputs of the amplifiers 1,2, then it is not required to provide an external mounted capacitor and number of pins is saved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit, and particularly to a delay circuit whose delay time can be varied in steps.

[Conventional technology]

Conventionally, this type of delay circuit has a time constant circuit that differs by the number of steps, the outputs of which are waveform-shaped by an inverter, each output is input to a multiplexer, and a certain amount of delay is generated depending on the conditions of the control terminal of the multiplexer. Only one signal was selected and output.

FIG. 5 shows an example of a conventional circuit.

In the conventional circuit shown in FIG. 5, 2 is an input terminal, 4 is an output terminal, 5 to 7 are multiplexer control terminals, and R
1-R1 is a resistance %C1~C7 are capacitors, INV3~
INV16 indicates an inverter.

Next, the operation of the conventional circuit will be explained with reference to FIGS. 5 and 6.

FIG. 5 shows an example in which the number of steps in the delay time is seven. Here, the delay time (hereinafter referred to as td) for the rising and falling edges of the input signal is
, 7, 9, 11, 13.15 threshold voltages (
Hereinafter, when vT, (assumed) is V, it is expressed by the following equation.

td=(-C,~,×R1~7)×J2n (1-VtM/V+s) [:S] (1)
However, (1): The peak value of the input voltage, therefore, assuming that V7H and VIN are constant, C1~ and R+~.

By changing the time constant, which is determined by the product of .

By inputting each of the above-mentioned outputs to a multiplexer (hereinafter referred to as MPX) and controlling MPX with the signals at control terminals 5 and 6.7, a step signal with a delay time of tdl to tar is obtained at output terminal 4. It will be done.

[Problem to be solved by the invention]

In the conventional embodiment described above, one set of time constant circuits is required for each delay time, so the larger the number of steps, the more time constant circuits will be required.

Furthermore, in order to improve the precision of the delay time in the IC, it is necessary to externally connect R or C1 or R and C, and the number of pins increases according to the number of steps. An object of the present invention is to provide a delay circuit in which outputs having different delay times can be obtained from one time constant circuit by changing the voltage at the control terminal regardless of the number of steps. Also, IC
In this case, it is possible to suppress variations in delay time due to element variations by adjusting the control terminal voltage according to the element variations, so the number of bins is determined by the number of bins for connecting capacitors. If one bottle or a capacitor is built in, an external bottle becomes unnecessary.

[Means to solve the problem]

The delay circuit of the present invention has a control terminal 3 for controlling the delay time. P-channel MO3 of the transfer gate Amplifier Amp2゜ outputs the opposite polarity of the voltage applied to the control terminal for controlling the gate voltage of the transistor A control terminal for controlling the gate voltage of the N-channel MOS transistor of the transfer gate An amplifier Ampl that outputs a voltage of the same polarity as the voltage applied to the transfer gate 92 whose resistance value changes depending on the gate voltage, a capacitor C3 for determining the time constant, and an inverter IN with a certain threshold voltage.
V1. It has an inverter I NV 2 for output Buff and an output terminal 4.

〔Example〕

Next, the present invention will be specifically explained with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, and the same numbers and symbols as in FIG. 5 indicate the same things.

In Fig. 1, when a voltage in the shape of a microwave as shown in Fig. 2 is applied to the control terminal, the voltage
Amplified by 1 times by Amp 1, minus 1 times by Amp2, MPI gate of transfer gate 9), MH
Amp2 output and Ampl output as shown in FIG. 3 are respectively applied to the I gate.

Next, the transfer gate 9 will be explained.

In the transfer gate, at the rising edge of the input voltage shown in Figure 4, if the input voltage peak value (hereinafter referred to as V+N) = power supply terminal voltage (hereinafter referred to as V), then the MHI is equal to the gate voltage (
Since VGN)<source voltage (VSN), it does not operate and only MPI operates.

Also, on the falling edge of the input voltage, MPI is V a p
> V Sp , it does not operate, and only MNl operates.

In addition, the operating resistance (hereinafter referred to as on-resistance) of the transfer gate 9
is expressed as the following equation at the time of rising and falling of the input voltage.

During operation, both MPl and MNl have a voltage of V due to the drain voltage and source voltage. The relationship s-V holds true.

However, VDS: Drain-source threshold voltage VO'! : Gate-source voltage ■T: Gate where a channel is generated and current begins to flow.
Source-to-source voltage P channel on-resistance (=Ros-p) ==(μ×ε
. , )/(2Xτ.X) μ: High field mobility ε. , : oxide film dielectric constant τ. Here, V G S p and V G S N are the input voltage peak value v1 and the gate voltage V G p r V
Since this is the voltage difference from G x, equations (2) and (3) become as follows.

N-channel on resistance (=RoN-x) = However, WP
, WN: P-channel MOS transistor, N-channel MO3) transistor channel width, , LN: P-channel MOS transistor, N-channel MOS transistor channel length β6. β,: P-channel MOS transistor, N-channel MOS transistor conductance Therefore, by controlling V G p + V G x with a voltage as shown in Figure 3, the rise of the input voltage.

The resistance of the transfer gate 9 can be varied by the falling edge.

Next, the amount of delay time is expressed by the following equation.

Rise delay time tdn= (-Cs xRox-r)xβn(1-Vt*/V+
++)CS) (6) Falling delay time tdn'= (-Cs xRox-1)XIln(1-VTI/V,
N)(S:) (7) From the above, from equations (4) to (7), substitute the necessary delay time and get V G p r V G
By finding N and inputting that voltage to the control terminal, Rox-p + Rox-y can be varied, so when the number of steps is 7 as shown in Figure 4, the delay time td
, to td7.

Also, β4. βN I V T p r V T pEven if the capacitor varies, the delay time due to element variation can be absorbed by changing the absolute value of the Ampl and Amp2 outputs, so there is no need to use an external capacitor. It is possible to reduce the number of pins.

Also, tdn and tdn' are W N / L x, W
p/L By setting the value of p to an appropriate value, tdn
=tdn'.

〔Effect of the invention〕

As explained above, according to the delay circuit of the present invention, by applying control voltages with different levels corresponding to the number of steps, even one time constant circuit can obtain outputs with different delay times. I can do it.

Also, variations in elements and capacitors can be absorbed by varying the absolute value of the control terminal voltage, which also makes it possible to reduce the number of external pins.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a voltage waveform applied to a control terminal of the present invention, and FIG. 3 is a diagram of a P-channel MOS transistor and an N-channel MOS transistor of a transfer gate. The voltage waveform applied to the gate, FIG. 4 shows the operating waveform of each part of the present invention, FIG. 5 is a circuit diagram showing a conventional embodiment, and FIG. 6 shows the operating waveform of each part of the conventional embodiment. l...Power terminal, 2...Input terminal, 3
...control terminal, 4 ...output terminal, 5 to 7 ...multiplexer control terminal, 8 ...multiplexer, 9 ...transfer gate, INVI~ NVI 6...Inverter, R1~R7...Resistor, C+~Ca...Capacitor.

Claims (1)

[Claims] P-channel MOS transistor and N-channel MOS
In a transfer gate in which the drain and source of a transistor are connected in common, an input terminal is provided on the drain side, and the gate of the P-channel MOS transistor receives the output of an amplifier that outputs a voltage of opposite polarity to the voltage applied to the control terminal. The gate of the N-channel MOS transistor is connected to the output of an amplifier that outputs the same polarity as the voltage applied to the control terminal, and the source side is connected to the G
In a circuit configured to have a capacitor between it and ND,
By generating the gate voltage of the transfer gate described above and varying the gate voltage in the voltage applied to the control terminal, the operating resistance of the transfer gate can be varied, and the delay time for the input signal is determined by the time constant of the operating resistance and capacitance. A delay circuit characterized by being able to change.