JPH03132132A - 4-value level shaped waveform generating system - Google Patents

Abstract

PURPOSE:To avoid an exponential increase in a memory capacity and to facilitate realization by realizing generation of a 4-value level shaped waveform with production of 2-dimension similar component waveform through addition and synthesis based on digital processing. CONSTITUTION:A modulated wave before band limiting (4-value square wave series) is analyzed into 2-dimension binary square wave series, and component waveform outputs subject to a prescribed band limit stored in advance accordingly are read from a component waveform generation ROM 5, then added and synthesized to generate a desired 4-value level shaped waveform. That is, let a component waveform output D represented in a storage data of the component waveform generation ROM 5 be DL and DM respectively when k-bit binary series BAL, BAM appear in a block address BA by the switching of a block address switching circuit 3, then addition of 2DM+DL or DM+1/2DL is implemented and the result is outputted externally as a 4-value level shaped waveform OUT. Thus, the 4-value level shaped waveform generating system is obtained, in which hindrance of the exponential increase in the memory capacity is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a series of four-level square waves having a pitch with a constant difference between adjacent levels used in digital modulation methods such as 16QAM and four-level FM. The present invention relates to an improvement of a four-level shaped waveform generation method that generates a shaped waveform by band-limiting a series of input four-level square waves.

(Prior art and its problems) FIG. 1A is an explanatory diagram showing an arrangement of modulation symbols of 16QAM, which is one of the modulation methods to which the present invention is applied. In the figure, the horizontal and vertical axes are the in-phase component (1) and quadrature component (Q) of the two orthogonal modulation waveforms, respectively, and as shown in the figure, ±3a and ±a on each axis. 4-value (ag
The intersection points (16 points) of vertical and horizontal straight lines occupying the value o) are modulation symbols. The difference between adjacent levels of modulation symbols on each axis is constant at 2a in the case of FIG. 1(A).

FIG. 1(B) is an explanatory diagram showing a four-level square wave sequence before band limitation. As mentioned above! Alternatively, the time variation of Q before band limitation becomes a four-level (±3a, ±a) square wave sequence with a variation period of one symbol time length T, as shown in FIG. 1(B). Four-value F, which is one of the other modulation methods to which the present invention is applied
In M, the baseband level before the band limitation of FM modulation becomes the same four-level square wave sequence as in FIG. 1(B), and the absolute value 3a of the maximum level becomes the quantity that defines the FM modulation index.

Now, as a method of generating a 4-level shaped waveform in which a predetermined band limit is applied to the above-mentioned 4-level square wave series, the conventional method is to generate the 4-level square wave signal shown in FIG. Analog processing methods such as shaping with a band-limiting low-pass filter, and inter-symbol interference symbol length (
For all combinations of the above four-level square wave series of k symbols), the waveform output of the second symbol after band limitation is calculated in advance and stored in the ROM (Read Only Me).
mory), read it out and D/A
There are methods that use digital processing to perform conversion.

However, in the former method using analog processing, the low-pass filter for band limiting is generally of high order, so the circuit scale becomes large, and when analog elements are used, it is difficult to compensate for environmental changes and aging In addition to requiring fine adjustment, there are problems with miniaturization and stabilization, such as making it unsuitable for IC implementation.

If the above-described low-pass filter is implemented using a digital signal processing device using A/D conversion and D/A conversion, stabilization can be achieved, but the circuit scale and power consumption will increase.

On the other hand, in general, methods using digital processing using ROM are superior in compactness, economy, and stability; however, in the latter method using conventional digital processing, the number of D/A conversion samples per symbol is set as S. and the RO to use
The capacity of M (the number of words for D/A conversion) is S·4 words. This value is the same as the conventional QPSK orthogonal modulated wave using a binary square wave series shaped waveform with the same number of samples S.
This is twice as large as the capacity of S·2 words that is required when generating k, and as k increases, the capacity becomes enormous, making it difficult to realize.

(Object of the Invention) The object of the present invention is to generate a 4-level shaped waveform with band limitation necessary for 16QAM, 4-level FM, etc. using a method using digital processing, and to generate a small waveform that is generated in the conventional analog processing. It is an object of the present invention to provide a four-value level shaped waveform generation method that eliminates the problems of economy, stability, and the problem of exponential increase in memory capacity that occurs in conventional digital processing methods.

(Structure and operation of the invention) [Structure] The present invention converts the modulated wave (four-level square wave series) before band limitation into two
A desired 4-level shaped waveform is generated by separating the original binary square wave series, reading out the corresponding component waveform outputs with pre-stored predetermined band limits from the component waveform generation ROM, and adding and synthesizing them. It is based on the method of generation.

FIG. 2 is a side view of the configuration showing an embodiment of the present invention. In the figure, l and 2 are binary 4-value (2-bit) LS that respectively indicate the level of each symbol of the 4-value square wave before band limitation.
Input B (lower bit) L and MSB (upper bit) M while sequentially shifting them according to the symbol timing,
Parallel outputs BAL and BA, which are binary sequences of (k is the inter-symbol interference symbol length due to band limitation)
.

This is a shift register that outputs .

3 is the parallel output BAL, B of the binary series of bits for each of the above.
A, and the external sampling clock signal 5
By switching according to the polarity of CLK, the resulting two-bit binary sequence output BA is used as a block address,
This is a block address switching circuit that supplies a component waveform generation ROM to be described later.

Reference numeral 4 denotes a scan address generation circuit which receives the sampling clock 5CLK and divides the frequency thereof to generate a scan address SA whose period is one symbol period.

Reference numeral 5 denotes a component waveform generation ROM in which any one of the binary component waveforms (hereinafter referred to as component waveform output) subjected to band limitation for one symbol period is stored in advance, and each of the component waveform generation ROMs is connected to the block address switching circuit 3. The block address BA and scan address SA, which are the outputs of the scan address generation circuit 4, are input, and the stored data of the memory block specified by BA, that is, the component waveform output, is outputted to the outside in the chronological order specified by SA.

Here, the above component waveform output is obtained by converting and separating each bit of the block address BA consisting of a binary series of k bits into positive and negative binary square waves with equal amplitude. Let it be the waveform of the th symbol when band limiting is applied to the value square wave series. Therefore, in the memory block specified by the block address BA of the component waveform generation ROM 5, the waveform of the second symbol interval of the binary shaped waveform subjected to the band limitation is calculated in advance as the component waveform output, and the scan address SA is They are written in the specified chronological order.

A register 6 temporarily stores the component waveform output read from the component waveform generation ROM 5 in accordance with the rise (or fall) timing of the sampling signal 5CLK.

Reference numeral 7 denotes an adder connected to the register 6 and the component waveform generation ROM 5, which is used to add bits when the binary series BAL and BAM of bits appear at the block address BA by the switching operation of the block address switching circuit 3. When the component waveform outputs shown in the stored data of the component waveform generation ROM 5 are respectively DL and D, 2DM+DL or DM+'/2DL is added and outputted to the outside as a four-level shaped waveform OUT.

Because the above-mentioned double and triple arithmetic operations are equivalent to shifting one bit to the MSB and LSB sides, respectively, due to the characteristics of binary values, there is no need to install a part that handles special processing functions; , can be easily realized by connection processing to the input of the adder 7.

Also, register 6 allows the above D t (or !4D
t) and 2DM (or) can be applied simultaneously to the two forces of the adder.

[Effect]

Next, the operation of the present invention based on the configuration example shown in FIG. 2 will be explained using FIG. 3.

FIG. 3 is an explanatory diagram in which the four-value square wave series of FIG. 1(B) is separated into a binary binary square wave series. That is, the four-level square wave series of ±3a and ±a shown in FIG.
This is a diagram in which the two-value square wave series (1) and (E) are separated, and the sum of both is equal to the four-value square wave series of FIG. ) is shown in Figure 1 CB)
Converting the LSB (marked in Figure 2) and MSB (M in Figure 2) of the binary 4-value (2 bits) assigned to the 4-value square wave level of , into binary values of ±a and ±2a, respectively. obtained by. The above variables are the binary values (0, 1) of L and M converted into positive and negative integers (-1°+1)! and m, the four-level square wave level; q (= ±3a
, ±a) can be expressed by the following formula; % formula % (1) where the first and second terms on the right side of (1) correspond to the waveform values of (e) and (n) in Figure 3, respectively. It is clear from the correspondence.

From the above, binary square wave sequences of symbols are added to the k-bit binary sequences BA and BA of FIG. The synthesized waveform is shown in Figure 1 (
Since it is equal to the symbol interval of the 4-level square wave sequence before band limiting shown in B), and the band limiting process is linear,
By adding the component wave outputs DL and D8 after band limitation at a ratio of 1:2 when the above B A L and BAD are read from the component waveform generation ROM 5 as block address BA, the 4-level level after band limitation is calculated. It is clear that a shaped waveform can be obtained, and it can be seen that in the present invention, the above processing is executed in a time-sharing manner using the block address switching circuit 3 and the register 6. Note that the output OUT of the adder 7 is input to an external register (not shown).
By converting the stored value into an analog signal using a D/A converter (not shown), a four-level shaped waveform can be obtained. In addition, when obtaining four-level shaped waveforms for each of the I and Q2 phases in parallel, as in the case of generating a 16QAM modulated waveform, a multiplexer that switches the input of the four-level square wave series for each of the I and Q phases is required. I, Q from the output of adder 7
By adding a demultiplexer or the like that separately stores each shaped waveform, it is possible to use the configuration of the present invention in time-division duplexing without increasing the memory capacity.

The capacity of the memory (component waveform generation ROM 5 in FIG. 2) used in the four-level level shaped waveform generation method of the present invention that performs the above operation is the number of samples of the shaped waveform per symbol.
Since the input sequence that determines l symbols is a binary sequence of 1 bits, it becomes a word in S·2, which is the same as in the case of shaping the modulation waveform of QPSK. This value is shown in Figure 1 (B
) to obtain a shaped waveform directly from the symbol interval. Compared to the conventional method, S4 is compressed to 172 words, and the memory capacity is significantly reduced. Ru.

(Effects of the Invention) As described above in detail, according to the present invention, generation of a four-level shaped waveform is realized by generation based on digital processing and additive synthesis of binary similar component waveforms, which is different from conventional Advantages include ease of implementation as it does not have the problems of compactness, economy, and stability that occur in analog processing, and also avoids the exponential increase in memory capacity that is an obstacle in conventional digital processing methods. There is.

[Brief explanation of the drawing]

FIG. 1 (A) is an explanatory diagram showing the arrangement of 16QAM modulation symbols, (B) is an explanatory diagram showing a 4-level square wave sequence before band limitation, and FIG. 2 is a diagram showing different configurations of an embodiment of the present invention. , FIG. 3 is an explanatory diagram in which FIG. 1(B) is separated into a binary binary square wave series. 1.2...Shift register, 3...Block address switching circuit, 4...Scan address generation circuit, 5.
...Component waveform generation ROM, 6...Register, 7...
Adder.

Claims (1)

[Claims] In order to obtain a 4-level shaped waveform with a predetermined band limit from a 4-level square wave sequence in which the difference between adjacent levels has a constant pitch, k symbols (k is a symbol due to the band limit) are used. The waveform of the k-th symbol after applying a predetermined band limit to an arbitrary binary square wave sequence with an interfering symbol length (interference symbol length) is calculated in advance as a component waveform output, and corresponds to the binary square wave sequence of the k symbols. The component waveform output is stored in a component waveform generation ROM (Read Only Memory) in chronological order in a memory block specified by a block address consisting of a k-bit binary series.
y), and alternately store k-bit binary sequences of lower bits and upper bits of binary 4-value (2 bits) indicating the level of each symbol of the 4-value square wave sequence before band limitation. The divided and switched outputs are supplied to the block addresses of the component waveform generation ROM, and two parallel waveforms obtained by switching and distributing the two component waveform outputs read out alternately from the component waveform generation ROM in a time division manner. 4 configured to add and synthesize the outputs at a ratio of 2:1 and output as the desired four-level shaped waveform.
Value level shaping waveform generation method.