JPH03131181A - Brightness adjustment circuit - Google Patents

Abstract

PURPOSE:To always keep a liquid crystal screen at an optimum brightness level by obtaining number of times when a luminance signal leaches white level and black level distortion for a prescribed period such as one field respectively and adjusting the luminance signal automatically based on a difference between number of times of both level distortions. CONSTITUTION:When an n-bit luminance signal Y is inputted to an input terminal 21, the luminance signal Y is added to an n-bit luminance control signal at an adder circuit 22. The luminance signal is amplified by a contrast control circuit 24 and converted into (n+alpha) bits and inputted to a limit circuit 25. The limit circuit 25 compresses the signal of (n+alpha) bits into an n-bit signal, and compresses a maximum value or a minimum value in n-bit depending on the content of the data in excess of n-bit. Then the n-bit luminance signal is controlled based on number of times of compression to a maximum value and number of times of compression to a minimum value for each prescribed period. Thus, the liquid crystal screen is kept always at an optimum luminance level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a brightness adjustment circuit in a liquid crystal television receiver.

[Prior Art] A brightness adjustment circuit in a conventional television receiver generally uses a method of changing the base voltage of a video amplification transistor, or a method of changing both the base voltage and the emitter voltage.

FIG. 6 shows a method for changing the base voltage of the video amplification transistor, and the brightness adjustment circuit includes a variable resistor 11 for setting the maximum brightness and a variable resistor 12 for brightness adjustment, and is provided in the video amplification circuit. That is, the video signal sent from the previous stage circuit is input to the base of the video amplification transistor 13 of the video amplification circuit, and the maximum brightness setting is performed via the characteristic correction coil 14 and resistor 15 between this base and the ground. A brightness adjustment circuit is provided, which includes a variable resistor 11 for use in the display and a variable resistor 12 for brightness adjustment.

Further, a resistor 16 is connected in parallel to the coil 14, and is grounded via a capacitor 17 from the connection point between the resistor 15 and the variable resistor 14.

A signal taken out from the collector of the video amplification transistor 13 is sent to the cathode of a picture tube (not shown).

In the above configuration, the maximum brightness is set by the variable resistor 11, and then the optimum brightness is set by the variable resistor 12. Since the video amplification circuit is a direct coupling circuit, the cathode voltage of the picture tube is changed by adjusting the variable resistors 11 and 12, and the brightness level can be set arbitrarily.

FIG. 7 shows a method for changing the base voltage and emitter voltage of the video amplification transistor, in which a variable resistor 11 for setting the maximum brightness is provided on the base side of the video amplification transistor, and a variable resistor 12 for brightness adjustment is provided. is provided on the emitter side of the transistor 13.

In the brightness adjustment circuit of the type shown in FIG. 7 as well, brightness adjustment is performed by variable resistors 11 and 12 in the same manner as in the case of FIG.

[Subtributive Problems to be Solved by the Invention] The brightness adjustment circuit shown in FIGS. 6 and 7 described above can perform brightness adjustment using variable resistors 11 and 12. However, in all of the conventional brightness adjustment circuits mentioned above, humans adjust the brightness by looking at the TV image. For example, if the black color is washed out, the brightness is increased; In such cases, it is necessary to make adjustments such as lowering the brightness, which is extremely troublesome.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a brightness adjustment circuit that can automatically adjust brightness and maintain a liquid crystal screen at an optimum brightness level at all times.

[Means and effects for solving the problem] The present invention amplifies an n-bit luminance signal and converts it into an n+α-bit signal, and then compresses the n+α-bit signal into an n-bit signal. Compress data exceeding bits to the maximum or minimum value of n bits depending on the content,
The value of the n-bit luminance signal is controlled based on the number of times of compression to the maximum value and the number of times of compression to the minimum value in each fixed period.

With the above configuration, the number of times the luminance signal is compressed to the maximum or minimum value of n bits for each field in a fixed period, that is, the number of times the whites are crushed and the shadows are crushed, is determined. The brightness signal is automatically adjusted to the optimum level based on the difference in the number of occurrences of crushed and dark areas.

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a brightness adjustment circuit in a liquid crystal television receiver. As shown in FIG. 1, the n-bit luminance signal sent from the previous stage circuit is sent to the input terminal 21.
The signal is input to the adder circuit 22 via. Furthermore, n-bit brightness adjustment data is inputted to the adder circuit 22 from an up/down counter 23 . The addition circuit 22 adds the n-bit luminance signal and the luminance adjustment data,
The addition result is output to the contrast control circuit 24. This contrast control circuit 24 amplifies the luminance signal input via the addition circuit 22 and (n
+α) bit data and output to the limit circuit 25. This limit circuit 25 will be described in detail later, but
It converts a luminance signal amplified to (n+α) bits into an n-bit luminance signal by cutting off the upper α bits.
For data that exceeds bits, it is compressed to a maximum or minimum value of n bits.

A portion of the output signal of the limit circuit 25 is sent to an overflow detection circuit 26 and an underflow detection circuit 27. The overflow detection circuit 26 includes a limit circuit 25
It detects data compressed to the maximum value by
Each time data is detected, a clock pulse CKI is output to count up the data counter 28. The underflow detection circuit 27 detects the data compressed to the minimum value by the limit circuit 25, and outputs a clock pulse CK2 every time data is detected to count up the counter 29. The count values of the counters 28 and 29 are latched into D-type flip-flops 30 and 31 by a pulse signal CKV synchronized with the vertical synchronization signal. Further, at this time, the count contents of the counters 28 and 29 are reset by the pulse signal CKV.

The m-bit output signal output from the flip-flop 30 is input to the "one terminal" of the magnitude comparator 32, and the m-bit output signal output from the flip-flop 31 is input to the "child terminal" of the magnitude comparator 32. ” will be entered. magnitude·
Comparator 32 compares the data held in flip-flops 30 and 31, and outputs the comparison result to up/down counter 23 as up/down signal U/D.

That is, when "number of overflows>number of underflows", the output of the magnitude φ comparator 32 becomes a low level, and the up/down counter 23 performs a countdown operation. When the number of overflows exceeds the number of underflows, the output of the magnitude comparator 32 becomes high level, and the up/down counter 23 performs a count-up operation.

The count value of the up/down counter 23 is input to the adder circuit 22 as control data and added to the n-bit luminance signal. As a result, the up/down counter 23 is set so that when the brightness signal output from the contrast control circuit 24 is "depleted whites > depleted blacks", the brightness is low, and when "depleted whites and depleted blacks", the brightness is increased. Operate.

Next, details of the limit circuit 25 will be explained with reference to FIG. The limit circuit 25 in FIG.
This figure shows the circuit configuration when the luminance signal of ``α'' is rn-7 bits'' and ``α-4 bits''.

8 sent from the contrast control circuit 24
As for the bit luminance signal Dll-Di, the lower five bits of data DI-D15 are input to OR circuits 42a to 42e via AND circuits 41a to 41e. Further, the upper 3 bits of data D6 to D8 are D6. The bit D7 is input to the OR circuit 43 and the NAND circuit 44, and the most significant bit D
8 is input to the inverter 45. And OR circuit 4
3 and the outputs of the inverter 45 are input to an AND circuit 46, and the NAND circuit 44 and the most significant bit D8 are input to an AND circuit 47.

The output signal A of the AND circuit 46 is output from the OR circuit 42.
a to 42e, and is also sent to the overflow detection circuit 26 shown in FIG. Further, the output signal of the AND circuit 47 is transmitted to the AND circuit 41a via an inverter 48.
.about.41e, and is also sent to the underflow detection circuit 27 in FIG.

Then, the most significant bit D8 in the output signals of the OR circuits 42a to 42e and the input luminance signal is output to the limit circuit 2.
5 output data Q1 to Q6.

The limit circuit 25 configured as described above is shown in FIG.
The upper three bits D8, D7 . of the input data from the contrast control circuit 24 shown in a). Depending on the state of Do, the output data is subjected to three types of processing shown below. Note that the most significant bit D8 of the input data is a sign bit, and in this example, “0° is “+” and “1” is “-”.
” is shown.

■ In the case of Dli-D7-D6, in this case, the limit is not applied and the same value as the input is output.

■ When D8-“0” and D7+D6 is “1” In this case, the output data is fixed to the maximum value r011111J.

■ When DB-“1” and D7・DB-“0” In this case, the output data is fixed to the minimum value r 100OOOJ.

FIGS. 3(a), 3(b) and 4 show the above operating state.

Therefore, in the case of rD8-D7-DBJ as in the above (■), both the output signals A and B of the AND circuits 46 and 47 become mOs, and the output to the inverter 48 becomes '1'.
° and is input to AND circuits 41a to 41e. As a result, the input data D1 to D5 are input to the AND circuits 418 to 418.
1e and the OR circuits 42a to 42e as Q1 to Q5, and the most significant bit D8, which is the sign bit of the input data, is added as Q6. Therefore, D
When 8 to DB is rill J or rooo J, the limiter operation is not performed and the manual data Dl-D5
, DB are taken out as they are as output data Q1 to Q6.

In addition, as in the above (■), rD8-“0” and D7.
When DB is '1', the outputs of the inverter 45, NAND circuit 44 and OR circuit 43 are all '1', and the output signals A and B of the AND circuits 46 and 47 are both jllll. Then, the output signal Ql of the OR circuits 42a to 42e
- Q5 is all "12Q6 is fixed to the maximum value of "0".

In addition, as in the above (■), rD8−“1° and D7・
DB-0", the output of the inverter 45 is '0"
, the output of the NAND circuit 44 becomes '1'', and the AND circuit 4
The output of the AND circuit 47 becomes "0", and the output of the AND circuit 47 becomes "1". Therefore, the output of the inverter 48 becomes "0", and the gates of the AND circuits 41a to 41e close. Output signals Ql-Q5 are all “0”
゛QB is fixed to the minimum value of "1".

As described above, the limit circuit 25 compresses the 8-bit data DI-D8 into 6-bit data Ql-QB. Also, during the above compression process, an AND circuit 46.4
Signal A output from 7.

B is sent to an overflow detection circuit 26 and an underflow detection circuit 27, details of which are shown in FIG.

The overflow detection circuit 26 is composed of an AND circuit 261, and the signal A sent from the AND circuit 46 is input to the AND circuit 261 together with the system clock, and the output signal is sent to the counter 28 in FIG. 1 as an overflow detection signal. It will be done.

Further, the underflow detection circuit 27 connects the inverter 271
and an AND circuit 272, and an AND circuit 44
Signal B sent from the inverter 271 is input to the AND circuit 272.

A system clock is further input to this AND circuit 272, and its output signal is sent to the counter 29 as an underflow detection signal.

Next, the overall operation of the above embodiment will be explained.

In FIG. 1, an n-bit luminance signal Y is input to the input terminal 21.
When input, this brightness signal Y is added to the n-bit brightness control signal output from the up/down counter 23 in the adding circuit 22.

The luminance signal added by the adder circuit 22 is amplified by the contrast control circuit 24, converted to n+α bits (7+4 bits in this embodiment), and input to the limit circuit 25 whose details are shown in FIG. . The limit circuit 25 converts the n+α-bit luminance signal into an n-bit luminance signal as described above, but compresses data exceeding n bits to the maximum or minimum value of n bits. Then, the n-bit luminance signal compressed by the limit circuit 25 is sent to the next stage processing circuit.

Also, the AND circuit 4 of the limit circuit 25 in FIG.
The signal A output from the AND circuit 44 and the signal B output from the AND circuit 44 are input to the underflow detection circuit 27. When the output signal A of the AND circuit 43 becomes high level, the overflow detection circuit 26 detects this state in synchronization with the system clock and outputs it to the counter 28 as an overflow signal. In addition, the underflow detection circuit 2
7 detects this state in synchronization with the system clock when the output signal B of the AND circuit 44 becomes low level, and outputs it to the counter 29 as an underflow signal. The counters 28 and 29 each include an overflow detection circuit 26.
Each time a detection signal is output from the underflow detection circuit 27, a count-up operation is performed, and the count continues until cleared by the pulse signal CKV. This pulse signal CK
Since V is a pulse with a one-field period synchronized with the vertical synchronization signal, the contents of the counters 28 and 29 that are cleared are the number of occurrences of "whitewashing" and "blackwashing" between one field. Become. The count value of this counter 28.29 is latched by a flip-flop 30.31 in synchronization with the pulse signal CKV, and then compared in a magnitude comparator 32. This comparator 32
outputs a low level signal when "overflow count > underflow count", and the up/down counter 23
count down. In addition, the comparator 32
When the number of overflows exceeds the number of underflows, a high level signal is output and the up/down counter 23 counts down.

The count value of the up/down counter 23 is sent as an n-bit brightness control signal to the adder circuit 22, and added to the n-bit brightness signal Y input from the previous stage circuit via the input terminal 21. As a result, when the brightness signal output from the contrast control circuit 24 is "depleted whites>depleted blacks", the count value of the up/down counter 23 becomes small and the brightness level becomes low. Further, when the brightness signal output from the contrast control circuit 24 is "dead whites and depleted blacks", the count value of the up/down counter 23 becomes large and the brightness level becomes high. In this way, the level of the luminance signal Y input to the input terminal 21 is automatically adjusted to an optimum value, and is sent from the limit circuit 25 to the next stage circuit. Therefore, the liquid crystal display screen is always maintained at an optimal brightness level and high image quality can be obtained.

[Effects of the Invention] As detailed above, according to the present invention, an n-bit luminance signal is amplified and converted into an n+α-bit signal, and then this n+α-bit signal is compressed into an n-bit signal. , data exceeding n bits is compressed to the maximum value or minimum value of n bits depending on its content, and the brightness of the n bits is determined based on the number of times of compression to the maximum value and the number of times of compression to the minimum value in each fixed period. Since the value of the signal is controlled, the brightness signal is automatically adjusted to the optimum value according to its level, that is, based on the difference in the number of times that white and dark areas occur. Therefore, the liquid crystal screen can always be maintained at an optimal brightness level.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a brightness adjustment circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing details of the limit circuit in FIG. 1, and FIGS. 3 and 4 are limit circuits. FIG. 5 is a diagram showing details of the overflow detection circuit and underflow detection circuit in FIG. 1, and FIGS. 6 and 7 are diagrams showing conventional brightness adjustment circuits. 21...Input terminal, 22...Addition circuit, 23...
Up/down counter, 24...Contrast control circuit, 25...Limit circuit, 26...Overflow detection circuit, 27...Underflow detection circuit, 28.29...Counter, 30.31... - Flip-flop, 32...Magnitude comparator, 41a-41e...AND circuit, 42a-42e. 43...OR circuit, 44...NAND circuit, 46.4
7...AND circuit.

Claims (1)

[Claims] an amplifying means for amplifying an n-bit luminance signal and converting it into an n+α-bit signal; and an n+α signal output from the amplifying means.
Compression means compresses a bit signal into an n-bit signal, and compresses data exceeding n bits to a maximum value or minimum value of n bits depending on the content, and this compression means compresses an n+α-bit signal to the maximum value. overflow counting means for detecting and counting the state each time the signal of n+α bits is compressed to the minimum value by the compression means; A brightness adjustment circuit comprising: control means for controlling the value of the brightness signal input to the amplification means based on the count values of the overflow counting means and the underflow counting means at regular intervals.