JPH03131119A - Delayed operation type switching device - Google Patents

Abstract

PURPOSE:To realize a switching device capable of delayed operation with a few number of components by providing a capacitor charged during input of an external signal, a resistor connecting to the capacitor and a field effect output transistor(TR) interposed in a power supply line leading to a load. CONSTITUTION:Switching TRs 11, 12 are connected in parallel with each other, one of two connecting points is connected to a power supply terminal Vc and the other point connected to a ground terminal E via a parallel circuit comprising a capacitor 17 and a discharge resistor 18. Moreover, a charge/discharge circuit section 2 is formed by the parallel circuit comprising the capacitor 17 and the discharge resistor 18. The control is applied to the switching device such that its delayed operation time is taken till the terminal voltage of the said capacitor 17 reaches the gate threshold voltage of an output TR 19 or below when the charge charged in the capacitor 17 is discharged via the discharge resistor 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delayed operation type switchgear having a function of maintaining driving of a load for a predetermined time after an input signal is stopped.

[Conventional technology]

Conventionally, the delayed operation type switchgear as described above has been
As shown in the figure, a delay circuit 42 equipped with a timer IC 41
and a drive circuit 44 having an output transistor 43 made of a bipolar transistor. By externally attaching several CR parts to the timer IC 41, the delay time, that is, the timer time is set. With this configuration of the delay circuit 42, the elapse of the timer time from the time when the external input signal stops is detected, and while the timer time elapses, the constant voltage drive signal is continuously output. By inputting this drive signal to the output transistor 43 of the drive circuit 44, energization to the load 45 is maintained during the timer period even after the input signal is stopped.

[Problem to be solved by the invention] As described above, the timer I has a built-in delay time measurement function.
By using C41, it is possible to perform a highly accurate delay operation in accordance with the set timer time. However, in cases where highly accurate timer time control is not required, if a delay circuit equipped with the above-mentioned timer IC is provided independently from the drive circuit, the manufacturing cost will be excessive. There's a problem. Further, in the above, even during the delay operation period, that is, the timer operation period, in order to maintain the time measurement operation of the timer IC 41 and the output state of the drive current consumed as the base current of the output transistor 43, the power supply voltage is applied to the delay circuit 42. As a result, there is a problem that power consumption increases.

[Means to solve the problem]

In order to solve the above problems, the delayed action switchgear of the present invention includes a capacitor that is charged during input of an external signal, a resistor connected to this capacitor, and an electric field interposed in a current carrying line to the load. Equipped with an effect type output transistor,
After the external signal is stopped, this output transistor is maintained in a closed state while the terminal voltage of the capacitor during discharging via the resistor exceeds the threshold voltage of the output transistor. It is characterized in that the terminal voltage of the capacitor is input to the gate of the transistor.

[For production]

According to the above configuration, first, a voltage is applied to the capacitor and the capacitor is charged while an external signal is being input. When the external signal is stopped, the charge stored in the capacitor will be discharged through the resistor, and the terminal voltage of the capacitor will gradually increase along the discharge curve determined by the capacitance and resistance value. decreases to This terminal voltage is input to the gate of the output transistor, and therefore, while it exceeds the threshold voltage of this output transistor, this output transistor remains closed and current continues to be applied to the load. Ru. In this manner, the above configuration is such that the terminal voltage during discharge in the capacitor is directly input to the output transistor, and the inherent operating characteristics of the output transistor are utilized to perform the delay operation. Therefore, it is possible to construct a switchgear that performs delayed operation without providing an expensive timer IC or the like as in the prior art and with a small number of parts.

In addition, in the above, the power required to determine the delay operation period and the gate current to the output transistor are:
It is powered by the charge stored in the capacitor, and does not require power from a power source during this time. In addition, since the output transistor is composed of a field effect transistor, the gate current required to maintain the closed state of this transistor is small, and as a result, it is possible to reduce the capacitance of the capacitor. Become.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

The delayed operation type switchgear in one embodiment of the present invention has a first
As shown in the figure, a switch circuit section 1, a charging/discharging circuit section 2,
Each functional section of the drive circuit section 3 is provided. First, in FIG. 2, the switch circuit section 1 has two switching transistors 11 and 12 connected to the first and second signal input terminals S1 and S2, respectively, and two switching transistors 11 and 12 connected to each switching transistor 11 and 12, respectively. It consists of base resistors 13 and 14 and base bias resistors 15 and 16. That is, in this case, two systems of input signal paths are provided, and the input signal to the first signal input terminal SI is input to the base of the first switching transistor 11 made of a PNP type bipolar transistor, and the first signal When an L (Low) level voltage signal is input to the input terminal S1, this first switching transistor 11 is closed, while the input signal to the second signal input terminal S2 is composed of an NPN type bipolar transistor. input to the base of the second switching transistor 12;
When an H (High) level voltage signal is input to the signal input terminal S2, the second switching transistor 12 is closed. In this way, in the above circuit,
The input terminal can be selected according to the signal format of the previous stage. In addition, in the above case, each signal input terminal S,
When separate switches are connected to both of S2, the switching transistors 11 and 12 are opened and closed independently according to each switch.

The switching transistors 11 and 12 are connected in parallel with each other, with one end connected to the power supply terminal Vc and the other end connected to the ground terminal via a parallel circuit of a capacitor 17 and a discharge resistor 18. ing. Note that the charging/discharging circuit section 2 is constituted by a parallel circuit of the capacitor 17 and the discharging resistor 18.

On the other hand, an MO
S-type FET (Field Effect Tr
An output transistor 19 consisting of a field effect transistor (ansistor) is connected, and the drive circuit section 3 is constituted by this output transistor 19. The terminal voltage of the capacitor 17 is inputted to the gate of the output transistor 19. Therefore, the terminal voltage of the capacitor 17 is different from the gate threshold voltage (threshold voltage) of the output transistor 19. The opening/closing operation of the output transistor 19 is switched depending on the height.

Note that the gate threshold voltage of the above-mentioned MOS-FET is generally 3 to 4 V, and the gate withstand voltage is ±2
It is about 0 to 30V. Therefore, in order to prevent the output transistor 19 from being destroyed, it is necessary that the voltage applied to the gate be within about 3 to 4 times the gate threshold voltage. In order to satisfy such conditions, a Zener diode 20 for overvoltage protection of the gate voltage and a resistor 21 for limiting gate current are connected to the gate terminal of the output transistor 19, respectively.

Next, the operating state of the delayed operation type switchgear having the above-mentioned structure will be explained, taking as an example the lighting control of the interior lights of an automobile. In this case, the 0N is linked to the opening and closing of the car door.
A door switch 31 that turns 10FF is connected to the first input terminal S1, and a power supply 32 consisting of a battery is connected to the power supply terminal Vc.
It is assumed that a load 33 consisting of an indoor light is connected to each of the load connection terminals. It is assumed that the door switch 31 is closed when the door of the automobile is opened.

First, when the door is opened and the door switch 31 is closed, the input voltage to the base of the first switching transistor 11 changes from H to L as shown in FIG.

As a result, the collector-emitter of the first switching transistor 11 becomes conductive (ON). As a result, the power supply 3
The supply voltage from 2 is applied to capacitor 17, and charging of this capacitor 17 begins. When the terminal voltage of this capacitor 17, that is, the input voltage to the gate of the output transistor 19 exceeds the gate threshold voltage as shown in FIG. As shown in FIG. 3, power supply to the load 33 is started, and the load 33, that is, the indoor light is turned on.

Thereafter, the door is closed, the door switch 31 is opened, and when the input voltage to the base of the first switching transistor 11 changes from L to H, the first switching transistor 11 is turned off. As a result, the voltage supply to the capacitor 17 is cut off, and after this, the electric charge stored in the capacitor 17 is discharged via the discharge resistor 18. As a result, the input voltage to the gate of the output transistor 19 is equal to the capacitor 17's capacity 1 and the discharge resistor 1.
As shown in FIG. 3, it gradually decreases along the discharge curve with a time constant determined from the resistance value of 8. Even in the process of decreasing the input voltage, the output transistor 19 continues to be in the ON state as long as it is higher than the gate threshold voltage, so that the load 33 is kept energized.

Then, when the input voltage becomes equal to or lower than the gate threshold voltage, the output transistor 19 becomes F, thereby stopping power supply to the load 33, that is, the indoor light.
Lights out.

As described above, when the charge stored in the capacitor 17 is discharged via the discharge resistor 18, the time required for the terminal voltage of the capacitor 17 to become equal to or lower than the gate threshold voltage of the output transistor 19 is calculated. , control is performed to set the delay operation time. As a result, for example, the interior light or the keyhole light will continue to be lit during the above-mentioned delay operation time after closing the car door at night. can be easily done.

As described above, in the above configuration, the terminal voltage of the capacitor 17 is directly input to the output transistor 19, and control is performed to delay the stop of energization to the load for a predetermined period of time from the stop of the input signal. That is, the delay operation time is controlled by a combination of the discharge characteristics of the capacitor 17 and the unique operating characteristics of the output transistor 19, and unlike the conventional configuration described above, an expensive timer IC or the like is not provided. Since it can be configured with a small number of parts without any problems, the configuration is simple and can be manufactured at a lower cost.

In addition, in the above, the power required to determine the delay operation period and the gate current to the output transistor are:
Since it is covered by the electric charge stored in the capacitor and does not require power supply from a power source during this period, it is possible to reduce power consumption compared to the conventional method.

Furthermore, as described above, the output transistor 19 has a MOS
- When a FET is used, this gate current is several μA or less, so even if the delay time is about several tens of seconds, the capacitor 17 can be configured with a small capacitor of about several tens of μF. , the production cost will be lower. Furthermore, as described above, since the current consumed by the output transistor 19 is small, the discharge of the capacitor 17 is mainly performed by the discharge resistor 18, and therefore the capacitance of the capacitor 17 and the resistance value of the discharge resistor 18 are Since it is possible to set the delay time so as to cause a voltage change that substantially follows the discharge curve of the time constant determined from , this setting work can be easily performed. As shown in FIG. 2, the device is provided with a connection terminal T for connecting external components in parallel to the capacitor 17 and the discharge resistor 18. When a capacitor is attached to this terminal T, the delay operation time can be lengthened, whereas when a resistor is attached, the delay operation time can be shortened, and the delay operation time can be adjusted depending on the purpose of use. changes can be made.

In addition, in the above embodiment, the lighting control of the interior lights of a car was explained as an example. It is possible to adopt a configuration in which the device is applied to control energization.

〔Effect of the invention〕

As described above, the delayed action type switchgear of the present invention includes a capacitor that is charged while an external signal is input, a resistor connected to this capacitor, and a field effect type switch that is interposed in the current carrying line to the load. an output transistor, and after the external signal is stopped, the output transistor remains closed while the terminal voltage of the capacitor during discharging through the resistor exceeds the threshold voltage of the output transistor. The configuration is such that the terminal voltage of the capacitor is input to the gate of this output transistor.

Therefore, it is possible to perform the delay operation with a small number of parts without providing an expensive timer tC or the like.

Further, during the delay operation period, control is performed using the charge stored in the capacitor, and no power supply is required for this purpose. Furthermore, since the output transistor is composed of a field-effect transistor, the gate current required to maintain the closed state of this transistor is also small, making it possible to reduce the capacitance of the capacitor. becomes. As a result, the present invention has the advantage that it can be manufactured at a lower cost and can be configured as a delayed operation switchgear with reduced power consumption.

[Brief explanation of the drawing]

1 to 3 show one embodiment of the present invention. FIG. 1 is a functional block diagram. FIG. 2 is an electrical circuit diagram. FIG. 3 is a timing diagram of signal waveforms. FIG. 4 is an electrical circuit diagram showing an example of a conventional delay action type switchgear. 17 is a capacitor, 18 is a discharge resistor, 19 is an output transistor, and 33 is a load. Figure 3 Seki Figure

Claims (1)

[Claims] 1. Equipped with a capacitor that is charged during input of an external signal, a resistor connected to the capacitor, and a field-effect output transistor interposed in the current-carrying line to the load, and after the external signal is stopped, While the terminal voltage of the capacitor during discharging through the resistor exceeds the threshold voltage of the output transistor, the capacitor is connected to the gate of the output transistor so that the output transistor remains closed. A delayed action switchgear characterized by inputting terminal voltage.