JPH03129851A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To shorten a time required for sorting non-defectives from defectives and to improve a screening operation in workability by a method wherein non-defective and defective chips on a wafer after a test are grouped into mosaic patterns which contain a prescribed number of chips each, a weight is attached to the position of each of the chips, and the movement from a non- defective chip to another non-defective chip is fixed into a prescribed movement pattern. CONSTITUTION:Chips on a wafer are checked if they are defective (mark X) or non-defective (mark O). After tested, non-defective and defective chips on a wafer are recognized as mosaic patterns of chips. Chip positions are weighted. Each movement from a non-defective chip to another non-defective chip has a prescribed movement pattern. Therefore, the movements are not uniform or sequential but have an optimal movement pattern. By this setup, a time required for sorting non-defectives from defectives can be shortened and a screening operation can be improved in workability.

Description

[Detailed Description of the Invention] Industrial Field of Application Prior Art (Figures 21 and 22) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems Explanation of the Principle of the Invention (Figures 1 to 4) ) The first aspect of the present invention
Example (Figures 5 to 18) Second example of the present invention
(Figures 19 and 20) Effects of the invention [Summary] Regarding a method for manufacturing a semiconductor device, the present invention provides a method for manufacturing a semiconductor device that can shorten the time for sorting between good and defective chips and improve workability. The purpose is to test the non-defective/defective product status of multiple chips on a wafer, and to determine the non-defective/defective product status of the chips on the wafer after the test is completed for a predetermined chip unit.
In addition to recognizing it as a mosaic pattern as a group, weighting is applied to each chip position in each chip, and the movement from good to good is fixed to a predetermined movement pattern, so that good/defective products can be sorted in the shortest process. Configure.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which good/defective chips on a wafer are selected in the shortest process from a wafer that has been tested in a wafer state.

Typically, a wafer fabrication process processes a large number of wafers at the same time (typically 50-100 wafers per 10 pieces). Since tens to hundreds of chips can be obtained from each wafer, the number of chips obtained at the end of the wafer process is enormous.

The degree of yield (the percentage of good chips in a wafer) varies depending on the complexity of the manufacturing process, the design rules used, and the circuit scale (chip size), but there is a certain percentage of defects in each wafer at the end of the wafer process. There is a chip. Therefore, in order to exclude these defective chips from the next assembly process and to minimize the loss caused in the assembly process, the quality of all chips on each wafer is tested in the wafer state. This test is called a probe test and is performed using a wafer prober device. In a probe test, the tip of the probe is brought into contact with a pad on the chip, and the electrical characteristics of the chip are tested using a signal generator and waveform analyzer connected to the probe.

Defective chips found here are automatically marked and excluded from future assembly.

[Conventional technology]

Sorting good/defective products from wafers that have undergone a wafer test (hereinafter abbreviated as PT) is carried out in die bonding, chip surface inspection, and the like.

In this work, (1) the positions of good/defective products and chips are stored in advance on a floppy disk or the like during PT, and the chips are automatically sorted based on the information. (2) There are two methods of sorting by observing (detecting) markings on the chip surface for good/defective products during work. In either case, the determination and sorting of good/defective products is performed by sequentially moving the wafer in a fixed direction. For example, there is a method shown in FIGS. 21 and 22 as a method of manufacturing such a semiconductor device. In FIG. 21, l is a wafer, and 2 is an X-
Y table, 3 is a camera for detecting the position of the chip, 4 is a floppy disk for storing the position data detected by camera 3, 5 is air for sucking and moving the chip after cutting with a vacuum chuck It's tweezers. The chips divided by dicing are subjected to die bonding through the following steps.
be done.

(2) Adsorb the divided chip 6 with the air tweezers 5 and move it onto the intermediate table 7.

■ Place the divided chips 6 on the intermediate table 7.

(2) Pick up and move the divided chips 6 from the intermediate table 7 with the Guicolette 8.

■Guicolette 8 is used to bond package 9. In this case, the X-Y position of the chip 6 divided by the intermediate table 7 is also determined.

(2) Move the X-Y table 2 so that the next chip 6 is directly under the air tweezers 5.

There are two patterns for the above-mentioned Gui bonding.

Pa5s/Fail of the Paenino top wafer 1 is recognized by the in mark on the chip, and only those without the in mark are picked up and transported to the intermediate table 7. The movement of the XY table 2 is sequential.

Pa5s/Fail and chip position of the wafer 1 are stored in the floppy disk 4 or the like at the PT stage, and based on this information, only the passed chips are picked up and transported to the intermediate table 7. The movement of the XY table 2 is sequential.

On the other hand, in the chip surface inspection, a person operates the microscope 11 to inspect the wafer 13 on the turntable 12, as shown in FIG.
Visually inspect each chip. The turntable 12 is moved manually or automatically to inspect the chip surface. Then, after looking at both the P T Pa5s/Fai1 products once and recognizing the Fai1 product as the Pa11 product, it moves on to the next chip. Movement of the turntable 12 is sequential.

(Problems to be Solved by the Invention) However, in such a conventional semiconductor device manufacturing method, the X-Y table 2 or the turntable 1
Since the structure is such that the movements of the parts 2 and 2 are carried out sequentially, it takes time to sort out good products and defective products, which poses a problem in that work efficiency cannot be improved.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can shorten the time required to sort out good/defective chips and improve workability.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention tests the non-defective/defective states of a plurality of chips on a wafer, and determines the non-defective/defective states of the chips on the wafer after the test is completed. Recognizes each chip as a mosaic pattern as one group, weights each chip position in each chip, and fixes the movement from good to good to a predetermined movement pattern, making the selection of good and defective products the shortest process. A method of manufacturing a semiconductor device is provided.

[Effect]

In the present invention, the non-defective/defective product status after PT is made into a predetermined chip-by-chip mosaic pattern, and the chip positions are weighted. Further, along with this, the movement from non-defective products to non-defective products is fixed to a predetermined movement pattern.

Therefore, movement is no longer performed uniformly and sequentially, and by operating in an optimal operation pattern, the selection of good/defective products is minimized, and throughput is improved.

[Explanation of principle]

First, the present invention will be explained in detail. 1 to 4 are diagrams for explaining a method of manufacturing a semiconductor device according to the present invention. As shown in FIG. 1, the condition of good/defective products on a wafer is considered to be a mosaic pattern, and for example, 4 chips are grouped into one group, and depending on the position of the chips, 1.2.4.
Give it a weight of 8. The basic movement direction is shown in FIG. 2, and the movement is basically from non-defective product to non-defective product, but it is always returned to "l". In this case, it does not stagnate at "1". According to this method, the movement direction is fixed in 16 patterns. FIGS. 3(a) and 3(b) are examples of the pattern.

Therefore, in the conventional example shown in FIG. 4(b), 15 steps were required to perform the movement sequentially;
In the present invention, there are 11 steps, which is about 25% shorter. The number of Fails is greater than the number of Pa5s (number of Pa-ss<
This ratio becomes even higher when the number of Fails increases.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

5 to 18 are diagrams showing a first embodiment of the method for manufacturing a semiconductor device according to the present invention, and this embodiment is an example in which the present invention is applied to a direct die bonding apparatus. In describing this embodiment, the same components as those in FIG. 21 shown as a conventional example are given the same reference numerals, and redundant explanation will be omitted.

In FIG. 5, during bonding of the n-th wafer 21, a good product/defective product of the n+1-th wafer 22 is identified, and
- By determining the motion pattern of the Y table 2 in advance, the identification time is reduced. There are two patterns for this bonding as in the conventional example, and these two patterns will be described in this embodiment in comparison with patterns 1 and 2 of the conventional example.

■The person who fired the burn to the burner 1 of the
The Pa5s/Fail of the +1st wafer 22 is read, and the operation of the X-Y table 2 is determined and stored.

■The n+1st wafer 22 is the P of the nth wafer 21.
After the a5s/Fail operation is completed, the X-Y table 2 moves according to the operation predetermined in step (2) above.

(2) Only when the X-Y table 2 is stagnant, the air tweezers 5 perform suction, movement, and release operations as shown in FIG.

A specific configuration for performing the above operations is shown in FIG. In FIG. 7, Pa5s/Fail detection section 23
Pa5s/Fail from n+1th wafer 22
is detected and this data is stored in the Pa5s/Fail data storage section 24. Pa5s/Fail data storage section 2
The data processing unit 25 performs data processing to convert the Pa5s/Fail data stored in 4 into an operation pattern, and stores this operation pattern in the operation pattern storage unit 26.

Here, the details of the operation pattern will be explained in detail with reference to FIG. 9.10, which will be described later. The operation pattern stored in the operation pattern storage section 26 and the control signal from the Guicolet control circuit 27 for controlling the Guicolet 8 are input to the X-Y table operation control section 28, and the X-Y table operation control section 28 A control value for controlling the X-Y table 2 is calculated based on the information and a control signal from the air tweezers operation control unit 30, which will be described later, and the calculation result is used as the
It is output to the table operating mechanism 29. The X-Y table operation mechanism 29 operates the x-Y table 2 based on the above control values. The control signal of the Guicolet control circuit 27 is further input to the air tweezers operation control section 30, and the air tweezers operation control section 30 receives this control signal and the X-
A control value for controlling the air tweezers 5 is calculated based on the control signal from the Y-table operation control section 28, and the calculation result is output to the air tweezers operation mechanism 31. The air tweezers operation mechanism 31 operates the air tweezers 5 based on the above control value.

■ In this case, there is no need to read out the n+1th wafer 22, and the data stored on the floppy disk is processed at the PT stage to determine the operation of the X-Y table 2. .

■The n+1st wafer 22 is the P of the nth wafer 21.
After the completion of the a5s/Fail operation, the X-Y table 2 moves according to the operation predetermined in step (2) above.

(2) Only when the X-Y table 2 is stagnant, the air tweezers 5 perform the operation shown in FIG. 6 described above.

A specific configuration of the above operation is shown in FIG. In FIG. 8, when the PT32 ends, the Pa5s/Fail data is stored in the Pa5s/Fail data storage section 24, and is output from the Pa5s/Fail data storage section 24 to the floppy disk 33 as required. The Pa5s/Fail data stored on the floppy disk 33 is read out by the disk drive device 34, and the process then proceeds to data processing after the data processing section 25 shown in FIG. 7 described above.

Next, the operation pattern according to this embodiment will be explained using FIG. 9.10. As explained in the explanation of the principle, the present invention regards a certain chip unit as a mosaic pattern, assigns a predetermined weight to each of the patterns, and fixes the movement from non-defective products to non-defective products in a predetermined pattern. In this embodiment, the mosaic pattern is a 4-chip mosaic pattern as shown in FIG.
weight. This (1), (2), (4), (8
) is given for convenience in order to predetermine the operation pattern, and is not limited to the case of FIG. 9. )
, (8) can be determined freely. The operation pattern when such weighting is applied is shown in FIG. Among the patterns shown in Fig. 10, the difference between the movement pattern shown in column A and the movement pattern shown in column B is that - degree stagnation (
The difference is whether the vehicle passes through (see mark ◎ in the figure) or only passes through (see mark ◎ in the figure). In this case, a return to the origin will always occur in (1). In the figure, "0°" indicates Fail, and "1" indicates Pa5s. In addition, in this example, 4 chips (
That is, the mosaic pattern is set in units of 4 bits, but of course the mosaic pattern is not limited to this, and a mosaic pattern in other units, for example, 16 chips (16 bits) may be used. However, in this case, the operation pattern becomes complicated, so it may not be suitable for small-scale locations.

Next, the processing of the chip end will be explained using FIGS. 11 to 16.

(1) Pa5s/Fail data area setting r P
The storage area for "a5s/Fai 1 data" is actually secured by four memory boards 41 to 44 (FMI-FM4), which are two-dimensionally configured in the X-Y direction, as shown in FIG. These memory boards 41 to 44 have chip No.
(F M 1 ), Pa5s/Fail data (F
M2), tip end (FM3) and final tip (FM4)
), and the data storage addresses of the memory boards 41 to 44 correspond to the X-Y movement of the wafer stage, and are set depending on whether the wafer stage has moved n indexes in the X and Y directions. Note that in the initial state, all data on the memory boards 41 to 44 are set to "°0°".

As shown in Fig. 12, at the time of PT or ink mark reading, X-
Determine the size of Y. In this case, set X and Y so that they are always even numbers.

In the figure, the numbers on the chip indicate the PT order, the symbol ■ indicates the starting point, and the solid line with an arrow indicates the inspection scanning direction.

(2) Storing Pa5s/Fail data during PT (first
(See Figure 2) ■Return the wafer stage to the zero point in the virtual area.

(3) At the start of PT, the 3 indexes until the sensor detects the chip end only move in the X direction.

(2) Set the proper operation so that PT is executed or canceled from the next chip after the sensor detects the chip end.

■Start PT from X=4th chip.

(2) Store the PT result of X=4th chip at the address of the memory board 42 (FM2) determined in conjunction with the movement of the wafer stage.

■Then, repeat the operation of ■ according to the normal blobbing operation.

(2) In this case, it is also possible to perform the operation (2) using software. That is, the chip area within the thick solid line in FIG. 12 is set in advance, and the wafer stage is moved in accordance with this outline.

■Which of the above ■ or ■ actions will cause the Eva Stage to
The basic operation is to store data at the corresponding address on the memory board in response to the movement of -Y.

[3] Storing Pa5s/Fail data when reading ink marks In this case, in the above-mentioned item [2], PT can be replaced with ink mark reading, and the processing method is the same.

[4] Chip end processing (processed by software) ■The following processing is performed on the memory board that stores the PT results or ink mark read results.

■Fill "1" to all addresses 1 (first column) and 12 (last column) of column X.

■As shown in FIG. 13, fill in "1" in the address of endpoint [F].

(2) Reset the chip Nα as shown in FIG.

(2) By solving the reset data, Pa5s/Fail data as shown in FIG. 14 is created.

[5] Setting of chip end data
data” to the “operation pattern data” shown in the same figure (b).
When converting to rPass/FailPa5s,
If there is at least one “1” in the /Fail data, “
Set 1”.

[6] Operation pattern at the chip end The details of the operation pattern at the chip end are shown in Figures 16 (a) and (b).
There are two modes as shown in (a) and (b) of the figure. In other words, as shown in FIG. 5(a), there is a two-index shift to the right and a one-index shift upward, and a two-index shift to the right and a downward one-index shift as shown in FIG. 2(b). There are two cases.

[7] Chip end operation ■Chip end data “1” in the “operation pattern data”
Count the number (N).

(2) The operation of FIG. 16(a) or FIG. 16(b) in item [6] mentioned above is determined by that number. For example, (N) Chip end operation 1 None 2 Pattern 3 in Fig. 16(a) None 4 Pattern 5 in Fig. 16(b) None 6 Pattern 7 in Fig. 16(a) None 8 Fig. 16(b) Pattern (2) That is, when (N) is an even number, the sequence of FIG. 16(a)→FIG. 16(b)-FIG. 16(a)-FIG. 16(b) is repeated.

[8] Upward operation/downward operation ■ Once the chip end enters the chip end operation shown in FIG. 16 (a) or the chip end operation shown in FIG. 16 (b), the operation in the X direction will be as shown in the next figure 16. It is assumed that the flag will not be cleared until the operation (a) or (b) is performed.

(2) Moreover, by taking correspondence between the chips Nα as shown in FIG. 13, the basic operation of 1→2→4→8 can be maintained even in the upward direction.

(2) The selection of up and down in the "motion pattern table" is selected in association with the motion shown in FIG. 16(a) and the motion shown in FIG. 16(b) of (2) above.

Next, the effect will be explained.

FIG. 17 is a flowchart showing a processing method when the semiconductor device manufacturing method is applied to a direct die bonding apparatus, and in the figure, Pn (n=1.2, . . . ) indicates each step of the flow. When the PT is completed, this flow starts (step PI). At P2, the PT results are output to a floppy disk, and at P, the presence or absence of ink marks is read from the wafer surface. In P4, based on these data, Pa5s as shown in Fig. 18(a)
/Fail data is created and this Pa5s/Fail data is stored in the Pa5s/Fail data storage section 24. Pa5s/Fail indicated by *1 in Fig. 18(a)
"1"'0" means that Pa5s is 1" and Fail is 0, and the column indicating whether or not it is a chip end indicated by *2 is "1°" for chip end and "0" for others. , furthermore, *3
The column indicating whether it is the final chip or not indicates that the final chip is 1"
, and others are "0". Note that there are two methods for detecting the chip end: a method using a sensor and a method using software to perform arithmetic processing based on the chip size measured from the outer angle of the wafer, and the method is specifically as explained in FIGS. 11 to 16.

Next, P compresses the Pa5s/Pa1l data into a mosaic pattern of 4 chips and converts it into an operation pattern.
12(b) based on the Pa5s/Fail data compressed by 4 chips as shown in FIGS. 18(a) and (b).
The motion pattern data shown in FIG. 1 is created and stored in the motion pattern storage section 26. Here, the operation pattern shown in FIG. 18(b) is the operation pattern shown in FIG. 10 described above. For example, the operation pattern Nα14 of the chip group Nα1 shown in FIG. 1 to 4 are regarded as one pattern, and this compressed chip group 1 is operated in an operation pattern NIIL14 as shown in FIG. Therefore, at the chip end, the operation pattern as shown in FIG. 16 is selected alternately upward and downward.

Then, set the wafer at the starting point at P, and
8, and the operation pattern is checked at P9 with reference to the operation pattern data shown in FIG. 18(b). P.I.
At G, the operation of the X-Y table 2 is set based on this operation pattern data, and at pH, the X-Y table 2 is operated according to the operation pattern table as shown in FIG. 18(C). Here, the operation of the X-Y table 2 is executed in steps P16 to P2°, which will be described later. The motion pattern table is data that specifically describes the movements of the X-axis and Y-axis for 16 patterns (16 patterns if 4 chips are one group), and the upstream, Downward refers to the movement of the wafer as shown in FIG. 18(d). Next, it is determined whether or not the X-Y table 2 is stopped based on the pH, and when it is stopped, the air tweezers 5 are set using the PI3.
, and if it is not stopped, return to P. The operation of the air tweezers 5 is executed in steps PZI to pit, which will be described later. At Pl, it is determined whether or not it is the last chip. If it is the last chip, it is determined at P1 whether it is the last wafer. If it is the last wafer, the current process ends. On the other hand, if it is not the final chip in Pl4, it returns to P, and if it is not the final wafer in PIS, it returns to P.

At P4, an operation pattern is set, and at P17, the operation pattern table shown in FIG. 18(C) is referred to according to this operation pattern. Next, data specifically describing the movement of the X-axis and Y-axis in pHl is sent to the X-Y table operation control unit 28.
, the X-Y table 2 is operated by the X-Y table operating mechanism 29 at Pl9, and if there is a Pt
Press O to pause.

On the other hand, in PzI, the air tweezers 5 are lowered and the chip is sucked from the wafer with P. Next, the air tweezers 5 are raised with Po, moved to the intermediate table 7 with pz4, and lowered with pzs. Then p
The chip is released to the intermediate table 7 with th, and returned to the origin with PR"r.

As described above, in this embodiment, during the bonding of the n-th wafer 21, the non-defective product/defective product of the n+1-th wafer 22 is identified, and the non-defective product/defective product status after PT is
A mosaic pattern is formed for each chip, and the movement of the X-Y table 2 is fixed to 16 patterns.

Therefore, the movement of the X-Y table 2 can be changed from sequential movement as in the conventional example to movement over the shortest distance, significantly reducing the Pa5s/Fail recognition time (index time) by more than 25%. be able to.

As a result, throughput in direct die bonding can be improved.

19 and 20 are diagrams showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention, and this embodiment is an example in which the present invention is applied to a chip surface inspection device. In describing this embodiment, the same components as those of the first embodiment shown in FIGS. 5 to 18 are given the same reference numerals, and the explanation of the overlapping parts will be omitted.

Conventionally, as shown in FIG. 22, the turntable 12 is moved manually or automatically, the chip surface is inspected, and both PTPass and Fai products are inspected for -degrees, and after recognizing Fail products as Fail, Move to next chip. Movement of the turntable was sequential.

In this embodiment, the direction of movement of the turntable 12 is automatically moved based on information stored and determined at the PT stage. The Pa5s product pauses and does not move to the next chip until a human restarts it. In addition, Fail products are -
Move to the next Pa5s product without stopping. The specific configuration is shown in FIG. 19, in which the operation pattern stored in the operation pattern storage section 26 is used as a turntable control signal for controlling the turntable 12 together with a restart instruction signal from the restart instruction circuit 35. The turntable operation control unit 36 calculates control values for controlling the turntable 12 based on these data, and transmits the calculation results to the turntable operation mechanism 3.
Output to 7. The turntable operating mechanism 37 operates the turntable 12 based on the control value.

Next, the effect will be explained.

FIG. 20 is a flowchart showing a processing method when the semiconductor device manufacturing method is applied to a chip surface inspection device, and steps that perform the same processing as in FIG. 17 of the first embodiment are given the same numbers. The explanation will be omitted, and the contents will be explained by attaching step numbers surrounded by O marks to different steps.

In FIG. 20, when the X-Y table 2 is stopped at Ptz, the turntable 12 is automatically moved to inspect the chip surface based on the data stored and determined at the PT stage at P31, and restart processing is performed at P32. , that is, Pa5s
The product temporarily stops and does not move to the next chip until a human instructs to restart, and the Fai1 product moves to the next Pa5s product without pausing, and then proceeds to PI3.

Therefore, in this embodiment as well, the movement of the turntable 12 is patterned as in the first embodiment, so
The travel time of the turntable 12 can be shortened, and the time required to recognize failed products can be significantly reduced by making it possible to inspect only non-defective products. As a result, throughput can be significantly improved.

〔Effect of the invention〕

According to the present invention, it is possible to shorten the time required to sort out good/defective chips. In particular, in direct die bonding, the indexing time can be reduced by 25% or more, and in chip surface inspection, it is no longer necessary to identify defects, greatly improving work efficiency. The degree of this effect is P
Depends on T yield.

[Brief explanation of the drawing]

Figures 1 to 4 are diagrams for explaining the present invention in detail. Figure 1 is a diagram showing a mosaic pattern when the non-defective/defective product status is made into a mosaic pattern of 4 chips, and Figure 2 is a diagram showing a mosaic pattern in units of 4 chips. 3 is a diagram showing an example of a pattern in the moving direction, FIG. 4 is a diagram showing a reduction in the number of steps, and FIGS. 5 to 18 are semiconductor devices according to the present invention. FIG. 5 is a diagram for explaining the Gui bonding, FIG. 6 is a diagram showing the movement of the air tweezers, FIG. 7 is a block configuration diagram, Figure 8 is another block configuration diagram, Figure 9 is a diagram showing the weighting of the mosaic pattern in units of 4 chips, Figure 10 is a diagram showing details of its operation pattern, and Figure 11 is a configuration diagram of the memory board. , Figure 12 shows the Pa5s
Figure 13 is a diagram to explain the processing at the chip end. Figure 14 is a diagram showing the Pa5s/Fail data. Figure 15 is the Pa5s data area. /Fail data and operation pattern data, Figure 16 is a diagram showing the operation pattern of the chip end, and Figure 17 is a diagram showing the operation pattern of the chip end.
The figure is a flowchart showing the processing method when applied to the direct die bonding equipment, and Figure 18 is the P
A5s/Fail data, operation pattern data, and operation pattern data are shown in FIGS. 19 and 20, and FIG. , Figure 20 is a flowchart showing the processing method when applied to the chip surface inspection equipment, Figures 21 and 22 are diagrams showing the conventional manufacturing method of semiconductor devices, and Figure 21 explains the Gui bonding. FIG. 22 is a diagram for explaining the chip surface inspection. 1... Wafer, 2... X-Y table, 3... Camera, 4... Floppy disk, 5... Air tweezers, 6...Divided chip, 7...Intermediate table, 8...Guicolet, 9...Package, 11...Microscope, l2 ...Turntable, 13...Wafer, 21...Nth wafer, 22...N+1th wafer, 23--Pas
s/ Fail detection section, 24...Pa5s/F
ail data storage unit, 25...data processing unit, 26...operation pattern storage unit, 27...
・Guicolet control circuit, 28...X-Y table operation control unit, 29...X-Y table operation mechanism, 30...Air tweezers operation control unit, 3
1... Air tweezers operating mechanism, 32...
...PT. 33... Floppy disk, 34...
- Disk drive device, 35...Restart instruction circuit, 36...Turntable operation control section, 37...Turntable operation mechanism, 41-4
4...Memory board. Fig. 1 shows the basic process in the direction of movement to explain the principle. Fig. 2 shows the basic process in the moving direction. Fig. 1 shows the structure of the memory board in the first embodiment. Figure 3 for explaining the process of detection scanning direction Figure 2 for explaining the setting and storage of the Pa5s/Fail data area in the first embodiment Figure 4 shows example Pa5s/Fail data. Figure 18. Figure 2 illustrates conventional chip surface inspection.

Claims (1)

[Claims] A mosaic pattern in which the non-defective/defective states of a plurality of chips on a wafer are tested, and the non-defective/defective states of the chips on the wafer are determined by a predetermined chip unit as one group after the test is completed. The feature is that the chip position of each chip is weighted, the movement from good to good is fixed in a predetermined movement pattern, and the selection of good/defective products is achieved in the shortest process. A method for manufacturing a semiconductor device.