JPH03129746A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent that a potential between a lead and a reference potential becomes a prescribed value or higher even when a metal member comes into contact with a tape face and a lead face and to prevent an electrostatic breakdown of a semiconductor chip by a method wherein a reference potential of the chip is decided in advance via an interconnection pattern for reference- potential supply use. CONSTITUTION:An opening part 18 into which an LSI chip 13 is inserted is opened in advance in each lead pattern region 12 of a tape 11. The LSI chip 13 is inserted into the opening part 18; a plurality of electrode pads 17,... formed on the surface of the chip 13 and a plurality of leads 14 in the lead pattern region 12 are connected by a thermocompression bonding method or the like; the LSI chip 13 is inner-lead-bonded to the lead pattern region 12. The individual leads 14 are fixed to the tape 11 by using an adhesive 19. A reference potential is supplied to each LSI chip 13,... via an interconnection pattern 15 for reference-potential supply use and via individual leads 14A for reference-potential supply use; a high voltage applied to the leads is made to escape to the reference potential through an internal circuit of each LSI chip 13,....

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) This invention relates to a semiconductor device in which a semiconductor chip is mounted on an insulating film, and a method for manufacturing the semiconductor device.

(Prior technology) As a mounting method for LSI (large scale integrated circuit), YuruT
A B (Tape Automated Bondi
ng) type is generally known.

FIG. 19 is a schematic top view of the conventional TAB type LSI. In the figure, 11 is a film-like tape made of insulating resin; 12. ...respectively. 4 Thin film and 7
Esegusu, Yu and 1. 13. The lead pattern area formed from 13. ... are LSI chips, respectively.

Each of the above lead pattern regions 12. ..., each LSI
Chip 13. A plurality of leads 14 consisting of inner leads and outer leads for supplying power supply potential and inputting/outputting signals. ...is provided. Then, each lead pattern area 12. ..., a plurality of leads 14. ... are electrically connected by each group located in the center of the...

FIG. 20 is a schematic top view of another conventional TAB type LSI. This corresponds to each lead pattern area 12.・
Multiple leads of 14. ... are short-circuited by a short-circuit conductive pattern 51, which is the other free end of the outer lead.

With such a configuration, even if a large voltage due to a surge or the like is applied to any of the leads 14, all the leads 14
．． ... are made equal potential by the shorting conductive pattern 51, so no potential difference occurs between each lead, and the LS
Electrostatic damage to the I-chip can be prevented.

(Problem to be Solved by the Invention) However, in the tape shown in Fig. 19, the material of the tape is easily charged with static electricity, so when feeding the tape during an operation test, the metal members such as the tape feeding mechanism are connected to the tape surface and the lead surface. When the lead is contacted at the same time, a high voltage is applied to the lead and the L
There is a problem that the SI chip is damaged by electrostatic discharge.

On the other hand, in the case of the one shown in FIG. 20, each lead is short-circuited by the short-circuiting conductive pattern, so there is a problem that the conduction operation cannot be carried out.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to enable energized operation,
It is also an object of the present invention to provide a semiconductor device and a method for manufacturing a semiconductor device that can also prevent electrostatic damage to semiconductor chips.

[Structure of the Invention] (Means for Solving the Problems and Their Effects) A semiconductor device of the present invention includes an insulating film and a plurality of leads formed on one surface of the film, each of which is composed of a plurality of leads. and a wiring pattern for supplying a group dIL potential, which is electrically connected to each lead for supplying a reference potential among the plurality of leads in each of the plurality of lead pattern regions and extending in the longitudinal direction of the film. It is characterized by having the following.

Further, the semiconductor device of the present invention includes an insulating film,
A plurality of lead pattern areas formed on one surface of the film, each consisting of a plurality of leads, and electrically connected to each lead for supplying a reference potential among the plurality of leads in each of the plurality of lead pattern areas. It has a wiring pattern for supplying a group IlfI potential that is connected and extended in the longitudinal direction of the film, and a plurality of electrodes, and is placed on each of the plurality of lead pattern regions, and each of the plurality of electrodes is placed on each of the plurality of lead pattern regions. It is characterized by comprising a plurality of semiconductor chips electrically connected to each lead.

Furthermore, the method for manufacturing a semiconductor device of the present invention includes a step of pasting a conductive thin film on the surface of an insulating film, and selectively removing the conductive thin film, each of which is composed of a plurality of leads. a step of forming a plurality of lead pattern regions, and a reference potential extending in the longitudinal direction of the tape, which is electrically connected to each lead for supplying a reference potential among the plurality of leads in each of the plurality of lead pattern regions; A step of forming a supply wiring pattern, placing a semiconductor chip on each of the lead pattern areas, and electrically connecting each of the plurality of electrodes provided on the semiconductor chip and each of the plurality of leads, respectively. The process of connecting and the state in which the reference potential is supplied to the wiring pattern for supplying the reference potential,
The method is characterized by comprising a step of cutting out each of the plurality of lead pattern regions on which semiconductor chips are mounted together with the film.

That is, in this invention, since the reference potential of the semiconductor chip can be determined in advance through the wiring pattern for supplying the reference potential, there is no possibility that a metal member such as a tape feeding mechanism contacts the tape surface and the lead surface simultaneously when feeding the tape. Even if
The potential between this lead and the reference potential does not exceed a predetermined value, and electrostatic damage to the chip can be prevented. Further, since the plurality of leads in each lead pattern area on the tape are electrically isolated from each other, there is no problem in the current supply operation.

(Example) Hereinafter, the present invention will be explained by way of examples with reference to the drawings.

FIG. 1 is a top view showing the structure of a first embodiment of a semiconductor device of the present invention.

In FIG. 1, 11 is a film-like tape made of insulating resin, such as polyester Kapton resin;
12. . . . are lead pattern regions formed by patterning a metal thin film, for example, a Cu thin film; 13. ... are LSI chips, respectively.

Each of the above lead pattern regions 12. ..., each LSI
A plurality of leads 14 consisting of inner leads and outer leads for supplying power supply potential to the chips H, . . . and inputting/outputting signals. ...is provided. and,
Each lead pattern area 12. A plurality of leads 14. ′ of each one of...:.

They are electrically connected and inner lead bonding is performed.

Furthermore, each lead pattern area 12 of the tape 11,
A linear wiring pattern 15 for supplying the base 11i is provided along the extending direction of the tape at one edge in the width direction of the forming surface. This wiring pattern 15 includes each of the lead pattern regions 12. Multiple leads in... 14. . . , each lead 14A for supplying a reference potential, . . . is electrically connected. Further, perforations 16 for feeding the tape are formed at regular intervals on both ends of the tape 11 in the width direction.

FIG. 2 shows each lead pattern area 12. . . . is a perspective view showing the external shape of the LSI chips 13 to which the die 6 is bonded. This LSI chip IS is
It is constructed by forming a desired circuit on a P-type or N-type silicon semiconductor substrate by well-known impurity diffusion treatment, wiring formation technique treatment, etc. On the surface of the substrate, there are a plurality of electrode pads 17 for supplying a power supply potential from the outside of the chip and for exchanging signals with the outside. ...
is formed.

FIG. As shown in the figure, each lead pattern area 12 of the tape 11 has an opening 18 formed in advance into which the LSI chip 13 is inserted. Then, the LSI chip 13 is inserted into this opening 18.
The plurality of electrode pads 17 . are inserted into the chip 13 and formed on the surface of the chip 13 . ... Toriido pattern area 12
For example, each of the plurality of leads 14 is heated. Note that each lead 14 is fixed to the tape 11 with an adhesive 19.

In such a configuration, each LSI chip 13. . . . When energizing is performed, a tape feeding mechanism (not shown) is used to move each LSI chip 13. ... are sequentially transported to the energized position. At this time, the reference potential supply wiring pattern 15 on the tape 11 is supplied with a U quasi-potential necessary to operate the LSI chip, such as the Ov ground potential or a positive or negative power supply potential. .

By the way, since the material of the tape 11 is easily charged with static electricity, it is charged with static electricity during the above-mentioned conveyance. When a metal member such as a tape feeding mechanism contacts the tape surface and the lead surface at the same time, a high voltage due to the static electricity is applied to the lead. However, each LSI chip 13. Since a reference potential is supplied to each LSI chip 13 .
... is released to the U quasi-potential through the internal circuit. Therefore, the potential of the leads to which a high voltage due to static electricity is applied is suppressed to a predetermined low potential, thereby preventing the LSI chip from being damaged by static electricity as in the prior art.

FIG. 4 is a top view showing the structure of a second embodiment of the semiconductor device of the present invention.

In this embodiment, wiring patterns 15° 15 for supplying a reference potential are provided on both edges of the tape 11 in the width direction along the extending direction of the tape, and each lead pattern area 12. In the width direction of the tape H, surrounding...
A linear wiring pattern 20 is formed to short-circuit both wiring patterns 15 and 15.

In this case, each lead pattern area 12. Multiple leads in... 14. Among the leads 14A, . . . for supplying a reference potential are located approximately at the center of the tape H, and these leads 14A, . ing.

FIG. 5 is a top view showing the structure of a third embodiment of the semiconductor device of the present invention.

In this embodiment, instead of the linear reference potential supply wiring pattern 15 in the first embodiment shown in FIG. A wiring pattern 21 for supply is provided.

FIG. 6 is a top view showing the structure of a fourth embodiment of the semiconductor device of the present invention.

In this embodiment, instead of the linear reference potential supply wiring patterns 15, 15 in the second embodiment shown in FIG. Wiring patterns 22 and 22 for supplying a reference potential are provided. In this case, each lead pattern area 12. Each lead 14 for supplying reference potential of...
A, . . . are located at the ends of the tape 11, as in the embodiments of FIGS. 1 and 5.

FIG. 7 is a top view showing the structure of a fifth embodiment of the semiconductor device of the present invention.

In this embodiment, instead of the linear wiring pattern 2o in the fourth embodiment shown in FIG. , each lead pattern area 12. ...
A pattern for supplying a reference potential is provided in most of the area except for the area where the reference potential is supplied.

FIG. 8 is a top view showing the structure of a sixth embodiment of the semiconductor device of the present invention.

In this embodiment, each lead pattern area 1 of the tape 11 is
2. The surface opposite to the surface where ... is formed, that is, the tape 1
1, a linear reference potential supply wiring pattern 24 is provided at one edge in the width direction of the tape 11 along the extending direction of the tape, and a plurality of linear wiring patterns 25. ...is provided. and,
One end of each wiring pattern 25 is connected to the reference potential supply wiring pattern 24, and the other end extends to the vicinity of each opening 18. In the vicinity of each opening 18, each wiring pattern 2!5 is electrically connected to the back surface of each LSI chip 13 by a bonding wire 2G.

FIG. 9 is a partially cross-sectional view of one structure near the lead pattern area 12 in the embodiment shown in FIG. 8. In this embodiment, bonding wires 2B are Since it is necessary to connect the two, a metal layer 27 is previously formed on that surface.

Normally, the substrate of an LSI chip is set to the ground potential or 7T [potential, so even with this configuration, the reference potential necessary for operating the LSI chip is provided in the wiring pattern 24 for supplying the reference potential. If supplied, electrostatic damage to the LSI chip can be prevented for the same reason as described above.

FIG. 10 is a top view showing the structure of the seventh embodiment of the semiconductor device of the present invention.

In this embodiment, on the back side of the tape, wiring patterns 2 for supplying reference potential are provided at both edges in the width direction of the tape.
4.24 are provided along the extending direction of the tape, and a plurality of the linear wiring patterns 25 are provided for each opening 18, and each wiring pattern 25 and each LS
The back surface of the I-chip 13 is electrically connected to the back surface of the I-chip 13 by each bonding wire 26.

FIG. 11 is a top view showing the structure of the eighth embodiment of the semiconductor device of the present invention.

In this embodiment, instead of the linear reference potential supply wiring pattern 24 in the sixth embodiment shown in FIG. A wiring pattern 28 for supply is provided.

FIG. 12 is a top view showing the structure of a ninth embodiment of the semiconductor device of the present invention.

In this embodiment, the strip-shaped reference potential supply wiring patterns 28 and 28 in the embodiment shown in FIG. 11 are provided on both edges of the tape in the width direction on the back surface of the tape.

FIG. 13 is a top view showing the structure of a tenth embodiment of the semiconductor device of the present invention.

In this embodiment, a pattern 29 for supplying a reference potential is provided on the entire surface of the tape except for each opening 18 on the back surface of the tape.

FIG. 14 shows the structure of an eleventh embodiment of the semiconductor device of the present invention, in which FIG. 14(a) is a top view, FIG. 14(b) is a back view, and FIG. 14(c) is a top view. FIG.

In this embodiment, as shown by diagonal lines in FIG. 14(a), a strip-shaped reference potential supply wiring pattern 21 similar to the embodiment of FIG. 5 is provided on the surface side of the tape 11. This is what I did. Furthermore, as shown in FIG. 14(b), a plurality of linear wiring patterns 25. ...is provided. One end of each of these wiring patterns 25 is connected to the tape 1.
The back side of each LSI chip 13 pushed into each opening 18 of 1 is electrically connected by a bonding wire 26. Moreover, each other end of each wiring pattern 25 is
Each of the wiring patterns 30 is connected to a plurality of wiring patterns 30 selectively provided on the side surface of the tape 11.

Therefore, in this embodiment, the back side of each LSI chip 13 is connected to the reference potential supply wiring pattern 21 provided on the front side of the tape 11 via the bonding wire 26, the wiring pattern 25, and the wiring pattern 30. It is connected.

FIG. 15 shows the configuration of a twelfth embodiment of the semiconductor device of the present invention, in which FIG. 15(a) is a top view, FIG. 15(b) is a back view, and FIG. 15(c) is a top view. FIG.

In this embodiment, as shown by diagonal lines in FIG. 15(a), a strip-shaped reference potential supply wiring pattern 22 similar to the embodiment of FIG. 6 is provided on the surface side of the tape 11. This is what I did. Furthermore, as in the case of FIG. 14, a plurality of linear wiring patterns 25 are provided on the back side of the tape H.
．． ... are provided, and each one end of each of these wiring patterns 25 is connected to each LS inserted into each opening 18 of tape 11.
It is electrically connected to the back surface of the I-chip 13 by a bonding wire 26, and the other end of each wiring pattern 25 is connected to a plurality of wiring patterns 30 selectively provided on the side surface of the tape 11. . Therefore, also in the case of this embodiment, the surface of each LSI chip 13 is connected to the reference potential supply wiring pattern provided on the surface side of the tape 11 via the bonding wire 26, the wiring pattern 25, and the wiring pattern 30. 22.

FIG. 16 shows the structure of a thirteenth embodiment of the semiconductor device of the present invention, in which FIG. 16(a) is a top view, FIG. 16(b) is a back view, and FIG. 16(C) is a top view. FIG.

In this embodiment, as shown in FIG. 16(a), the fourth
Similar to the embodiment shown in the figure, on the surface of the tape 11, the tape 1
Wiring pattern 1 for supplying reference potential on both widthwise edges of 1
5.15 are provided along the extending direction of the tape, and a linear wiring pattern 20 is formed to short-circuit both wiring patterns 15.15. Furthermore, the first
As shown in FIG. 6(b), a plurality of linear wiring patterns 25.6 are formed on the back side of the tape 11. It was designed to provide... Each end of each of these wiring patterns 25 is electrically connected to the back surface of each LSI chip 13 inserted into each opening 18 of tape H by bonding wire 2G. Further, in this embodiment, a through hole 31 is formed in the middle of the wiring pattern 15, passing through both the front and back surfaces, and the inside of the through hole 31 is plated with metal. Therefore, in the case of this embodiment, the back side of each LSI chip 13 is connected to the reference potential supply provided on the front side of the tape 11 via the bonding wire 26, the wiring pattern 25, the through hole 31, and the wiring pattern 20. It is connected to the wiring pattern 15.15.

Next, a method for manufacturing a semiconductor device having the above structure will be described below.

First, as shown in the sectional view of FIG. 17, for example, perforations L6 and L as shown in FIGS.
A metal thin film, for example, a Cu thin film 41, is attached via an adhesive 19 to the surface of the tape 11 in which an opening L8C (not shown in FIG. 17) for inserting an SI chip is formed. Said 8th
When forming a conductive pattern on the back side of the tape 11 as in the embodiment shown in the figure, a Cu thin film 41 is attached to both sides of the tape 11.

Next, the Cu thin film 4I is patterned by photolithography to form a plurality of leads 14. Multiple leads consisting of...? Turn area 12. . . . and the wiring pattern 15 for supplying the quasi-potential are formed at the same time.

Next, from each opening 18 formed in the tape H, each LS
The I-chip (3) is pushed in, and the plurality of pad electrodes 17. . By doing so, inner lead ◆bonding is performed as shown in the cross-sectional view of FIG. 3.

Thereafter, each LSI chip 13 is covered with potting resin on both the front and back surfaces or only on the front surface, as required, and the tape 11 is wound up and shipped.

When the semiconductor device of the present invention is mounted, the tape 11 is moved from the wound state by the tape feeding mechanism.
are sent out one after another, each lead pattern area 12 is cut out using a cutter or the like at the outer lead bonding position, and outer lead bonding is performed.

FIG. 18 is a top view showing the state in which the tape 11 is cut out with a cutter or the like and separated into individual semiconductor devices. After being separated into individual semiconductor devices, the reference potential supply leads 14A in each of the lead pattern regions 12 have substantially the same shape as other leads, and are connected to the reference potential supply wiring patterns 15. There will be no inconvenience caused by this.

Note that the present invention is not limited to the above-mentioned embodiments, and various modifications are possible. For example, in the above embodiment, the case where a Cu thin film is used as the metal thin film has been described, but other metal thin films may be used.

[Effects of the Invention] As explained above, according to the present invention, the leads connected to the semiconductor chip can be provided on the tape without short-circuiting each other, so that the conduction operation is not affected.
Electrostatic damage can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a top view showing the configuration of a first embodiment of the semiconductor device of the present invention, FIG. 2 is a perspective view showing the external shape of an LSI chip used in the semiconductor device of the above embodiment, and FIG. FIG. 4 is a top view showing the configuration of the second embodiment of the semiconductor device of the present invention, and FIG. 5 is a cross-sectional view showing the LSI chip shown in FIG. 6 is a top view showing the structure according to the fourth embodiment of the semiconductor device of the present invention, and FIG. 7 is a top view showing the structure according to the fourth embodiment of the semiconductor device of the present invention. FIG. 8 is a top view showing the structure of the sixth embodiment of the semiconductor device of the present invention, and FIG. 9 is a top view showing the structure of the lead pattern area in the embodiment of FIG. 8. 10 is a top view showing the configuration of a seventh embodiment of the semiconductor device of the present invention, and FIG. 11 is a top view showing the configuration of the eighth embodiment of the semiconductor device of the present invention. FIG. 12 is a top view showing the structure of a ninth embodiment of the semiconductor device of the present invention, FIG. 13 is a top view showing the structure of the tenth embodiment of the semiconductor device of the present invention, and FIGS. (c) shows the structure according to the eleventh embodiment of the semiconductor device of the present invention;
Figure 4(a) is a top view, Figure 14(b) is a back view,
FIG. 15(C) is a side view, FIGS. 15(a) to 15(c) show the configuration of a twelfth embodiment of the semiconductor device of the present invention, FIG. 15(a) is a top view, and FIG. Figure (b) is a back view, Figure 15 (c) is a side view, Figures 16 (a) to (c)
16(a) shows a top view and FIG. 16(a) shows a structure according to a thirteenth embodiment of the semiconductor device of the present invention.
b) is a back view, FIG. 16(c) is a side view, FIG. 17 is a sectional view for explaining the method of manufacturing a semiconductor device of the present invention, and FIG. 18 is a top view for explaining the method. FIGS. 19 and 20 are top views of conventional semiconductor devices, respectively. DESCRIPTION OF SYMBOLS 11... Film-like tape, 12... Lead pattern area, 13... LSI chip, 14... Lead, 14A... Lead for supplying reference potential, 15... Lead for supplying reference potential Wiring pattern, 1B... Perforation, 17... Pad electrode, 18... Tape opening, 19... Adhesive, 20, 24.25... Linear wiring pattern, 21.22 .23゜28... Band-shaped reference potential supply wiring pattern, 26... Bonding wire, 27... Metal layer, 29... Reference potential supply pattern, 30... Wiring pattern, 31... Through hole, 41... CU thin film.

Claims (3)

[Claims] (1) An insulating film, a plurality of lead pattern areas formed on one surface of the film, each consisting of a plurality of leads, and a reference potential among the plurality of leads in each of the plurality of lead pattern areas. electrically connected to each supply lead,
A semiconductor device comprising a wiring pattern for supplying a reference potential extending in the longitudinal direction of the film. (2) an insulating film; a plurality of lead pattern areas formed on one surface of the film, each consisting of a plurality of leads; and a reference potential among the plurality of leads in each of the plurality of lead pattern areas; electrically connected to each supply lead,
It has a wiring pattern for supplying a reference potential extending in the longitudinal direction of the film, and a plurality of electrodes, and is placed on each of the plurality of lead pattern areas, and each of the plurality of electrodes is connected to each of the plurality of leads, respectively. A semiconductor device comprising a plurality of semiconductor chips that are electrically connected. (3) A step of pasting a conductive thin film on the surface of an insulating film, and selectively removing the conductive thin film to form a plurality of lead pattern regions each consisting of a plurality of leads. electrically connected to each lead for supplying a reference potential among the plurality of leads in each of the plurality of lead pattern regions;
forming a reference potential supply wiring pattern extending in the longitudinal direction of the tape; placing a semiconductor chip on each lead pattern area;
A step of electrically connecting each of the plurality of electrodes provided on the semiconductor chip and each of the plurality of leads, and a step of electrically connecting each of the plurality of electrodes provided on the semiconductor chip to each of the plurality of leads; A method for manufacturing a semiconductor device, comprising the step of cutting out each of the plurality of lead pattern regions on which are placed the film together with the film.