JPH03127842A - Wire bonding method and equipment - Google Patents
Wire bonding method and equipmentInfo
- Publication number
- JPH03127842A JPH03127842A JP1266667A JP26666789A JPH03127842A JP H03127842 A JPH03127842 A JP H03127842A JP 1266667 A JP1266667 A JP 1266667A JP 26666789 A JP26666789 A JP 26666789A JP H03127842 A JPH03127842 A JP H03127842A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- wire
- temperature
- heating
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000006243 chemical reaction Methods 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 10
- 230000003247 decreasing effect Effects 0.000 abstract description 3
- 238000003825 pressing Methods 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract 2
- 230000003685 thermal hair damage Effects 0.000 abstract 1
- 229910000765 intermetallic Inorganic materials 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 235000006040 Prunus persica var persica Nutrition 0.000 description 1
- 240000006413 Prunus persica var. persica Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009396 hybridization Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は複数の半導体チップを一つのパッケージに収容
する型の半導体集積回路に於けるワイヤボンディング処
理に関し、
ボンディングワイヤ材料とボンディング・バッド材料と
が反応して金属間化合物を形成するのを避けることを目
的とし、
集積回路パッケージの外部接続電極である金属リード片
の複数のステム部の各々に半導体チップを接着し、半導
体チップのボンディングパッドと前記金属リード片との
間をワイヤボンディングによって接続する際に、
ボンディング作業の終了した半導体チップは、ボンディ
ングパッド材料と前記ボンディングワイヤとの間に化学
反応が進行することのない温度まで、その他の半導体チ
ップとは独立に降温させる構成とする。[Detailed Description of the Invention] [Summary] The present invention relates to a wire bonding process in a semiconductor integrated circuit in which a plurality of semiconductor chips are housed in one package, and the present invention relates to a wire bonding process in which a bonding wire material and a bonding pad material react. For the purpose of avoiding the formation of intermetallic compounds in the integrated circuit package, a semiconductor chip is bonded to each of a plurality of stem portions of a metal lead piece that is an external connection electrode of an integrated circuit package, and the bonding pad of the semiconductor chip and the metal lead are bonded to each other. When connecting the semiconductor chip with the other semiconductor chip by wire bonding, the semiconductor chip after the bonding operation is heated to a temperature that does not allow chemical reaction to proceed between the bonding pad material and the bonding wire. The structure is such that the temperature is lowered independently.
また、半導体チップを個々に温度制御するための装置と
して、半導体チップが接着される複数のステム部を加熱
或いは冷却するための加熱ブロックが前記複数のステム
部の位置に合わせて配置され、この加熱ブロンクはその
各々が独立に温度制御されるものである装置が提供され
る。Further, as a device for individually controlling the temperature of semiconductor chips, a heating block for heating or cooling a plurality of stem parts to which semiconductor chips are bonded is arranged in accordance with the position of the plurality of stem parts, and this heating block is arranged to match the position of the plurality of stem parts. An apparatus is provided in which each of the broncs is independently temperature controlled.
本発明はワイヤボンディングに於ける加熱／冷却の処理
に関わり、特に、複数の半導体チップから成る集積回路
のワイヤボンディングに於けるこの種の処理に関わる。The present invention relates to heating/cooling processes in wire bonding, and more particularly to such processes in wire bonding integrated circuits comprising a plurality of semiconductor chips.
半導体集積回路（ＩＣ）の構成が複雑化するに伴い、複
数のＩｃチップを組み合わせて一つのパ・７ケージに集
積するハイブリッド化が行われるようになり、ワイヤボ
ンディングによって外部リードと接続する箇所の数も大
幅に増加している。As the configuration of semiconductor integrated circuits (IC) becomes more complex, hybridization, which combines multiple IC chips and integrates them into a single package, is being implemented, and wire bonding is used to connect external leads. The number has also increased significantly.
ワイヤボンディング作業では、ＩＣチップやリードフレ
ームのボンディング部を所定温度に加熱しておき、これ
にＡｕワイヤの先端を圧接すること、更に超音波振動を
併用することが行われる。In wire bonding work, the bonding portion of the IC chip or lead frame is heated to a predetermined temperature, and the tip of the Au wire is pressed against the bonding portion, and ultrasonic vibration is also used.
加熱温度は圧接のみの場合３００°Ｃ程度、超音波併用
の場合２００°Ｃ程度である。The heating temperature is about 300°C when only pressure welding is used, and about 200°C when ultrasonic waves are used together.
自動装置に於けるボンディングの所要時間は、バクーン
認識の時間を含めても、ワイヤ１本当たり０．５秒程度
であり、ワイヤ数が少ない場合はＩＣ１個当たりの処理
時間が短く、加熱の影響が不都合をもたらすことはない
が、ハイブリッドＩＣではワイヤ数が数十本或いはそれ
以上になることがあり、ＩＣ１個の処理時間が、昇温／
降温の時間を含めると１分を越える場合も生じている。The time required for bonding using automatic equipment is about 0.5 seconds per wire, including the time for back-up recognition, and if the number of wires is small, the processing time per IC is short, and the influence of heating Although this does not cause any inconvenience, hybrid ICs may have dozens or more wires, and the processing time for a single IC may increase due to temperature rise/
In some cases, it takes more than 1 minute, including the time for the temperature to fall.
ＩＣチップのボンディングパッドは通常Ａｇであり、ワ
イヤはＡｕであるから、このように長時間Ａ ｌ ／
Ａ ｕ接触部が高温下に置かれると、ＡｕＡｌ！、２や
Ａ ｕ ５Ａ Ｅ ２のような金属間化合物が生成する
。ボンディング部に金属間化合物ができると、接続抵抗
が増加し接着強度が低下する等の不都合がもたらされる
ので、その生成は極力回避するようにしなければならな
い。Since the bonding pads of IC chips are usually made of Ag and the wires are made of Au, the A l /
When the Au contact part is placed under high temperature, AuAl! , 2 and A u 5A E 2 are formed. If an intermetallic compound is formed at the bonding portion, it will cause disadvantages such as increased connection resistance and decreased adhesive strength, so the formation of such intermetallic compounds must be avoided as much as possible.
ワイヤボンディングの作業時間が長時間化することは、
初期にボンディングされたワイヤの接続部で金属間化合
物の生成する可能性が増すことであり、金属間化合物の
生成以外にも、チップ接着用のエポキシ・ペーストの熱
劣化といった問題が生しることにもなる。従って、ボン
ディングの所要時間が短縮し得ないのであれば、何らか
の方策を講して高温保持時間を実質的に短縮することが
必要になる。The long working time of wire bonding means that
This increases the possibility of intermetallic compounds forming at the initial bonded wire connections, which can also lead to problems such as thermal degradation of the epoxy paste used to attach the chip. It also becomes. Therefore, if the time required for bonding cannot be shortened, it is necessary to take some measures to substantially shorten the high temperature holding time.
（従来の技術と発明が解決しようとする課題〕従来この
ような問題に対処する特別な対策は講じられておらず、
処理温度をなるべく低くする他には、装置の放熱特性を
良好にし、全ワイヤのボンディングが終了した後、半導
体チップに熱応力を生しない範囲で速やかに降温するこ
とが行われている程度である。(Problems to be solved by conventional technology and inventions) No special measures have been taken to deal with such problems in the past.
In addition to keeping the processing temperature as low as possible, the only thing that can be done is to improve the heat dissipation characteristics of the equipment, and after all wire bonding is completed, the temperature is quickly lowered within a range that does not cause thermal stress on the semiconductor chip. .
このような対策は抜本的な解決策とはいえず、金属間化
合物を生しない時間内にボンディング出来るワイヤの本
数に限りがあるため、ワイヤ数の増加に追随し得ないと
いう問題がある。Such countermeasures cannot be said to be a fundamental solution, and there is a problem that the number of wires that can be bonded within a period of time without forming an intermetallic compound is limited, so that it cannot keep up with the increase in the number of wires.
本発明の目的は全ワイヤ数には無関係に、各ワイヤ毎の
加熱時間を短縮するボンディング処理法を提供すること
であり、そのための装置を提供することである。An object of the present invention is to provide a bonding process that reduces the heating time for each wire, regardless of the total number of wires, and to provide an apparatus therefor.
上記目的を遠戚するため、本発明のボンディング法では
集積回路パッケージの外部接続電極である金属リード片
の複数のステム部の各々に半導体チップを鑞付けし、半
導体チップのボンディングパッドと前記金属リード片と
の間をワイヤボンディングによって接続する際に、
ボンディング作業の終了した半導体チップは、ボンディ
ングパッド材料と前記ボンディングワイヤとの間に化学
反応が進行することのない温度まで、その他の半導体チ
ップとは独立に降温させることか行われる。In order to achieve the above object, in the bonding method of the present invention, a semiconductor chip is brazed to each of a plurality of stem portions of a metal lead piece, which is an external connection electrode of an integrated circuit package, and the bonding pad of the semiconductor chip and the metal lead piece are brazed to each other. When connecting the semiconductor chip with the other semiconductor chip by wire bonding, the semiconductor chip after the bonding operation is heated to a temperature that does not allow chemical reaction to proceed between the bonding pad material and the bonding wire. The temperature can be lowered independently.
また、半導体チップを個々に温度制御するための装置と
して、半導体チップが接着される複数のステム部を加熱
するための加熱ブロックが前記複数のステム部の位置に
合わせて配置され、この加熱ブロックはその各々が独立
に温度制御されるものである。Further, as a device for individually controlling the temperature of semiconductor chips, a heating block for heating a plurality of stem parts to which semiconductor chips are bonded is arranged in accordance with the position of the plurality of stem parts. Each of these is independently temperature controlled.
本発明ではハイブリッドＩＣを構成するＩＣチップを個
々に昇温／ｌ！！温することが可能なので、一つのチッ
プのワイヤボンディングが終了すれば、他のチップのボ
ンディングには無関係に温度を下げる。その結果ボンデ
ィング後の高温保持時間が著しく短縮されるので金属間
化合物の生成は進行せず、他の熱的障害も発生しない。In the present invention, the temperature of each IC chip constituting a hybrid IC is increased/l! ! Since wire bonding of one chip is completed, the temperature is lowered regardless of bonding of other chips. As a result, the high temperature holding time after bonding is significantly shortened, so that the formation of intermetallic compounds does not proceed and other thermal problems do not occur.
また、本来単一チップに集積し得る回路であっても、複
数のチップに分割してハイブリッド化し、本発明を適用
することによって、接続ワイヤ数が多いことに起因する
金属間化合物生成の問題を解決することが出来る。Furthermore, even if a circuit can originally be integrated on a single chip, by dividing it into multiple chips and hybridizing it, and applying the present invention, the problem of intermetallic compound formation caused by the large number of connecting wires can be solved. It can be solved.
第１図は本発明の実施例を示す模式図、第２図は実施例
の加熱ブロックの配置を示す図である。FIG. 1 is a schematic diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the arrangement of heating blocks in the embodiment.
以下、該図面を参照しながら本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図に於いて、複数のＩＣチップ１は金属のリードフ
レーム２のステム部３にエポキシ・ペースト等によって
接着されている。この接着処理は公知の方法によって、
本発明に関わる工程の前に実施されたものである。リー
ドフレームがボンディング位置に送られて来ると、各ス
テム部は加熱ブロック６に当接した状態となる。リード
フレームを構成する各金属リード片はタイバー４で連結
され、相対位置が固定されている。In FIG. 1, a plurality of IC chips 1 are bonded to a stem portion 3 of a metal lead frame 2 using epoxy paste or the like. This adhesion process is carried out by a known method.
This was carried out before the steps related to the present invention. When the lead frame is sent to the bonding position, each stem portion comes into contact with the heating block 6. The metal lead pieces constituting the lead frame are connected by tie bars 4, and their relative positions are fixed.
各加熱ブロックには図示されないヒータと温度センサが
設けられており、所定の温度例えば３００°Ｃに保持さ
れており、ＩＣチップ及びリードフレームのワイヤ接続
部は加熱ブロックにより加熱されて上記温度に達する。Each heating block is equipped with a heater and a temperature sensor (not shown), and is maintained at a predetermined temperature, for example, 300°C, and the wire connections of the IC chip and lead frame are heated by the heating block to reach the above temperature. .
加熱ブロックは同時にワイヤを圧接する支持台でもある
ので、Ａｕワイヤ５を所定位置に圧着してワイヤポンデ
ィングが行われる。Since the heating block also serves as a support base for pressing the wire, wire bonding is performed by pressing the Au wire 5 into a predetermined position.
ボンディングを実行する順序を、最初に第２図のブロッ
クＡ６１上のチップに行い、次いでブロックＢ６２上の
チップに行うものとすると、ブロックＡ上のチップのワ
イヤポンディングが終了したところでブロックＡの加熱
を停止し、その上のチップの温度を下降させる。その間
、ボンディングはブロックＢ上のチップに対して行われ
、該デツプのボンディングが終了すれば、これも同様に
直ちに降温を開始する。以下同様に他のブロック６３を
逐次加熱し、後続チップのボンディングを実施する。ボ
ンディング終了後は直ちにそのブロックの加熱を停止し
て降温させる。Assuming that the order in which bonding is performed is first to the chip on block A61 in FIG. and lower the temperature of the chip above it. During this time, bonding is performed on the chip on block B, and once the bonding of this depth is completed, the temperature of this chip also begins to decrease immediately. Thereafter, other blocks 63 are sequentially heated in the same manner, and subsequent chips are bonded. Immediately after bonding is completed, heating of the block is stopped and the temperature is lowered.
第２図に６０で示したものは予備加熱用ブロックである
。先行するリードフレームに対しワイヤポンディングが
行われている間に、次のリードフレームの最初にボンデ
ィングされる部分がこのブロックによって予備加熱され
る。これは先行リードフレームのボンディングが終了す
れば直ちに次のリードフレームのボンディングが行える
ようにするための処理である。それ以後にボンディング
が行われる部分の加熱は、ボンディング位置に移されて
から開始しても間に合うので、予備加熱は行わない。昇
温速度が緩やかな場合は予備加熱ブロック数を増すこと
になる。ボンディング順が後の方のブロックの加熱は、
ボンディング実施の時刻を見込んで開始すればよい。What is shown at 60 in FIG. 2 is a preheating block. While wire bonding is being performed on the preceding lead frame, the first portion of the next lead frame to be bonded is preheated by this block. This process is performed so that the next lead frame can be bonded immediately after the previous lead frame has been bonded. Preheating of the parts to be bonded thereafter can be started after the parts are moved to the bonding position, so no preheating is performed. If the temperature increase rate is slow, the number of preheating blocks will be increased. Heating blocks that are later in the bonding order is
It is sufficient to start the process in anticipation of the time when bonding will be performed.
各ブロックの加熱開始／停止の時刻は、ボンディング作
業がＭＰＵの制御により行われるので、その作業ステッ
プに合わせて設定される。本発明に於いては加熱停止の
時刻は設定精度が高いほど金属間化合物生成抑止に有効
であるが、加熱開始時刻については遅れないようにする
ことが重要で、若干早すぎても問題はない。Since the bonding work is performed under the control of the MPU, the heating start/stop times for each block are set in accordance with the work steps. In the present invention, the more accurately the heating stop time is set, the more effective it is in suppressing the generation of intermetallic compounds, but it is important not to delay the heating start time, and there is no problem if the heating stop time is set a little too early. .
冷却速度については、急冷し過ぎるとＩＣチップに熱応
力が発生し、ＩＣの特性を劣化させることがあるので、
加熱ブロックの熱容量をある程度大きく設定し、加熱を
停止するだけで所定の冷却速度が得られるようにしてお
けば、本発明の実施に有利である。Regarding the cooling rate, if the IC chip is cooled too quickly, thermal stress may occur on the IC chip and the characteristics of the IC may deteriorate.
It is advantageous to implement the present invention if the heat capacity of the heating block is set to a certain degree large so that a predetermined cooling rate can be obtained simply by stopping heating.
（発明の効果〕
以上説明したように、本発明によればハイブリッドＩＣ
のワイヤポンディング数が多い場合でも、ポンディング
済のワイヤが長時間高温に置かれることがないので、ワ
イヤ材料とボンディングバンド材料の間に金属間化合物
を生成することがなく、ＩＣの特性劣化を来すことがな
い。(Effects of the Invention) As explained above, according to the present invention, a hybrid IC
Even when the number of wire bonding is large, the bonded wire is not kept at high temperature for a long time, so intermetallic compounds are not generated between the wire material and the bonding band material, and the characteristics of the IC are not deteriorated. It never happens.
第１図は本発明の実施例を模式的に示す図、第２図は実
施例の加熱ブロックの配置を示す図であって、
図に於いて
ｌはＩＣチップ、
２はリードフレーム、
３はステム部、
４ばタイバー
５はＡｕワイヤ、
６は加熱ブロック、
６０は予備加熱ブロンク、
６１は加熱ブロックＡ１
６２は加熱ブロックＢ１
６３はその他の加熱ブロック
である。
も
もFIG. 1 is a diagram schematically showing an embodiment of the present invention, and FIG. 2 is a diagram showing the arrangement of a heating block in the embodiment. In the figure, l is an IC chip, 2 is a lead frame, and 3 is a Stem portion, 4 is a tie bar 5 is an Au wire, 6 is a heating block, 60 is a preliminary heating bronck, 61 is a heating block A1, 62 is a heating block B1, and 63 is another heating block. Peaches
Claims (2)
ード片の複数のステム部の各々に半導体チップを鑞付け
し、該半導体チップのボンディングパッドと前記金属リ
ード片との間をワイヤボンディングによって接続する処
理に於いて、 ボンディング作業の終了した前記半導体チップは、前記
ボンディングパッド材料と前記ボンディングワイヤ材料
との間に化学反応が進行することのない温度まで、その
他の半導体チップとは独立に降温させることを特徴とす
るワイヤボンディング方法。(1) A semiconductor chip is brazed to each of a plurality of stem parts of a metal lead piece that is an external connection electrode of an integrated circuit package, and the bonding pad of the semiconductor chip and the metal lead piece are connected by wire bonding. In the process, the temperature of the semiconductor chip after the bonding process is lowered independently of other semiconductor chips to a temperature at which no chemical reaction occurs between the bonding pad material and the bonding wire material. A wire bonding method characterized by:
るための装置であって、 前記半導体チップが接着される前記金属リード片の複数
のステム部を加熱するための加熱ブロックが、前記複数
のステム部の位置に合わせて配置され、 該加熱ブロックはその各々が独立に温度制御されるもの
であることを特徴とするワイヤボンディング装置。(2) An apparatus for carrying out the wire bonding method according to claim (1), wherein a heating block for heating a plurality of stem portions of the metal lead piece to which the semiconductor chip is bonded includes a plurality of stem portions of the metal lead piece to which the semiconductor chip is bonded. 1. A wire bonding apparatus, wherein each of the heating blocks is arranged in accordance with the position of the stem portion, and each of the heating blocks is independently temperature-controlled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1266667A JPH03127842A (en) | 1989-10-13 | 1989-10-13 | Wire bonding method and equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1266667A JPH03127842A (en) | 1989-10-13 | 1989-10-13 | Wire bonding method and equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03127842A true JPH03127842A (en) | 1991-05-30 |
Family
ID=17434018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1266667A Pending JPH03127842A (en) | 1989-10-13 | 1989-10-13 | Wire bonding method and equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03127842A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030082337A (en) * | 2002-04-17 | 2003-10-22 | 기아자동차주식회사 | Gas lifter |
-
1989
- 1989-10-13 JP JP1266667A patent/JPH03127842A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030082337A (en) * | 2002-04-17 | 2003-10-22 | 기아자동차주식회사 | Gas lifter |
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