JPH0312758A - Data erasion detecting device for volatile memory - Google Patents

Abstract

PURPOSE:To obtain a data erasion detecting device containing a simplified circuit constitution by comparing the index data set to a volatile memory with the index data obtained before the supply of power is cut and deciding that the data stored in the volatile memory is erased when no coincidence is obtained between both index data. CONSTITUTION:A state where the electric power is supplied to a power circuit 6 from an external power supply is restored from a state where the supply of electric power is cut to the circuit 6 from the external power supply. Thus a switch of a separation circuit 5 is closed and the supply of power is restarted from the circuit 6. At the same time, the index data Z set at addresses A - D is compared with the index data Z stored in a ROM. If no coincidence is obtained between both index data in terms of just a single one of addresses A - D, it is decided that the data stored in a volatile memory is erased. Then 1 is set to a voltage defective flag and a main process is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention generally relates to a data loss detection device for a volatile memory, and more particularly to a data loss detection device for a semiconductor volatile memory such as a RAM.

(Prior Art) This type of volatile memory data loss detection device generally detects whether data held in the volatile memory has been lost in the manner described below. There is. In other words, the holding voltage of the data retention capacitor of the volatile memory (hereinafter simply referred to as "retention capacitor") when the volatile memory changes from a state where power is not supplied to a state where power is supplied. is input to a voltage level detector, and the voltage level detector detects whether the data holding voltage of the holding capacitor is below a predetermined value. When the data holding voltage detected by the voltage level detector is below a predetermined value, it is determined that the data stored in the volatile memory has been lost.

FIG. 8 is a block diagram showing the configuration of a conventional power system digital protection control device that has the function of the volatile memory data loss detection device described above.

In FIG. 8, the power supply circuit 6 receives power from an external power supply, starts supplying a DC voltage vb of a predetermined magnitude to the central processing unit 2, and then supplies the digital protection control device through the separation circuit 5. Supply to each part being formed.

The separation circuit 5 is composed of a voltage level detector and a switch, and when the output voltage from the power supply circuit 6 detected by the voltage level detector is equal to or higher than a predetermined level value, the disconnection circuit 5 closes the switch and closes the power supply circuit. The output voltage from 6 is directly supplied to each section. On the other hand, the separation circuit 5 is
When the output voltage from the power supply circuit 6 is less than a predetermined level value, a switch is opened to electrically disconnect the power supply circuit 6 and each of the above-mentioned parts.

When the switch of the separation circuit 5 is closed, the holding capacitor C1 is charged by the voltage Va output from the power supply circuit 6 and supplied through the separation circuit 5 and the current limiting resistor R1, and the separation circuit 5 is connected to the power source. Charges are accumulated to hold the data in the volatile memory 1 when the connection with the circuit 6 is cut off. The holding capacitor C1 is configured to discharge the accumulated charge in order to hold data in the volatile memory 1 when the switch is open.

As the volatile memory 1, a semiconductor volatile memory 1 such as a RAM is used, for example. When the switch of the separating circuit 5 is closed, the volatile memory 1 is driven by receiving the voltage Va outputted from the power supply circuit 6 and supplied through the separating circuit 5 and the current limiting resistor R1. It holds and stores various data given from the processing device 2.

On the other hand, when the switch is open, the volatile memory 1 receives a voltage supplied by discharging from the holding capacitor C1, and the voltage value is set to a height that can hold various stored data. The various types of data mentioned above are continued to be held during the period of time.

Like the volatile memory 1, the clock IC 4 is connected to the central processing unit 2 when the switch of the separation circuit 5 is closed.
It is driven by the voltage Va outputted from the power supply circuit 6 and supplied through the separation circuit 5 and the current limiting resistor R1.

The voltage level detection circuit voltage supply capacitor (hereinafter simply referred to as "voltage supply capacitor") C2, when the switch of the release circuit 5 is closed, is similar to the volatile memory 1 and the clock IC 4. Output from the power supply circuit 6, separation circuit 5, current limiting resistor R1, current limiting resistor R
2, and stores charges for driving the voltage level detection port 7 when the separation circuit 5 cuts off the connection with the power supply circuit 6 side.

The voltage supply capacitor C2 is configured such that when the switch is open, the voltage level detection circuit 7 can detect the voltage accumulated in the holding capacitor C1.
The charge accumulated in the voltage level detection circuit 7 is discharged.

Almost the same as the volatile memory 1, clock IC 4, voltage supply capacitor 02, etc. described above, the voltage level detection circuit 7 outputs an output from the power supply circuit 6 when the switch of the separation circuit 5 is closed. 5. Driven by the voltage supplied through the current limiting resistor R1 and the current limiting resistor R2, and receiving the voltage applied from the holding capacitor C1 without passing through the current limiting resistor R2. level is detected and output to the central processing unit 2.

On the other hand, when the switch is open, the voltage level detection circuit 7 is driven by receiving the voltage supplied from the voltage supply capacitor C2 due to discharge from the voltage supply capacitor C2, and is driven through the current limiting resistor R2. The voltage applied to the holding capacitor C175 is detected, and the level of the received voltage is detected and output to the central processing unit 2.

The central processing unit 2 performs control operations using the voltage vb directly applied from the power supply circuit 6, and uses the power system current data il, 1 given through the interface circuit 3.
2 + 13 and power system voltage data v 1 + v
2 * v 3 and store these data in the volatile memory 1, and perform arithmetic processing to perform protection control of the power system based on these data. As a result of the arithmetic processing, the central processing unit 2 generates current data il, i2 . i3, when it is recognized that a change has occurred in the voltage data vl, v'l, v3, it is determined that an accident has occurred in the power system, and a trip signal is sent to the circuit breaker through the interface circuit 3 to protect the power system. It is designed to output a knob command signal f. Central processing unit 2
is a volatile memory when the power supply from the power supply circuit 6 side is cut off based on the voltage failure signal (logic level signal) e outputted from the voltage level detection circuit 7 while putting the clock IC 4 under its control. It is determined whether the data held in 1 has been lost.

Next, the operation of the above configuration will be explained.

When power is being supplied from the external power source to the power supply circuit 6, the switch of the separation circuit 5 is in the closed state, so the output voltage from the power supply circuit 6 is the same as that of the separation circuit 5 and the current limiter. The voltage is supplied to the holding capacitor C1, the volatile memory 1, and the clock IC4 through the resistor R1. Along with this, the output voltage from the power supply circuit 6 is
It is also supplied to the voltage level detection circuit 7 and the 'M pressure supply capacitor C2 through the current limiting resistor R2.

At this time, since a voltage higher than a predetermined value is inputted to the voltage level detection circuit 7 from the power supply side without passing through the current limiting resistor R2, the logic of the voltage failure signal e output from the voltage level detection circuit 7 is The level becomes "H". If the logic level of the voltage failure signal e is "H", it means that the data held in the volatile memory 1 has not been lost. Performs arithmetic processing for power system protection control based on current data and voltage data held in the system.

Through this calculation process, it is determined whether an accident has occurred in the power system.

In the above arithmetic processing, if it is determined that an accident has occurred in the power system, as shown in the flowchart illustrated in FIG.
i2. i3, voltage data vl, v2. v3 is stored in the volatile memory 1, and then in step 92, time data (year, month, day, hour, minute, second) at the time of occurrence of the system accident is stored in the volatile memory 1. Finally, in step 93, a trip command signal f is output to the circuit breaker through the interface circuit 3.

When the power supply from the external power supply to the power supply circuit 6 is cut off, the switch of the separation circuit 5 is in the open state, so the charge accumulated in the holding capacitor C1 is directed toward the power supply circuit 6 side. It is not discharged, but is discharged toward the volatile memory 1, and the data stored in the volatile memory 1 is held by the voltage supply from the holding capacitor C1. However, if the power supply to the power supply circuit 6 from the external power source continues to be cut off as described above, the amount of charge stored in the holding capacitor C1 gradually decreases, and the holding capacitor C1 gradually decreases.
The output voltage from Volatile Memory 1 will eventually drop below the voltage at which Volatile Memory 1 can hold data, and as a result, the data held in Volatile Memory 1 will be lost.

When the state in which the power supply from the external power supply to the power supply circuit 6 is cut off returns to the state in which power is being supplied to the power supply circuit 6 from the external power supply, the first
1. Processing as shown in the flowchart shown in FIG. 1 is performed. That is, when the switch of the separation circuit 5 is closed and power supply from the power supply circuit 6 is resumed, the voltage failure signal e outputted from the voltage level detection circuit 7 is read in step 111, and the voltage failure signal e outputted from the voltage level detection circuit 7 is read in step 121. It is determined whether the logic level of the read voltage failure signal e is "H" or "L". When the power supply from the external power supply to the power supply circuit 6 is cut off and it takes a long time until the power supply is restored, the voltage applied to the voltage level detection circuit 7 during the cutoff period is This is the output voltage from the capacitor C1, and the value of the output voltage is less than a predetermined value for the reason described above. Therefore, the logic level of the voltage failure signal e output from the voltage level detection circuit 7 is “
If the logic level of the voltage failure signal e is "L", it means that the data held in the volatile memory 1 has been lost, so the central processing unit 2
It is determined that the data held in the volatile memory 1 has been lost.

On the other hand, in step 121, the power supply circuit 6 from the external power supply
If the time from when the power supply is cut off to when the power supply is restored is short and the value of the output voltage from the holding capacitor C1 is equal to or higher than a predetermined value, the logic of the voltage failure signal e output from the voltage level detection circuit 7 Since the level is “H”,
It is determined that the data held in the volatile memory 1 has not been lost. Then, in step 131, each of the data held in the volatile memory 1 is displayed on a display section or the like.

(Problem to be Solved by the Invention) By the way, in order for the central processing unit 2 to execute the flowchart illustrated in FIG. 11, the logic level of the voltage failure signal e output from the voltage level detection circuit 7 becomes a problem. However, the logic level of this voltage failure signal e was determined as shown in FIG. That is, in the conventional device, as is clear with reference to FIG. In addition, a voltage V2 larger than the voltage V1 is set as a defect detection voltage (the time when this defect detection voltage V2 is output is set as t2), and by cutting off the power supply from the external power supply, the holding capacitor C1 When the output voltage reaches (2), the voltage level detection circuit 7 outputs a voltage failure signal
The logic level of the circuit was changed from "H" to "L" and outputted.

Therefore, the data loss voltage (1) and the defect detection voltage (V2)
The error between them is equal to the margin, and the error is equal to the margin, and the error is at the time (t2 ), there will be an error between when the voltage reaches V1 (time tl) at which data actually disappears and when the voltage at T1 is V2 - Vl, the volatile memory 1
There is a problem in that it is not possible to accurately detect and determine the loss of data within the computer. Furthermore, if the voltage V1 at which the data held in the volatile memory 1 disappears changes over time, it will not only become difficult to determine whether the data in the volatile memory 1 has disappeared. , there is a possibility of misjudgment. Furthermore, in order to detect the output voltage of the holding capacitor C1, hardware such as a current limiting resistor R2, a voltage level detection circuit 7, a voltage supply capacitor 02 for the voltage level detection circuit, etc. is required, and the number of components is reduced. Another problem was that the circuit configuration was complicated.

Therefore, the present invention has been made to solve the above problems, and its purpose is to accurately detect whether or not data held in volatile memory has been lost when power supply from an external power source is cut off. In addition, when the power supply from an external power source is cut off, there is no need for hardware to detect the output voltage of the capacitor provided to hold data in volatile memory, and the number of components is small, making the circuit configuration easier. An object of the present invention is to provide a volatile memory data loss detection device that can be simplified.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, a data loss detection device for a volatile memory according to the present invention provides a volatile memory that retains data by external power supply and a volatile memory that retains data by external power supply. means for setting in a volatile memory data that serves as an index for determining whether or not the previously selected data has been lost due to a power supply cutoff; and when the cutoff external power supply is restored; means for comparing the index data set in the volatile memory by the setting means with the index data before the power supply cutoff, and determining that the data held in the volatile memory has been lost when the two do not match; The configuration is equipped with the following.

(Function) In the above configuration, when the cut off external power supply is restored, the index data set in the volatile memory by the setting means and the index data before the supply @ cut off are compared and both are matched. Since the data held in the volatile memory is determined to have been lost when the power is not being supplied, the index data set in the volatile memory by the setting means when power is being supplied from an external source is It is possible to directly determine whether the data held in volatile memory has been lost by determining whether or not the data has disappeared from volatile memory when the external power supply that had been previously restored is restored. Even if the voltage at which retained data disappears changes over time, it is now possible to accurately determine whether data has been lost.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a power system digital protection control device having a function as a volatile memory data loss detection device according to an embodiment of the present invention.

The power system digital protection control device shown in FIG. 1 is hardware for detecting the output voltage of the holding capacitor C1 from the conventional power system digital protection control device shown in FIG. 8. Current limiting resistor R2
, the voltage level detection circuit 7, the voltage level detection circuit voltage supply capacitor 02, etc. are removed. Therefore, in FIG. 1, the same components as those shown in FIG. 8 are given the same reference numerals.

In FIG. 1, a power supply circuit 6 receives power from an external power supply, starts supplying a DC voltage vb of a predetermined magnitude to the central processing unit 2, and forms a digital protection control device through a separation circuit 5. supply to each department.

The separation circuit 5 is composed of a voltage level detector and a switch, and when the output voltage from the power supply circuit 6 detected by the voltage level detector is equal to or higher than a predetermined level value, the disconnection circuit 5 closes the switch and closes the power supply circuit. The output voltage from 6 is directly supplied to each section. On the other hand, the separation circuit 5 is
When the output voltage from the power supply circuit 6 is less than a predetermined value, a switch is opened to electrically disconnect the power supply circuit 6 and each of the above-mentioned parts.

The central processing unit 2 performs control operations using the voltage vb directly applied from the power supply circuit 6, and uses current data if, i2 of the power system given through the interface circuit 3.
．． i3 and power system voltage data vl, v2. v3 and stores each of these data in the volatile memory 1, and performs arithmetic processing for performing protection control of the power system based on these data. The central processing unit 2 is
As a result of the arithmetic processing, current data it, i2°i3, voltage data vl, v2 . When it is recognized that a change has occurred in v3, it is determined that an accident has occurred in the power system, and a trip command signal f is output to the circuit breaker through the interface circuit 3 in order to protect the power system. .

FIG. 2 is an explanatory diagram showing the memory contents of the volatile memory 1 included in the power system digital protection control device shown in FIG. 1. In this embodiment, the storage area of the volatile memory 1 is used to store and hold data (referred to as index data, which will be described in detail below) that is different from the data related to the power system described above, as shown in the diagram. Four specific addresses are set: A address, D address, C address, and D address. The above-mentioned address A is, for example, an address for storing current data il, i2°i3 at the time of an accident in the power system, and voltage data Vl, V2 . It is set between the address where V3 is stored. The address D is an address that stores the voltage data Vl, V2°V3 at the time of the accident in the electric power system, and an address that stores the year, month, and day data for specifying the year, month, and day when the accident occurred. is set between. The address C is set between the address where the year, month, and day data is stored and the address where the hour, minute, and second data for specifying the time point of the accident occurrence is stored. Further, the address D is set below the address for storing the hours, minutes, and seconds data in FIG. Note that the year, month, and day data and the hour, minute, and second data are stored in the volatile memory 1 from the central processing unit 2 based on the output signal from the clock IC 4.
The current data and voltage data are data given via the interface circuit 3 and output from the central processing unit 2 to the volatile memory 1. The above-mentioned four specific addresses A to D are designated by the second number Z selected in advance by the central processing unit 2 when power is being supplied to the power supply circuit 6 from the external power supply. The index data that is displayed is stored and held by the output from the central processing unit 2.

Here, to explain the above-mentioned index data Z, the index data Z is arbitrary numerical data, and the data is
For example, the data is stored as non-volatile fixed data in a storage element such as a ROM that is stored in the central processing unit 2. The index data Z is determined by the central processing unit 2 by detecting whether or not the index data Z has disappeared from each of the addresses (A-D addresses) due to a cutoff of the power supply from the external power source to the power supply circuit 6. It is determined whether the data related to the electric power system stored and held at each address other than address D has been lost.

When the power supply from the cut-off external power supply to the power supply circuit 6 is restored, the central processing unit 2 stores the index data Z (i.e., from the ROM, etc.) before the power supply from the external power supply to the power supply circuit 6 is cut off. index data Z) which is non-volatile fixed data stored in Comparison calculations are made with each index data Z. When the central processing unit 2 recognizes that they match across all addresses A to D as a result of the above comparison operation, the central processing unit 2 stores the data at an address other than addresses A to D in the volatile memory. If it is determined that no data regarding the electric power system has been lost and, for example, it is recognized that the index data Z of the address C is inconsistent, all or part of the date data or the hour minute second data may be deleted. is determined to have disappeared or become defective.

Next, the operation of the above configuration will be explained with reference to the flowcharts shown in FIGS. 3 and 4.

When power is being supplied from the external power supply to the power supply circuit 6, the switch of the isolation circuit 5 is in an open state, so the output voltage from the power supply circuit 6 is It is supplied to the holding capacitor C1, the volatile memory 1, and the clock IC4 through the resistor R1. In the above state, the index data Z stored in the ROM etc. is read out, and the read index data Z is written into addresses A to D forming the storage area of the volatile memory 1, respectively (steps 31 and 32). 33.34
). In steps 31 to 34, the index data Z written in the addresses A to D, respectively, and the index data Z, which is non-volatile fixed data stored in the ROM, are compared and calculated, and it is recognized that the two match. For example, set the voltage failure flag to “1”.
It is determined that the data related to the power system in the volatile memory 1 has not been lost (step 35), and the data related to the power system is displayed on a display unit (not shown) (step 36). When an accident occurs in the power system, protection operations for the power system are executed based on the data stored in each of the storage areas. If any one of the index data Z written in the respective addresses A to D in step 35 does not match the nonvolatile fixed data stored in the ROM, the index data Z that does not match is stored. The data related to the power system stored in the address near the address has been lost (or is in a bad state)
As a result, the voltage defect flag is set to "0".

When the state where the power supply from the external power supply to the power supply circuit 6 is cut off returns to the state where power is being supplied from the external power supply to the power supply circuit 6,
Processing as shown in the flowchart shown in FIG. 4 is performed. That is, when the switch of the separation circuit 5 is opened and power supply from the power supply circuit 6 is resumed, the index data Z set at each address A to D in steps 31 to 34 described above is stored in the ROM. It is determined whether the index data Z matches the index data Z (step 41,
42, 43. 44). As a result of the above judgment, if there is a mismatch in any one of the index data Z written to addresses A to D, the voltage defect flag is set to "0#" (step 46), and the process shown in FIG. As a result of the above judgment, A
~All the index data Z written to addresses D are in the above R.
If it matches the index data Z stored in the OM, the voltage defect flag is set to "1#" (step 45), and the flow shifts to the main processing flow shown in FIG.

In the main processing flow, if the voltage failure flag is set to "0", the volatile memory 1
All or part of the data related to the electric power system stored in the memory 1 is not displayed on the display section, etc., and on the other hand, if the voltage failure flag is set to "1", the data is stored in the volatile memory 1. Data regarding the power system currently being displayed is displayed on a display unit, etc., and protection control of the power system is performed based on the displayed data.

As explained above, according to an embodiment according to the present invention,
Set index data Z to a specific address in volatile memory 1 when power is being supplied from an external power supply,
By checking whether the index data Z matches the index data Z at the time of setting after the power supply from the cut-off external power supply is restored, the data related to the electric power system stored in the volatile memory 1 is updated. Since we decided to detect and determine whether or not the memory has disappeared (or whether it has become defective) due to the interruption of power supply from the external power supply, it is possible to detect and determine whether the volatile memory 1
It is now possible to detect whether data within the device has been lost (or defective). That is, according to this embodiment, as is clear with reference to FIG. error between (time tl corresponding to both voltages)
, t2 becomes extremely small, and accordingly, the time T2 when the voltage defect flag changes from "1" to "O" and the time T when the data in the volatile memory 1 disappears.
1 has also become extremely small, making it possible to determine extremely accurately whether data stored in the volatile memory 1 has been lost.

FIG. 6 is an explanatory diagram showing the memory contents of the volatile memory 1 according to another embodiment of the present invention. In the volatile memory 1 according to the embodiment, a specific address (A-D address)
While the same index data Z is stored in four locations,
In the volatile memory 1 shown in FIG. 6, index data is stored at address A, index data Y is stored at address B, index data X is stored at address C, index data W is stored at address D, etc.
This embodiment differs from the embodiment shown in FIG. 2 in that different index data are stored at each address.

FIG. 7 is an explanatory diagram showing the memory contents of the volatile memory 1 according to still another embodiment of the present invention.

In the volatile memory 1 according to the embodiment shown in FIG. 2 and the volatile memory 1 according to the embodiment shown in FIG. 6, index data is stored only for specific addresses such as addresses A-D. However, in the volatile memory 1 shown in FIG. 7, a binary pattern serving as index data is stored in the upper two bits of every address, and this binary pattern is By checking whether the pattern has changed over all addresses, it is possible to more accurately determine whether data has disappeared from the volatile memory 1.

It should be noted that the present invention is not limited to the above-described embodiments; for example, the index data stored in the volatile memory 1 may be the sum of the index data set corresponding to each address in the ROM. It is also possible to use only the lower bits.

Furthermore, the element for supplying power to the volatile memory 1 is not limited to a capacitor (secondary battery), but a negative battery may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, when the cut off external power supply is restored, the index data set in the volatile memory by the setting means is compared with the index data before the power supply cut off. If the two names do not match, it is determined that the data held in the volatile memory has been lost, so it is possible to check whether the data held in the volatile memory was lost when the external power supply is cut off. In addition to being able to accurately detect and judge the voltage, there is no need for hardware to detect the output voltage of the power supply element that is provided to retain data in volatile memory when the external power supply is cut off. It is possible to provide a data loss detection device for a volatile memory that has a small number of points and can simplify the circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a digital protection control device for a power system equipped with a function as a volatile memory data loss detection device according to an embodiment of the present invention, and FIG. 3 and 4 are explanatory diagrams showing the memory contents of the volatile memory included in the digital protection control device for the electric power system illustrated in FIG. 1, and FIG. 6 is a timing chart according to one embodiment of the present invention, FIG. 6 is an explanatory diagram showing the memory contents of a volatile memory according to another embodiment of the present invention, and FIG. 7 is a timing chart according to another embodiment of the present invention. An explanatory diagram showing the memory contents of a volatile memory according to an example, FIG. 8 is a block diagram showing the configuration of a conventional power system digital protection control device equipped with a function as a volatile memory data loss detection device, 9 and 11 are flowcharts of the configuration shown in FIG. 8, and FIG. 10 is a timing chart of the configuration shown in FIG. 8. 1... Volatile memory, 2... Central processing unit, 5...
- Separation circuit, 6...Power supply circuit, C1...Holding capacitor.

Claims (1)

[Scope of Claims] A volatile memory that retains data by being supplied with power from an external source, and an index that, when being supplied with power from the outside, serves as an index for determining loss of data selected in advance due to interruption of the power supply. means for setting data in a volatile memory; and when the interrupted external power supply is restored, the index data set in the volatile memory by the setting means is compared with the index data before the power supply was cut off. A device for detecting data loss in a volatile memory, comprising: means for determining that data held in the volatile memory has been lost when the two do not match.