JPH03125516A - Clock regenerating device - Google Patents

Abstract

PURPOSE:To attain the synchronization even when the variable range of a VCO oscillating frequency by a loop filter is made narrow by varying sequentially the self-running frequency of a voltage controlled oscillator(VCO) sequentially through the operation of the clock recovery circuit. CONSTITUTION:When a charging voltage F of a capacitor 66 reaches a reference voltage Vref, a voltage comparator 74 outputs a high level, a clock is outputted to a flip-flop 78 and signals A, B are both inverted. A P-channel MOSFET 62 is turned off at this point of time, an N-channel MOSFET 64 is turned on, a capacitor 60 is discharged, a P-channel MOSFET 68 is turned on, an N- channel MOSFET 70 is turned off and a capacitor 72 starts charging. When the charging voltage of the capacitor 72 reaches the reference voltage Vref, the output of a voltage comparator 76 goes to a high level and the output of the flip-flop 78 is inverted. Thus, the charging speed of the capacitor 66 is changed according to a control voltage and a 2nd control voltage to control an output frequency.

Description

[Detailed Description of the Invention] (Industrial Application) The present invention reproduces a clock having the same bit rate as the input signal in synchronization with an input signal such as CMI (coded mark inversion). The present invention relates to a clock regeneration device.

[Conventional technology]

Generally, a clock regeneration device uses a phase comparator to detect the phase difference between a human-powered pulse and an output pulse from a voltage-controlled oscillator (hereinafter referred to as vCO), uses a loop filter to remove high-frequency components from this phase difference, and thereby controls vCO. The output pulse was synchronized with the human pulse.

In particular, for digital signals such as CMl, one-shot circuits or the like are used to convert a human pulse into a pulse train with a constant pulse width starting from the falling edge of the pulse train, and the rising or falling edge of the pulse train is compared with the output pulse. Alternatively, phase comparison has been performed by comparing the rising edge or falling edge of the output pulse with the pulse train.

At this point, in an actual circuit, the pulse width of the pulse train needs to be 1/2 of the period of the output pulse.

However, in the conventional device, the pulse width of the one-shot circuit does not follow the frequency change of the output pulse, so the phase difference detection ability of the phase comparator is degraded.

For this reason, the VOC control voltage (loop filter output)
The pulse width is changed by 172 of the period of the output pulse.
This prevents the phase difference detection ability of the phase comparator from deteriorating (see Japanese Patent Laid-Open No. 5FL-205337).

[Problems to be Solved by the Invention] In conventional devices, when integrated into an LSI, the free-running frequency of the clock regenerator and the pulse width of the one-shot circuit vary greatly due to variations in the elements that make up the clock regenerator. Put it away. Therefore, since it is necessary to be able to synchronize the frequency over a wide range of frequencies and to be able to change the pulse width, it was necessary to widen the variable range of vCO by the output from the loop filter and widen the band of the loop filter.

For this reason, the output of the loop filter contains many high-frequency components, and the frequency and phase of the VCO change greatly due to slight fluctuations in the control voltage from the loop filter and noise, so the accuracy of the frequency and phase of the output pulse
In addition to poor stability, the output pulse width of the one-shot circuit also fluctuated, making it impossible to perform highly accurate phase comparisons.

Therefore, in view of the above-mentioned points, an object of the present invention is to provide a clock regeneration device that can synchronize even if the variable range of the VCO oscillation frequency by the loop filter is narrowed, and has excellent precision and stability for one phase of the frequency of the regenerated clock. I decided to do it.

(Means for Solving the Problems) In order to achieve such an object, the crotter reproducing device according to the present invention employs voltage control that generates a clock pulse having the same bit rate as the input signal in synchronization with the input signal. In a clock regeneration device that includes an oscillator, a phase comparator that compares the phase of the output of the oscillator and an input signal, and a loop filter that removes high frequency components of the output signal of the comparator and outputs a control voltage to the oscillator. , an edge detector that detects a level change of an input signal, a pulse generator that forms a pulse of a predetermined width from an output signal of the edge detector and outputs it to the phase comparator, and an output signal or an input of the edge detector. detecting a difference in frequency or phase between a reference clock having the same frequency as the signal bit rate and the output of the voltage controlled oscillator;
a first correction circuit that supplies the voltage controlled oscillator with a second control voltage that changes the output frequency of the voltage controlled oscillator so that the difference becomes smaller; a second variable proportional to the period of the output signal of the voltage controlled oscillator calibrated by the circuit;
It is equipped with a correction circuit.

[For production]

According to the present invention, since the free-running frequency of the vCO is successively varied by the function of the correction circuit, the frequency pull-in range, that is, the variable range of the oscillation frequency of the VCO by the output of the loop filter can be narrowed.

Furthermore, the output pulse width from the pulse former is corrected by the second correction circuit to the optimum width for phase comparison by the phase comparator, and is not dependent on the output of the loop filter, resulting in a highly accurate and stable phase. Comparison becomes possible.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

1. An embodiment of a clock recovery device according to the present invention is shown in FIG. 1. In this figure, 2 to 3 are signals, 20 is an edge detector, 22 is a pulse generator, 24 is a phase comparator, 26 is a loop filter, 28 is a VCO (voltage controlled oscillator), and 30 is a correction circuit. In this embodiment, the first correction circuit and the second correction circuit are shared.

FIG. 2 shows a more detailed configuration diagram of the first embodiment.

The input signal ■ is the voltage difference v between the two input terminals of the voltage comparator 32
The edge detector 20 is composed of a voltage comparator 32 and a falling edge detection section 34, and the pulse generator 22 is composed of a monostable multivibrator.
C028 is composed of an astable multivibrator.

The correction circuit 30 outputs the edge detector output ■ and the regenerated clock ■
a phase comparator 36 that compares the phases of
It has a voltage comparator 44 that compares the voltage of the low-pass filter 42 that further smoothes the output of the output voltage to a value close to a DC component, and the voltage of the reference voltage v1, and the phase comparator 36 and the voltage comparator 44
The control circuit 38 controls the D/A converter 40 according to the output signal of the D/A converter 40. The output voltage of the D/^ converter 40 is output to the VCO 28 and the pulse generator 22.

The embodiment shown in FIGS. 1 and 2 is an example of a clock recovery device used in a CMI (codet mark inversion) code decoder, and FIG. The waveforms of signals ■ to ■ shown inside are shown.

The signal is expressed as the voltage difference between the two input terminals of the edge detector 20.
is input, and the center of the amplitude is detected at the falling edge of the signal (2) as shown in the signal (2) in FIG. The signal (2) is manually inputted to the pulse forming section 22 to become a pulse train signal (2) with a constant width, and the reproduced clock (2) is reproduced as a pulse with a constant period and a phase delayed by 90 degrees with respect to the signal (2).

In this embodiment, for example, if the input signal's pitch rate is 2.048 MH2, the frequency change of the VCO by the loop filter 26 is ±100k11. shall be. Furthermore, the D/A converter 40 is 8 bits, and the LSII
(the least significant bit) changes by 10kl-1.

Next, FIG. 4 shows an operation flowchart of the correction circuit,
FIG. 5 shows the transition state of the frequency of the VCO 213 and the pulse width of the pulse generator 22 during correction.

In this embodiment, an inner claw microcomputer or the like may be used to control the correction circuit using a combination of cables.

The correction circuit starts operating when the power is turned on or the reset signal is input manually to the crotch regeneration device. First, the same circuit 38 resets the D/8 converter 40, and
^ Set the output of the converter 40 to the minimum "o" (step 1). As a result, the output frequency of the VCO 211 becomes the minimum, and the frequency of the input signal (2) is out of the frequency pull-in range of the clock regeneration device, resulting in an asynchronous state. At this time, the output pulse width of the pulse former 22 is also maximum.

The phase comparator 36 samples the output pulse (2) of the VCO 28 for an appropriate period of time, for example, 32 times, using the signal (2), and performs phase comparison (step 2). When the sampled signal is in an asynchronous state, 11 IGH and LOW appear irregularly.

If all the results of 32 samples are not LOW, D/
In step 3), increase the data supplied to the 8-verter 40 by +2. After increasing the output frequency of the VC028 and setting an appropriate phase, phase comparison is performed again. 32
The results of consecutive samples are all 1. If it becomes OW, it is determined that synchronization has been achieved.

At this point, the frequency of the input signal is near the upper limit of the frequency one period holding range of the clock regeneration device, and has a steady phase error. Therefore, the output voltage of the loop filter 26 is higher by the amount of the steady phase error. The output voltage of the loop filter 26 when the manual phase difference of the phase comparator 24 becomes a stem is added to the voltage comparator 44 as a reference voltage v1, and the output voltage of the loop filter 26 is determined as the base jljH'7jj pressure V
1, increase the data to the D/8 converter 40 and increase the output voltage of the +/A converter 40 (
Step 4).

Although the output frequency of the VC028 becomes high once, it becomes synchronized again due to feedback, and at this time the output voltage of the loop filter 26 becomes low. This operation is repeated until the output of the loop filter 26 becomes smaller than the reference voltage, that is, until they almost match. When they match, the output of the correction circuit may be locked and the operation may be terminated, or fine adjustments may be made subsequently.

At this time, the second control voltage is manually applied to the pulse generator 22, and the pulse generator 22 is configured so that the output pulse width is 1/2 of the period of the reproduced clock (2).

Next, pulse former 2 on the nut flow side? and VC[)2
The specific configuration of 8 will be explained with reference to FIG. 6(A) and FIG. 7(A), respectively.

In FIG. 6(A), 46 is a VI converter that converts the control voltage output from the correction circuit 30 into a current.

Now the output signal ■ (signal B in Fig. 6 (II)) is I, OW.
When , PMO5FET50 is off, NMOS
FET 52 is turned on and both ends of capacitor 48 are grounded. Now, the trigger signal ■ (signal C in FIG. 6(B)) which is the output of the edge detector 20 is sent to the flip-flop 54.
When input manually, the output signal ■ becomes the old G11, and PM [
] The S FET 50 is turned on, the NMOS FET 52 is turned off, and the capacitor 48 is charged at a rate proportional to the current generated in the V-E converter (signal E in FIG. 6 (11)
).

When the charging voltage reaches Vref, the output of the voltage comparator 56 becomes HT G l-1, outputs a clock to the flip-flop 54, and the output signal - becomes LOW, and the capacitor 48 is discharged.

1 2 As described above, the pulse generator 20 can vary the pulse width according to the control voltage.

Figure 7 (8) shows VC0 which has two control voltage input terminals.
This is an example of the configuration of 211. The V-1 converters 58 and 60 have the same configuration as the V-1 converter shown in FIG.
Converting a second control voltage from 0 to a current. Now, considering the case where the regenerated clock ■ (signal A in Fig. 7 (B)) is 7QOW, PMO5FET62 is on and NMO
S FET64 is off, capacitor 86 is charged by the current, PMO5FET61 is off, NM
OSFET 70 is turned on and both ends of capacitor 72 are grounded.

When the charging voltage F of the capacitor 66 reaches the reference voltage Vref, the voltage comparator 74 becomes old Gl+, a clock is output to the flip-flop 78, and the signals A and B are both inverted. At this point PMO5FET 62 is off, NMOS FET 64 is on, capacitor 60 is discharged, PMO5FET 68 is on, NMOS FET
70 is turned off and capacitor 72 begins charging. When the charging voltage G of the capacitor 72 reaches the reference voltage Verf, the output of the voltage comparator 76 becomes the old Gll, and the output of the flip-flop 78 is inverted.

Therefore, the rate at which the capacitor is charged changes according to the control voltage and the second control voltage, thereby controlling the output frequency.

On the wood flow side, VC028 capacitor 68°7
2 and the capacitance of the capacitor 48 of the pulse former 22 were made equal, and the reference voltage Verf was made the same, so the pulse width of the pulse former 22 was set to 172
I was able to do this.

As described above, since the pulse former 22 and the VC028 use highly similar circuits such as a monostable multivibrator and an astable multivibrator, respectively, the correction accuracy can be improved.

Note that in the Kinotsu style, the output pulse width of the pulse generator was set to 172 cycles of the reproduced clock, but it is possible to obtain the optimal pulse width for the circuit configuration according to the circuit configuration.

Embodiment 2 FIG. 8 shows a second embodiment to which the present invention is applied. This embodiment is basically the same as the embodiment shown in FIG. This assumes that a reference clock exists. In other words, the correction circuit 32 has a base! 1 (the clock is manually operated, and output so that the oscillation frequency of VC028 (free running frequency of Pl, 1) matches the frequency of the reference clock, and also in response to the output from the level detector of the pulse width corrector. so that the width of the pulse is 1/2 of the 1-bit interval,
This is a correction.

According to this embodiment, the correction circuit can be configured more simply than the first embodiment (see FIG. 1).

Embodiment 3 FIG. 9 shows a third embodiment to which the present invention is applied. In this embodiment, a first correction circuit and a second correction circuit are provided separately, and the first correction circuit 30a has the same function as in the first embodiment, and its output is output only to VC028. There is.

Further, the second correction circuit 30b outputs a voltage for controlling the pulse generator 22 in accordance with the output of the VCO 28.

According to this embodiment, since the correction circuit is installed separately, the degree of freedom in design can be increased.

(Effects of the Invention) As is clear from the above description, according to the present invention, even if the elements vary during manufacturing, the synchronization holding range can be narrowed, and the phase comparator can be adjusted to the optimal width for phase comparison. Therefore, it is possible to realize a clock regeneration device with good frequency/phase accuracy and stability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the configuration of FIG. 1, and FIG. Figure 4 is a flowchart showing the operation of the correction circuit, Figure 5 is a diagram showing the frequency of the VCO and the output pulse of the pulse generator during correction, and Figure 6 (A) is the VCO and pulse formation. Figure 6(B) is a waveform diagram showing the operation of Figure 6(A), Figure 7 is a circuit diagram showing the specific configuration of the device.
Figure (8) is a waveform diagram showing the specific configuration of vCO and pulse generator, Figure 7 (B) is a waveform diagram showing the operation of Figure 7 (A), and Figure 8
The figure is a block diagram showing the second embodiment, and FIG. 9 is a block diagram showing the third embodiment. 26... Loop filter, 28... vCOl 30... Correction circuit, 30a... First correction circuit, 30b... Second correction circuit. 20... Edge detection section, 22... Pulse former, 24... Phase comparator, □○ n JP-A-3 125516 (6) Ku-ha υ Ku-no-ha-' = 1 Fig. JP-A-Hei 3 125516 (13)

Claims (1)

[Claims] 1) A voltage controlled oscillator that synchronizes with an input signal and generates a clock pulse having the same bit rate as the input signal, and a phase comparator that compares the phase of the output of the oscillator and the input signal. , a loop filter that removes high frequency components of the output signal of the comparator and outputs a control voltage to the oscillator, the clock regeneration device comprising: an edge detector that detects a level change of the input signal; a pulse generator that forms a pulse of a predetermined width from an output signal and outputs it to the phase comparator; a reference clock having the same frequency as the bit rate of the output signal or input signal of the edge detector; and a frequency of the output of the voltage controlled oscillator. or a first correction circuit that detects a phase difference and supplies the voltage controlled oscillator with a second control voltage that changes the output frequency of the voltage controlled oscillator so that the difference becomes smaller; and a second correction circuit that changes the pulse width in proportion to the period of the output signal of the voltage controlled oscillator corrected by the first correction circuit.