JPH03125515A - Integrated circuit - Google Patents

Abstract

PURPOSE:To reduce leakage power and undesired radiation in a bus line by providing one or plural C-MOS inverter circuits in cascade connection operating at a lower voltage than a power voltage of an internal logic circuit section as an interface circuit between the logic circuit section and the bus line. CONSTITUTION:One or plural C-MOS inverter circuits 13, 16 in cascade connection operated at a lower voltage than a power voltage Vdd of an internal logic circuit section 20 are provided as an interface circuit between the logic circuit section 20 and the bus line 10. Since the C-MOS inverter circuits 13, 16 for voltage level conversion are provided in this way, a maximum value of a signal sent through the bus line 10 is set lower, while the power voltage Vdd of the logic circuit section 20 is set higher. Thus, the arithmetic speed of the logic circuit section 20 is kept fast and the leakage power and undesired radiation in the bus line 10 are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit with low power consumption, such as a (-MOS structure).

[Summary of the invention]

The present invention provides, for example, in an integrated circuit with low power consumption such as a C-MOS structure, one or a plurality of cascade-connected C-MOS devices that operate at a voltage lower than the power supply voltage of an internal logic circuit section.
By having a MOS inverter circuit as an interface circuit between the logic circuit section and the bus line, leakage power and unnecessary radiation in the bus line can be reduced with a simple circuit configuration without sacrificing the operation speed of the logic circuit section. It was made in a similar manner. Further, according to the present invention, integrated circuits having greatly different operating power supply voltages can be electrically connected to each other without using a special circuit such as a level converter.

[Conventional technology]

Integrated circuits (ICs) having a C-MOS structure are widely used in various applications because of their extremely low power consumption and relatively high operating speed. Also, the standard (, MO
The power supply voltage of an S IC is about 5V, but recently, ICs that operate with a power supply voltage of about 3V have been developed using, for example, a 1.4μm process, and if a finer process is developed, the power supply voltage will increase. It can be made even lower.

On the other hand, when the power supply voltage of an IC with a C-MOS structure decreases, the operating speed also decreases, so ICs that require high-speed calculations in particular
The power supply voltage is kept at around 5V.

[Problem to be solved by the invention]

However, since the maximum input/output signal level of an IC with MO3 structure is approximately equal to the power supply voltage,
When driving an IC with a power supply voltage of about V, this IC
In order to connect the input/output terminals of the IC and the input/output terminals of other ICs, a relatively high frequency digital signal with a maximum value of about 5V is transmitted through a bus line formed on a printed circuit board, for example. In general, if Z is the absolute value of impedance caused by stray capacitance and pure resistance of a bus line, and E is the maximum level of a signal of a predetermined frequency transmitted through that bus line, the leakage will be proportional to E2/Z. Electricity is generated. Therefore, when a relatively high frequency digital signal with a maximum value of about 5V is transmitted through a bus line, leakage occurs in the bus line, even though the power consumption of the C-MOS IC itself is small. There was an inconvenience that the electric power was increased.

Furthermore, since unnecessary radiation on a bus line occurs approximately in proportion to the amplitude of a relatively high frequency signal transmitted on the bus line, the maximum level of the signal and, if the amplitude is large, the radiation from the bus line. There is a problem in that the unnecessary radiation of the IC increases, which may adversely affect other ICs.

Regarding this, even if the power supply voltage of (-MOS IC is lowered), the operating speed is increased by attenuating the harmonic components of the signal by a bypass filter circuit consisting of a capacitor and resistor installed between the bus lines. Although methods to improve this have been proposed, external attachments have the disadvantages of increasing the number of parts, increasing manufacturing costs, and improving the operating speed to a small extent.

In view of the above, an object of the present invention is to propose an IC that can reduce leakage power and unnecessary radiation in the bus line without sacrificing the calculation speed of the internal logic circuit section.

[Means to solve the problem]

For example, as shown in FIG. 1, the IC according to the present invention includes one or a plurality of cascaded CMOS inverter circuits (13), (16) that operate at a voltage lower than the power supply voltage Vdd of the internal logic circuit section (20). its logic circuit part (20
) and the bus line (10).

[Effect]

According to the present invention, a C-MOS for voltage level conversion
Since the inverter circuits (13) and (16) are provided, the maximum value of the signal transmitted through the bus line (10) is set low, while the power supply voltage V, 1.1 of the logic circuit section (20) is set low. Can be set high. Therefore, the calculation speed of the logic circuit section (20) can be maintained at a high speed, and leakage power and unnecessary radiation in the bus line (10) can be reduced.

In this case, when lowering the voltage, one MOS inverter circuit is usually required even if the amount of drop is large.On the other hand, when increasing the voltage,
- By gradually increasing the voltage with a simple circuit configuration in which a plurality of MOS inverter circuits are connected in series, the voltage can be increased by a desired amount without using a special circuit such as a level converter.

Furthermore, according to the present invention, ICs with significantly different operating power supply voltages can be used.
They can be electrically connected by simply adding a simple circuit.

〔Example〕

Hereinafter, one embodiment of the IC of the present invention will be described with reference to FIGS. 1 to 3. In this example, the present invention is applied to two ICs mounted on a printed circuit board and connected to each other by a bus line.

Figure 1 shows the circuit configuration of this example, and in this Figure 1,
(1) and (2) respectively show the IC as a whole, and the ground terminal (1a) of the first IC (1) and the second IC (2)
The grounding terminal (2a) of the first IC (1) is grounded, and the two power supply terminals (1b) and (IC) of the first IC (1) are connected to a voltage of Vd.
d and Vdd VA DC voltage power supply, and the three power terminals (2b), (2c) of the second IC (2)
and (2d), the voltages are Vdd-vA+VIl, Vd, respectively.
d-VA+VB10V. Connect to the DC voltage power supply of Vdd. The relationship between these voltages and specific numerical examples will be described later.

In the first IC (1), (3) is the power supply voltage Vdd
For example, this internal logic circuit [3] is connected to the ground terminal (1a).
and the power supply terminal (1b), and the signal generated at the data output terminal of this internal logic circuit (3) is connected to the P channel MO3 type FET (4) and the N channel 9MO3 type FET (5). Commonly supplied to each gate, F
Connect the source of ET (4) to the power supply terminal (1b), and
Connect the source of E T (5) to the ground terminal (1a),
The drains of FET (4) and (5) are connected, and the signals generated at these drains are connected to the P-channel MO3.
Type F E T (7) and N Chacinet 9MO3 type F E
Commonly supplied to each gate of T (8), F E
, T (7) is connected to the power supply terminal (IC), and F
The source of E T (8) is connected to the ground terminal (1a), the drains of F E T (7) and (8) are connected, and the signals generated at these drains are connected to the output terminal (1d).
so as to supply it to A first C-MOS inverter circuit (6) is formed by FETs (4) and (5), and a second C-MOS inverter circuit (6) is formed by FETs (7) and (8).
An inverter circuit (9) is formed.

Connect the output terminal (1d) of the first IC (1) to the bus line (1
0) to the input terminal (2e) of the second IC (2).

In this second IC(2), (11), (14
) and (17) are respectively P channel MO3 type F E
T , (12>, (15) and (18) are respectively N
Channel MO3FET is shown and a pair of FET(1
1), (12), a pair of FET (1,4),
<15> and a pair of FET(17), (18)
respectively the third CMOS inverter circuit (13)
, a fourth C-MOS inverter circuit (16) and a fifth C-MOS inverter circuit (19) are formed. The third inverter circuit (13) is connected between the power supply terminal (2b) and the ground terminal (2a), and the fourth inverter circuit (13) is connected between the power supply terminal (2b) and the ground terminal (2a).
16) between the power supply terminal (2C) and the ground terminal (2a), and the fifth inverter circuit (19) is connected between the power supply terminal (2C) and the ground terminal (2a).
d) and the ground terminal (2a).

Further, (20) indicates an internal logic circuit that operates with the power supply voltage V d d, and the input terminal (2e) is connected to the third, fourth, and fifth inverter circuits (13), (16), (1
9) to the data input terminal of its internal logic circuit (20). The first (, -M
OS inverter circuit (6) and second (7) IC (
The fifth C-Mo5 inverter circuit (19) in 2) operates as an output buffer circuit and an input vanofer circuit, respectively, and the second C-MOS inverter circuit (9) in the first IC (1). Also, the third and fourth C-MOS inverter circuits (13) <16> in the second IC (2) each substantially operate as a level converter.

The operation of this example will be described with reference to FIG. 2, which is a block diagram of the example shown in FIG.
The values of B and Vc are set as follows.

Vdd=5V, VA=3V, VB=Vo=IV...
...(1) At this time, the power terminal (1b) of the first IC (1) and (
1c) are supplied with voltages of 5V and 2V, respectively, and power supply terminals (2b), (2c) and (2d) of the second IC (2) are supplied with voltages of 3V, 4V and 5V, respectively. . Generally, the input/output level of the 0M03 circuit is approximately equal to the power supply voltage, so the first and second inverter circuits (6),
The high side signal levels of the output signals J1 and J2 of (9) are approximately 5V and 2V, respectively, and the bus line (10)
The maximum level of the transmitted signal is approximately 2V.

In general, the input/output characteristics of a C-MOS inverter circuit with a power supply voltage of V are as shown in Figure 3, and the output voltage is between the voltage corresponding to the high level "1" and the voltage corresponding to the low level "0". When the input voltage is in the so-called linear region, the input voltage is in a region (21
) exists in Then, the output voltage is low level ``0'''
The range of input voltage when it is the voltage corresponding to V-
Since the region (22) is between ΔV and voltage V, voltages Vs, Vc and (VAVs Vc
) respectively satisfy conditional expression (2) of the law, then VI
I<ΔV, vC<ΔV (Va VB vc)<
ΔV...(2) The output signal of the second C-MOS inverter circuit (9) is the output signal of the third, fourth and fifth C-MOS inverter circuits (13)
, (16), and (19), the signals are sequentially accurately inverted and supplied to the internal logic circuit (20). In a C-MOS inverter circuit, ΔV is a value exceeding IV, so when the values of voltages VA, VB, and Vc are set as in equation [1] as shown in the example in Fig. 2, the above conditional expression (2) is satisfied. Therefore, the signal J2 having a high level of approximately 2V transmitted through the bus line (10) is transmitted to the second IC (2
) in the third, fourth, and fifth C-MOS inverter circuits (13), (16), and (19), respectively, invert the signals J whose high-order side levels are approximately 3V, 4V, and 5V.
3. The signal J5, whose lower and higher levels are approximately OV and 5V, respectively, is supplied to an internal logic circuit (20) whose operating power supply voltage is 5V.

As mentioned above, according to the example in FIG. 2, the first IC(1,)
Since the internal logic circuits (3) inside are each driven by a power supply voltage of 5V, there is an advantage of fast calculation speed. On the other hand, as mentioned above, the leakage power in the bus line (10) is proportional to the square of the maximum level of the signal transmitted through this bus line (10), and the unnecessary radiation in this bus line (10) is The amplitude increases in proportion to the amplitude of the signal transmitted through the line (10) (the maximum level of the signal when the minimum level of the signal is OV as in this example).
The bus line (
10) is lowered to about 2V, so even if the bus line (10) is routed for a long time, leakage power and unnecessary radiation in the bus line (10) are extremely low. There is profit.

Furthermore, in this example, the third, fourth and fifth C-MOS inverter circuits (13), (16) of the second IC (2)
) (19) converts the signal J2 transmitted through the bus line (10) into a signal J5 with a maximum level of 5V and supplies it to the internal logic circuit (20), so that the calculation of the internal logic circuit (20) Speed also has the benefit of being maintained quickly. In this case, in this example, three inverter circuits (13),
Since (16) and (19) are connected in cascade to gradually increase the signal level by IV, there is no need to use a special circuit such as a level converter, which has the advantage of reducing manufacturing costs.

Next, another embodiment of the present invention will be described with reference to FIG. In this example, the present invention is applied to a system in which a signal is transmitted via a bus line from a first IC with a low operating power supply voltage to a second IC whose internal logic circuit has a high operating power supply voltage. In FIG. 4, parts corresponding to those in FIG. 2 are given the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 4, (23) indicates a first IC whose operating power supply voltage is 3V, and a 3V DC voltage power supply is connected to the power supply terminal of the first IC (23), and its ground terminal is grounded. (
2A) is the second IC1 (2OA) of this example.
(2A) shows an internal logic circuit with an operating power supply voltage of 5V, which is the main part of the IC (2A). In this second IC (2A), a C-MOS inverter circuit (
19) is substantially integrated with its internal logic circuit (2OA). The other configuration of this second IC (2A) is the same as the second IC (2) in FIG. A bus line (10) is connected to the input terminal (2e) of the person (person).

According to this example, a signal with a maximum level of 3V transmitted on the bus line (10) is gradually transmitted by the cascade-connected C and MOS inverter circuits (13) and (16) in the second IC (2A). Since the voltage is boosted and supplied to the internal logic circuit (2OA) 2, there is no need to use a special circuit such as a level converter, the circuit configuration is simple, and manufacturing costs can be reduced.

Next, FIG. 5 shows an example in which the present invention is applied to a system in which signals are transmitted via a bus line from a first IC having an internal logic circuit with a high operating power supply voltage to a second IC having a low operating power supply voltage. Refer to and explain.

5. Parts corresponding to those in FIG. 2 are denoted by the same reference numerals.
In the figure, (IA) is the first IC, (24) is the second IC whose operating power supply voltage is 3V, and this second
4) Connect a 3V DC voltage power source to the power terminal and ground the ground terminal.

Further, (38) indicates an internal logic circuit which is the main part of the first IC (IA>) and has an operating power supply voltage of 5V.
In C(LA), the (-MOS inverter circuit (16) as the buffer circuit in the example of FIG. 2 is omitted, and a 3V DC voltage power source is connected to the power supply terminal (IC).

The other configuration of this first IC (LA) is the first I in FIG.
The output terminal (1d) of the first IC (LA>) is connected to the second IC via the hash line (10).
(24)-3 4 Connect to the input terminal.

According to the example in FIG. 5, a signal with a maximum level of about 5V from the internal logic circuit (3A) is converted into a signal with a maximum level of 3V by the C-MOS inverter circuit (9), and is transmitted via the bus line (10). It is transmitted to the second IC (24). That is, the C-MOS inverter circuit [9] in the first ■c (IA) has two functions: a buffer circuit and a level transformer, and according to this example, the circuit configuration is simple. There is a certain benefit.

It should be noted that the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations may be adopted without departing from the gist of the present invention.

〔Effect of the invention〕

According to the present invention, the power supply voltage of the internal logic circuit section can be set high while the maximum level of the signal transmitted through the bus line can be set low. This has the advantage of reducing leakage power and unnecessary radiation on the bus line.

Furthermore, by simply adding one C-MOS inverter circuit or multiple cascaded C-MOS inverter circuits, ICs with different operating power supply voltages can be integrated.
There is an advantage in that they can be electrically connected to each other.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing the human output characteristics of a C-MOS inverter circuit, FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a diagram showing a third embodiment of the present invention. It is a block diagram which shows an example. (1) is the first IC, (2) is the second IC, (3) is the internal logic circuit, (9), (13), and (16) are each (, MOS inverter circuit, and (10) is the bus line,(
20) is an internal logic circuit. Agent Hideo Hitomatsu Kuma Mori 5 6 JP-A-3 125515 (6) ``11 XJ1 ``-1--'' 3rd actual sales example Figure 5

Claims (1)

[Claims] Operates at a voltage lower than the power supply voltage of the internal logic circuit 1
1. An integrated circuit comprising: one or a plurality of cascade-connected C-MOS inverter circuits as an interface circuit between the logic circuit section and a bus line.