JPH0312471B2 - - Google Patents
Info
- Publication number
- JPH0312471B2 JPH0312471B2 JP58168745A JP16874583A JPH0312471B2 JP H0312471 B2 JPH0312471 B2 JP H0312471B2 JP 58168745 A JP58168745 A JP 58168745A JP 16874583 A JP16874583 A JP 16874583A JP H0312471 B2 JPH0312471 B2 JP H0312471B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductivity type
- buried layer
- well region
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58168745A JPS6059771A (ja) | 1983-09-13 | 1983-09-13 | 半導体装置およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58168745A JPS6059771A (ja) | 1983-09-13 | 1983-09-13 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6059771A JPS6059771A (ja) | 1985-04-06 |
JPH0312471B2 true JPH0312471B2 (enrdf_load_stackoverflow) | 1991-02-20 |
Family
ID=15873625
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58168745A Granted JPS6059771A (ja) | 1983-09-13 | 1983-09-13 | 半導体装置およびその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6059771A (enrdf_load_stackoverflow) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61139058A (ja) * | 1984-12-11 | 1986-06-26 | Seiko Epson Corp | 半導体製造装置 |
US5190886A (en) * | 1984-12-11 | 1993-03-02 | Seiko Epson Corporation | Semiconductor device and method of production |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5987850A (ja) * | 1982-11-11 | 1984-05-21 | Matsushita Electronics Corp | 半導体装置 |
JPS59222957A (ja) * | 1983-06-02 | 1984-12-14 | Matsushita Electronics Corp | 半導体装置 |
-
1983
- 1983-09-13 JP JP58168745A patent/JPS6059771A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6059771A (ja) | 1985-04-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4484388A (en) | Method for manufacturing semiconductor Bi-CMOS device | |
EP0110313B1 (en) | Semiconductor integrated circuit device and a method for manufacturing the same | |
US4965220A (en) | Method of manufacturing a semiconductor integrated circuit device comprising an MOS transistor and a bipolar transistor | |
KR930008018B1 (ko) | 바이씨모스장치 및 그 제조방법 | |
US4161417A (en) | Method of making CMOS structure with retarded electric field for minimum latch-up | |
US6215160B1 (en) | Semiconductor device having bipolar transistor and field effect transistor and method of manufacturing the same | |
JPH0510828B2 (enrdf_load_stackoverflow) | ||
JP3097092B2 (ja) | Bi―CMOS集積回路およびその製造方法 | |
JPH0557741B2 (enrdf_load_stackoverflow) | ||
US4517731A (en) | Double polysilicon process for fabricating CMOS integrated circuits | |
JPH0148661B2 (enrdf_load_stackoverflow) | ||
JP2736493B2 (ja) | 半導体装置およびその製造方法 | |
JPH02101747A (ja) | 半導体集積回路とその製造方法 | |
JP2000068372A (ja) | 半導体デバイス及びその製造方法 | |
JPH0312471B2 (enrdf_load_stackoverflow) | ||
JP3369862B2 (ja) | 半導体装置の製造方法 | |
US5506156A (en) | Method of fabricating bipolar transistor having high speed and MOS transistor having small size | |
JP3105237B2 (ja) | Dmos型半導体装置の製造方法 | |
EP0281032B1 (en) | Semiconductor device comprising a field effect transistor | |
JP2508218B2 (ja) | 相補型mis集積回路 | |
JP3126082B2 (ja) | 相補形トランジスタおよびその製造方法 | |
JP3856968B2 (ja) | 半導体装置の製造方法 | |
JP3300238B2 (ja) | 半導体装置及びその製造方法 | |
JPH04218972A (ja) | Dmosを含む半導体装置の製造方法 | |
JP3272596B2 (ja) | 半導体装置及びその製造方法 |