JPH03124176A - High speed picture recorder - Google Patents

Abstract

PURPOSE:To store a picture signal from each area into a separate area of a large sized storage device with reliability at a high speed continuously by dividing a CCD area sensor into plural areas sharing equally a horizontal pattern obtained from a horizontal transfer circuit, giving a synchronizing signal in parallel in the same timing and storing the picture signal from each area to separate areas. CONSTITUTION:A pattern is divided to share picture elements obtained from a horizontal transfer circuit of a CCD area sensor 10 impartially and plural output terminals are provided to apply multi-processing to the picture signal. In the video recording mode, after an analog signal from the CCD camera is digitally converted, the signal is shifted by a vertical transfer signal and a horizontal transfer signal given from a CCD drive circuit 12 as a parallel picture signal resulting from pattern division and the result is stored in a field memory 11 sequentially. Then 20 analog signals from the CCD area sensor 10 are subject to 16 gradation A/D conversion in 4-bit and 80 parallel digital outputs are obtained and fed to a large capacity DRAM of the field memory 11 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed recording device that can continuously record images at high speed using a CCD imaging device and reproduce them in slow motion.

[Prior Art] FIG. 7 is a block diagram illustrating a TV broadcast system using a conventional COD camera. The image of subject 30 is CO
The signal is input to the CCD area sensor 32 in the D camera and photoelectrically converted. The image sensor in a video camera is CC
D (C) IARGE C0UPLED DEVI
CCD area sensor 3 in which 0 pixels, which are excluded by solid-state imaging devices using CE), are arranged in a matrix.
The image signal from 2 is multiplexed by a horizontal/vertical synchronization video signal multiplexing circuit 33 on which a synchronization signal from a synchronization generation circuit 34 is superimposed, and is converted into a video signal waveform for an NTSC TV system.

Thereafter, the signal is modulated by a modulator 35, amplified, and transmitted once from a transmitting antenna 36 on a high frequency carrier wave.
On the receiving side, the multiplexed video signal is received via the receiving antenna 38 and the receiver 39, demodulated by the demodulator 40 to extract the video signal, separated into primary colors R-GφB, brightness-modulated, and then directly sent to the TV's cathode ray tube. 42 is the current TV method.
It is a system.

Here, FIG. 8 is a schematic diagram showing an enlarged view of the CCD area sensor 32 shown in FIG. 7. As shown in FIG.

When an image is captured with a video camera, light hits the pixels of the CCD area sensor 32, and the pixels perform photoelectric conversion and accumulate charges.

Charge is accumulated in the photoelectric conversion element (charge accumulation circuit) that is exposed to light. This is scanned and turned into an image signal.

In detail, for example, a total of 200,000 picture materials, 500 horizontally and 400 vertically, are arranged on the CCD area sensor 32.

The vertical transfer circuit 32a transfers signal charges downward every one horizontal sweep (every scan), and the horizontal transfer circuit 82b sequentially transfers the accumulated signal charges to an output terminal and outputs them via the amplifier 32c.

The two-dimensional image information of the CCD area sensor 32 is thus outputted as a one-dimensional output signal 32d. Electric charge is analog information.

If the light is strong, the amount of charge will be large, and if the light is weak, the amount of charge will be small. Conventionally, as shown in FIG.
200,000 pixels in time series from one end of the horizontal transfer circuit 32b of the area sensor 32 in the form of an analog pulse 32d
It is output as .

[Objective of the present invention: Problems to be solved] However, in recording with a conventional COD imaging device, the field screen speed is 30 per second (frame rate 60).
Since only the screen can be photographed, there is a problem that it is not possible to sufficiently record subjects that change at extremely high speeds. It was not suitable for imaging. An object of the present invention is to provide a high-speed image recording device that can record images continuously and reliably at high speed and play them back in slow motion by significantly increasing the number of screens per unit time in conventional imaging systems using semiconductor technology. It is to provide.

[Structure of the present invention: Means for solving the problems] According to the present invention, in order to achieve the above object.

Divide the horizontal transfer circuit in the CCD area sensor in the chair into N equal parts, for example 20 parts.

Horizontal pixels are divided into N horizontal transfer circuits □, and N output terminals are provided for all the horizontal transfer circuits.

The output end of each horizontal transfer circuit is connected to each area of the mass storage device. The synchronization generation circuit is connected to the horizontal transfer circuit and provides a synchronization signal at the same timing. In this way, the pixel extraction time is reduced to 1/N of the conventional method.

[Function J In a high-speed image recording device that captures and records images using a COD imaging device, the horizontal screen obtained from the horizontal transfer circuit in the CCD area sensor in the CCD1i image device is divided into a plurality of areas that are equally divided. Then, a synchronizing signal is applied in parallel to the horizontal transfer circuit of each area at the same timing to store the image signal from each area in a separate area of the mass storage device, and then the image signal is transferred to the horizontal transfer circuit of each area. Combine and play back serially in numerical order.

[Embodiment J ν] An embodiment of the high-speed image recording apparatus of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is an overall block diagram showing a high-speed image recording apparatus of the present invention. l is a CCD video camera, 2 is a COD peripheral circuit that extracts image information from the video camera l, 3
For example, is a mass storage device that stores 500 screens per second, 4 is a computer, 5 is a keyboard, and 6 is a CRT.
7 is a large capacity external storage device corresponding to an optical or magnetic disk, 8 is an NTSC converter, and 9 is a TV receiver. As described later, 1 imaged at high speed
For example, images at 500 screens/second are stored on a mass storage device (R).
AM) 3. Thereafter, it is retrieved using the keyboard 5, processed, and stored in the large-capacity external storage device 7. There is an external storage device for playing back images on the TV receiver 9! Image information is sent from 7 to a TV9 transmitter 9 via a computer 4 and a 1Tsc converter 8. The image information can also be displayed on the computer's CRT display 6 for analysis.

FIG. 2 is a block diagram which is a part of FIG. 1 and shows a characteristic part of the present invention. CCD of CCD video camera
Area sensor lO output signal is 20 from #1 to #20
Each output terminal is connected to a divided field memory 11 consisting of a large-capacity DRAM. A control computer (not shown) is connected to the field memory 11. The CCD area sensor 10 has pixels arranged in a matrix, and while the shutter is open, the pixels irradiated with light accumulate charges.In the present invention, in order to enable high-speed recording, the CCD area sensor 10 The screen is divided so that the pixels obtained from the horizontal transfer signal are divided equally, and multiple output terminals are provided to perform multi-processing of the image signal. In M image mode, the analog signal from the CCD camera is digitally converted and then divided into 9 screens as parallel image signals.

The signals are shifted by the vertical transfer signal and horizontal transfer signal provided by the CCDwA111 circuit 12 and are sequentially stored in the field memory 11.

FIG. 3 is a schematic diagram showing an enlarged view of the CCD area sensor IO of FIG. 2. - For example, 640 pixels in a row and 512 pixels in a column are arranged two-dimensionally in a matrix. Each pixel consists of a photosensitive section (photoelectric conversion section) that converts irradiated light into charges and multiplies them by N, and a transfer section that sequentially transfers analog signals accumulated in this photosensitive section. C
In the CD area sensor lO, the vertical transfer circuits 10a operate all at once to sequentially transfer signal charges for one cycle downward to the horizontal transfer circuit 10b.
b sequentially transfers the accumulated signal charges to the output terminal. In this embodiment, the horizontal transfer circuit Job is divided into 20 equal parts so that each part is responsible for 32 pixels. In practical use, there is a certain limit to the number of terminals of the horizontal transfer circuit 10b in order to form a package. The signals necessary to control this CCD area sensor 10 are a shutter signal that takes in one image and determines the photoelectric conversion time, and a charge
There are vertical transfer signals that vertically shift rows in parallel readout, and horizontal transfer signals that shift charges horizontally by the number of divisions of the horizontal transfer circuit 10b. The number of areas is not limited to 20, but can be divided into any number of areas.The operation of the CCD area sensor 10 will be described as follows.While the shutter is open, the photosensitive portion of the pixel receives an image as light. The charges accumulated in response to light reception are transferred to the transfer section, and the charges in the transfer section are shifted downward one stage at a time by alternately shifting 640 horizontal transfer signals for each pulse of the vertical transfer signal. The horizontal transfer circuit tab arranged at the bottom level moves horizontally one by one to the left in response to the horizontal transfer signal. Therefore, there are 512 vertical transfer pulses and 2
When 32×512 = 18.384 Kihira transfer pulses are applied, all pixels of one screen are taken out from the output terminal. The output image waveform is, compared to the output image waveform in FIG.
Output waveform 10d-1゜10d-2, 1Od-3...-
-1Od-20 FIG. 4 is an enlarged block diagram of the field memory 11. CCD area sensor 10 to 20
The main analog signal undergoes 4-bit, 16-gradation A/D conversion, resulting in 80 digital outputs in parallel. 80
Each output of the book is output at a period of about 100 nsec.

The 80 digital outputs are each connected to a large capacity DRAM of the field memory 11. The input/output of the large-capacity DRAM is controlled by a control circuit (not shown). If one screen is 400,000 pixels and 500 screens are to be photographed per second, each pixel is A/D converted with 4 bits, so a storage capacity of 20 Mbytes (8 bits, 71 bytes) is required. This storage capacity is commercially available 4Mbit L.
This corresponds to 400 SI (DRAM).

FIG. 5 is a waveform diagram showing the output waveform of the CCD area sensor 10. In order to take out all pixels, conventionally to take out the output from the l output terminal.

640 pixels are output for each horizontal scan of one screen.
Therefore, a minimum of 840×512 pulse times, including 640 horizontal transfer pulses and 512 vertical transfer pulses, was required. However, in the uninvented case, the total number of horizontal transfer pulses is 32 trees and vertical transfer pulses fi512 trees: T2
The pulse time of the X512 tree is sufficient, and as a result, the screen speed is 20 times faster than before. Namely.

This means that the time width will be 1/20th. In other words, each section of the horizontal transfer circuit has a different horizontal screen area, but the synchronization signal is output at the same timing.

Therefore, as shown enlarged in FIG. 6, conventionally 64040
I could not proceed to the next screen without image leakage output, but 1
In the present invention, if 32 pixels are omitted, it is possible to proceed to the next screen.

[Effects of the Invention 1] As mentioned above, according to the present invention, images can be recorded at a speed that is, for example, 10 times higher than the conventional screen speed, and the screen capture per unit time can be greatly reduced. By increasing the number of images, it is possible to reliably record phenomena that change at high speed in the natural world, industry, sports, etc., and it is possible to easily analyze and analyze phenomena by slow playback. Phenomena of natural science that cannot be followed by the human eye can be easily observed. Conventionally, a recording method in which optical photographic film is advanced frame by frame at high speed has been used for the above purpose, but there is a lot of economic loss.It was generally not possible to use the equipment for repeated experiments, but this point has also been significantly improved. Improved.

[Brief explanation of drawings]

Fig. 1 is an overall block diagram showing the high-speed image recording Q device of the present invention, Fig. 2 is a block diagram showing the characteristic parts of the present invention in Fig. 1, and Fig. 3 is an enlarged view of the CCDC area sensor in Fig. 2. 4 is an enlarged block diagram of the field memory 11, FIG. 5 is a waveform diagram showing the output waveform of the cco area sensor IO, and FIG. 6 is a partial enlarged waveform diagram of FIG.
FIG. 7 is an overall block diagram illustrating a conventional image recording Q device, and FIG. 8 is a schematic diagram showing an enlarged view of a conventional CCD area sensor 32. 1...000 type video camera. 2.0.CCD peripheral circuit. 3φ...Mass storage device. 4...Computer, 5...Keyboard 6...C
RT display. 7. - Large capacity external storage device. 811...NTSC converter. 9...TV receiver. lO...CCD area sensor. 11...Field memory. 12--CCD drive circuit. 13.--Multiplex circuit. 141・Subject. 15...Synchronization generation circuit. 10a--Vertical transfer circuit. 10b...Horizontal transfer circuit. 10cs...Amplifier Fig. 1 Fig. 4 Fig. 6 Fig. 8 Fig. 2 Procedural amendments November 20, 1999

Claims (2)

[Claims] (1) In a high-speed image recording device that captures and records images using a CCD imaging device, a horizontal screen obtained from a horizontal transfer circuit in a CCD area sensor in the CCD imaging device is divided into a plurality of equally divided areas; A synchronizing signal is applied in parallel to the horizontal transfer circuit of each area at the same timing to store the image signals read out in parallel from each area in separate areas of the mass storage device, and then the image signals are transferred to the number of each area. A high-speed image recording device characterized by sequentially composing and reproducing images in series. (2) Claim 1 in which the mass storage device comprises a DRAM.
The high-speed image recording device described in .