JPH03122520A - Pulse dividing device - Google Patents

Abstract

PURPOSE:To enable division of a reference pulse within the range of a multiplied pulse by a method wherein an encoder of an incremental type is driven at a fixed speed, one period of the reference pulse outputted therefrom is synchronized with PLL and multiplied, a count value of this pulse is compared with prescribed set data, and a pulse output is controlled by an output of the comparison. CONSTITUTION:A multiplier constituting a pulse dividing circuit used for an energy beam drawing device is constructed in the following way. A pulse, e.g. a phase-A output, outputted by an incremental-type encoder 5 driven at a fixed speed by a motor 4 is given as a reference pulse A to a phase detector 7. The detector 7 forms a phase-locked loop together with a low-pass filter 8, a voltage- controlled oscillator 9 and a frequency divider 10, comparing phases of the pulse A and a frequency division output A'' of the frequency divider 10 with each other and making a signal in proportion to the comparison outputted. In the filter 8, only a low-frequency component of the output of the detector 7 is selected, and in the oscillator 9, an oscillation frequency is varied in accordance with an input.

Description

Detailed Description of the Invention <Industrial Application Field> The present invention relates to a technology related to an incremental encoder incorporated in, for example, an energy beam drawing device. The present invention relates to a pulse splitting device that is used to divide a reference pulse into a reference pulse at an arbitrary duty ratio.

<Prior art> For example, an energy beam lithography apparatus, as shown in FIG. A sample 3 fixed on a sample 1 is irradiated with an energy beam such as an electron beam or a laser beam. The sample 3 is used to manufacture a rotating disk to be incorporated into, for example, an incremental type low-resolution encoder, and a predetermined pattern is generated by irradiating the sample 3 with an energy beam from the beam irradiation unit 2 while rotating the sample 3. do.

An incremental rotary encoder (hereinafter simply referred to as "encoder") 5 is integrally connected to the motor 4 for rotationally driving the sample stage 1. The pulse outputted by this encoder 5 (for example, A phase output) is given to the motor 4 and the beam irradiation unit 2 as a reference pulse A,
The rotation operation of the motor 4 is controlled at the timing of this reference pulse A, and the beam irradiation operation of the beam irradiation section 2 is also controlled.

In other words, the beam irradiation unit 2 outputs an energy beam in response to the on/off of the reference pulse A, and thereby the sample 3
A predetermined pattern is drawn on the top surface of the . Therefore, the same pattern as the rotating disk included in the reference encoder 5 is drawn on the sample 3.

Since the number of pulses of the reference pulse A is a constant value, if you want to draw a pattern on the sample 3 that is different from the rotating disk built in the encoder 5, the reference pulse A output from the encoder 5 should be frequency-divided. It is also necessary to divide it as shown by A' in FIG. 11.

For example, if the reference pulse A is frequency-divided using a known frequency divider, a pulse with a frequency of 1/integer can be obtained, and a sinusoidal analog signal can be extracted from the encoder 5 and processed using multiple threshold values. For example, pulses with a frequency that is an integer multiple can be obtained.

<Problems to be Solved by the Invention> However, with these methods, pulses with a frequency that is an integer fraction or an integer multiple of the reference pulse can only be obtained, and it is not possible to obtain pulses with any other frequency. Have difficulty. Furthermore, in the case of a method that processes analog signals, it is necessary to install the encoder with high accuracy in order to obtain an appropriate analog signal, and there is also a limit to the rotation speed of the encoder.

By the way, when the beam irradiation unit 2 is driven by a blanking signal Bx as shown in FIG. 12(1), the actual energy beam is as shown in FIG. 12(1) due to a delay in response speed.
The intensity distribution will be as shown in 2). As a result, the cross section of the pattern drawn on the sample 3 has the rising and falling edges of the blanking signal B, as shown in FIG. 12 (3).
Time τ from K. , τ. It will be delayed only.

If these time delays match (τ0 = τD), the drawing pattern will be similar to the blanking signal BK only by shifting its entire phase with respect to the blanking signal Bx, but in reality, the two do not match. (τ.≠τD), it is difficult to obtain the expected drawing pattern. Therefore, to generate the blanking signal BK, as shown in FIGS. 13 and 14, a rising angle θ and a falling angle θ are set for one period Q of the pulse.

It is necessary to give this as a command and set the duty ratio appropriately.

However, in the conventional pulse division method, this duty ratio can be set arbitrarily, and in order to set an accurate duty ratio, it is necessary to add a dedicated circuit at the subsequent stage.

This invention was made by focusing on the above problem, and the output pulses of an incremental encoder are converted into PLL (
By introducing a method of dividing the pulse by multiplying it by a multiplier (Phase Locked Loop), a new pulse division method that can divide the pulse into any number of pulses at any duty ratio within the frequency range of this multiplied pulse. The purpose is to provide equipment.

Means for Solving the Problems In order to achieve the above object, the present invention uses an incremental encoder that is driven at a constant speed, and a pulse generator that uses the pulse outputted by the encoder as a reference pulse and uses a PL
a PLL multiplier that multiplies the reference pulse in L synchronization;
a counter that counts the multiplied pulses by the PLL multiplier; and one or more comparators that compares the count output of the counter with setting data regarding one period length of the output pulse and each timing of rising and falling. , and a pulse generator that controls the rise and fall of the output pulse based on the output of this comparator.

<Operation> An incremental encoder is driven at a constant speed, one cycle of the reference pulse outputted by this encoder is multiplied in synchronization with the PLL, and the count value of the multiplied pulse is compared with the setting data, and based on the comparison output. Since the rise and fall of the output pulse are controlled, the reference pulse is divided into an arbitrary number of pulses at an arbitrary duty ratio within the frequency range of the multiplied pulse.

<Example> FIG. 1 shows a PL used in the pulse splitting device of the present invention.
The configuration of the L multiplier 6 is shown.

The incremental encoder 5 shown in the figure is driven at a constant speed by the motor 4, and the pulses output by the encoder 5 (for example, A-phase output) are given to the phase detector 7 as a reference pulse A.

This phase detector 7 forms a phase locked loop with a low pass filter 8, a voltage controlled oscillator 9, and a frequency divider 10. That is, the phase detector 7 compares the phases of the reference pulse A and the frequency-divided output A# of the frequency divider 10, and outputs a signal proportional to the phase difference. The low-pass filter 8 selects only low frequency components from the output of the phase detector 7. The voltage controlled oscillator 9 has an oscillation frequency that changes depending on the input voltage, and its oscillation output is divided by a frequency divider 10 and given to the phase detector 7. Note that the oscillation output of the voltage controlled oscillator 9 is outputted to the subsequent circuit as a multiplied pulse A'.

In this way, when the phases of the divided output A# of the frequency divider 10 and the reference pulse A do not match, the oscillation frequency of the voltage controlled oscillator 9 is changed by the output signal of the phase detector 7, and thereby a state of phase synchronization is achieved. Force migration.

Figure 2 (1) shows the relationship between the reference pulse A, the multiplied pulse A', and the divided output A" when the rotation speed of the encoder 5 is constant, and the multiplied pulse A' is connected to the reference pulse. It is multiplied in PLL synchronization with one cycle of .

FIG. 2 (2) shows the relationship between the reference pulse A, the multiplied pulse A', and the divided output A# when the rotational speed of the encoder 5 changes slowly. In this case as well, if the speed change of the encoder 5 is not sudden, the multiplied pulse A' will be accurately synchronized with the reference pulse A.

FIG. 3 shows this PL multiplier 6 with the above configuration.
An asynchronous detection circuit 11 is added to detect that the L multiplier 6 has become asynchronous. The asynchronous detection circuit 11 is supplied with the frequency divided output A1 from the frequency divider 10, and the reference pulse A and the origin signal (Z phase output) Z from the encoder 5, and these inputs provide the PLL signal.
When it is detected that the multiplier 6 is in an asynchronous state,
The asynchronous detection circuit 11 outputs an asynchronous signal ASY to the beam irradiation section 2 to prohibit beam irradiation and interrupt drawing.

FIG. 4 specifically represents each circuit configuration of FIG. 3, with reference numeral 11 an asynchronous detection circuit and 12 a phase synchronization circuit constituting the PLL multiplier 6.

In the illustrated example, the reference pulse A from the encoder 5 is input to one input R of the phase detector 7 in the phase synchronization circuit 12.
, and the phase detection output p of this phase detector 7 is given as
oo is applied to a low-pass filter 8 via a resistor R+. This low-pass filter 8 is composed of a resistor R1 and two capacitors C+ and Ct. In the figure, the input At and the output AO of the phase detector 7 are the input/output of an OP amplifier, and the output AO of this OP amplifier is connected to the resistor R3゜R.
4 and is transmitted to the variable capacitor BC.

This variable capacitor BC has a capacitance that depends on the voltage, and the voltage controlled oscillator 9 is constituted by this variable capacitor BC, capacitor C3, resistor R3, and gate G.

The multiplied pulse A′ which is the oscillation output of this voltage controlled oscillator 9
are two BCD counters 13a forming the frequency divider 10.
, 13b is given as the clock human power T. These counters 13a.

13b constitutes a two-digit counter, and its output T0
~T, the inverted signal of the most significant bit output T is given as the other input Si of the phase detector 7.

5(1) to (6) illustrate the operation of one counter 13a, and FIG. 5(1) shows the clock input T of the multiplied pulse A', ) is the output T0~T,
are shown respectively. Figure 5 (6) shows the carry signal R
This is CO and rises when there is a carry (when data is "9"). Therefore, the other counter 13b has data "99".
A carry signal RCO is output when .

Next, the asynchronous detection circuit 11 includes four D flip-flops 14a to 14d, and a preset manual power P is pulled up to all of these flip-flops 14a to 14d. The first flip-flop 14a receives the carry signal RCO of the counter 13b as a D input, and the inverted signal of the multiplied pulse A' from the voltage controlled oscillator 9 as a clock.

Further, the second flip-flop 14b is supplied with the Q1 output of the first flip-flop 14a as a D input, and the reference pulse A of the encoder 5 as a clock. Note that each of the first and second flip-flops 14a
, 14b, the reset manual power R is pull-amplified.

The 0□ output of the second flip-flop is given as the reset manual power R of the third flip-flop 14c. The D input of this third flip-flop 14c is pulled up, and the origin signal Z is applied as a clock.

The fourth flip-flop 14d is supplied with the outputs of the third flip-flop 14c as D inputs, and the origin signal Z as a clock. Note that the reset manual power R of the fourth flip-flop 14d is pulled up. The 04 output of the fourth flip-flop 14d and the Q, output of the third flip-flop 14e are output to the OR circuit 15, and the OR output is output via the inverting gate 16 as the asynchronous signal ASY.

FIG. 6 shows the operation timing of this asynchronous detection circuit 11. FIG. 6 (1) shows the reference pulse A of the encoder 5, and FIG. 6 (2) shows the output T7 of the most significant bit of the counter 13b. The inverted signal is input to the counter 13b in Fig. 6 (3).
The carry signal RCO of each is shown. The figure also shows an enlarged view of the signal states of each part of the circuit at the time when the reference pulse A rises.

When the phase locked circuit 12 is now in a synchronized state,
First flip-flop 1 in asynchronous detection circuit 11
4 a O) Q, the output is the D input at that moment, that is, the carry signal RC of the counter 13b, in response to the falling edge of the multiplied pulse A' as a clock (the rising edge of its inverted signal).
It is fixed at the O level. This Q1 output is encoder 5
It has a certain width centered around the rising edge of the reference pulse A, and is output to the second flip-flop 14b as a synchronizing signal.

Once the phase synchronization circuit 12 is synchronized, the Q2 output of the second flip-flop 14b corresponds to the D input at that moment, that is, the first flip-flop 14a, in response to the rising edge of the reference pulse A of the encoder 5 as a clock. Noro,
Since it is fixed at the output level, the Q2 output maintains the rHIGHJ level as long as it is synchronized.

FIG. 7 shows the operation timing of the asynchronous detection circuit 11 when the asynchronous detection circuit 11 is out of synchronization. FIG. 7 (1) shows the origin signal Z of the encoder 5, and FIG. The Q, -Q3 outputs of the respective flip-flops 14a to 14c of the seventh
Figure (5) shows the asynchronous signal ASY.

Now, while the encoder 5 rotates once, the phase synchronization circuit 12
Assuming that becomes asynchronous only once, the 02 output of the second flip-flop 14b of the asynchronous detection circuit 11 is r
The level becomes LOW J (see Figure 7 (2)). When this Q2 output reaches the rLOW J level, the third flip-flop 14c is reset, and its Q2 output immediately goes to the rLOW J level (see FIG. 7 (3)).

The third flip-flop 14c is set at the next rise of the origin signal Z, and its Q output attempts to return to the rHIGHJ level, but the fourth flip-flop 14d
When the origin signal Z rises, the Q3 output at the rt, ow J level is transmitted to the Q4 output (Fig. 7 (4)
), thus the 0 of the third flip-flop 14c
The time it takes for the output of the fourth flip-flop 7" 14d to drop to rLOW J is faster than the time it takes for the output to rise to rHIG) IJ.
The output of the flip-flop 14d holds the level rLOWJ until the origin signal Z is input.

Therefore, once the asynchronous detection circuit 11 performs asynchronous detection, the on state of the asynchronous signal ASY is maintained until the encoder 5 outputs the origin signal Z twice (see FIG. 7 (5)). In other words, the state of asynchronous detection is maintained while the encoder 5 rotates at least once.

FIG. 8 shows a configuration example of a pulse division device including the above-mentioned PLL multiplier 6.

In the illustrated example, the reference pulse A from the encoder 5 is input to the PLL multiplier 6, and the multiplied pulse A' is applied to the counter 19 as the clock GK. The preset manual power PS of this counter 19 is given the origin signal Z of the encoder 5, and its preset data is set by the data setter 20. The counted value θ by this counter 19 is given as one input to four comparators 21 to 24.

Further, the illustrated apparatus includes a computer 17, and data setting devices 18a to 18c are connected to the computer 17 to determine the number n of pulses to a reference pulse per one rotation of the encoder 5 and this pulse dividing device. The rising angle θ and falling angle θ of the blanking signal BK that is the output of
, it is possible to input. Also this computer 1
7 receives similar data nl from the higher-level host computer.
l+ θ1. θ, is input.

The data bus of the computer 17 has six registers 25~
30.

Of these, the second register 26 sets the time timing θiゎ, at which the falling angle θ of the blanking signal B is first read into the seventh register 33;
is for setting the time timing θ8 at which the rising angle θ3 of the blanking signal BK is first read into the eighth register 34. 1st. Each second register 25.
The output of 26 is given as the other input of the comparators 21 and 22, and the output IN2 of one comparator 21 is input to the selector 35.
The output INI of the other comparator 22 is provided to the other selector 36, respectively.

The third register 27 stores the falling angle θ of the blanking signal B, and the fifth register 29 stores the rising angle θ1 of the blanking signal B, and the fourth register 29 stores the rising angle θ1 of the blanking signal B. Each of the sixth registers 28 and 30 is used to set the angle θ of one cycle of the blanking signal BK.

The output of the third register 27 is connected to one input of the selector 35, the output of the fourth register 28 is connected to one input of the adder 31, and the output of the adder 31 is connected to the selector 35. 35.

The output side of this selector 35 is input to the comparator 23 via the seventh register 33, and the output of the seventh register 33 is connected to the other input of the adder 31. The comparator 23 compares the count value θ of the counter 10 with the output of the seventh register 33, and supplies the output to the seventh register 33 as a data shift input, and also as a heliset signal R to the R3-flip-flop 37. .

Similarly, the output of the fifth register 29 is connected to one input of another selector 36, and the output of the sixth register 30 is connected to one input of the adder 32.
The output of this adder 32 is connected to the other input of the selector 36. The output side of this selector 36 is input to the comparator 24 via the eighth register 34, and
The output of 4 is connected to the other input of adder 32. The comparator 24 compares the count value θ of the counter 10 with the output of the eighth register 34, and supplies the output to the eighth register 34 as a data shift input, and also supplies it as a set signal S to the R3-flip-flop 37. .

Thus, R3-flip-flop 37 connects each comparator 23.
Reset and set signal inputs are obtained from 24, and a blanking signal BK is generated as the Q output.

In the pulse splitting device having the above configuration, the computer 17
The number of pulses n of the reference pulse A per one revolution of the encoder 5, and the rising angle θ5 and falling angle θ of the blanking signal BK which is the output of this pulse dividing device. is input. The computer 17 calculates the angle θ2 of one period of the blanking signal Bx from the number of pulses n.

Next, the computer 17 stores the rising angle θ8 immediately after the origin signal Z from the rotational speed of the encoder 5 in the seventh register 33.
The timing θin+ to be given to is determined. In this case, if the rise angle θ1 is small, the rise (
Since it is too late to set this in the seventh register 33 after the rotation angle 0') has passed, the rise angle θ5 is read into the seventh register 33 before the origin signal Z rises. Therefore, the blanking signal Bll will not be output during one rotation of the encoder 5 at most, but this can be notified to the outside by a predetermined signal.

FIG. 9 shows the operation of the eighth register 34 as an example.

First, immediately before the encoder 5 outputs the origin signal Z, the output IN of the comparator 22 is given to the selector 36, and thereby the rising angle θ of the blanking signal BK is set in the eighth register 34 (the ninth (See Figure (1)).

Next, the encoder 5 rotates and the count value θ of the counter 19
When θ=θ, the comparator 24 gives its output to the R3 flip-flop 37 as a set signal, and the blanking signal B rises. At this time, the adder 32 adds the rising angle θ and the angle θ of one period, and the added value (θ
, +θP) is sent to the eighth register 34 (Fig. 9 (2)
)reference).

Furthermore, the encoder 5 rotates and the count value θ of the counter 19 is
When θ = θ, +θ, the comparator 24 as above,
Set the output to R3-flip-flop 37 with signal S
, and causes the blanking signal BK to rise.

At this time, the adder 32 calculates (θ, +2θF) and sends it to the eighth register 34 (see FIG. 9 (3)).

In this way, when the encoder 5 rotates once and reaches just before 0°, the rise angle θ is again set in the eighth register 34 by the action of the selector 36 (see FIG. 9 (4)).
.

The seventh register 33 also performs the same operation as described above, and the encoder 5 rotates so that the count value θ of the counter 19 reaches θ. , θ. +θ,.

θ. +2θ2. ..., the comparator 23 gives its output to the R3 flip-flop 37 as a reset signal R, causing the blanking signal BK to fall.

<Effects of the Invention> As described above, the present invention drives an incremental encoder at a constant speed, multiplies one period of the reference pulse outputted by the encoder in synchronization with the PLL, and sets the count value of this multiplied pulse at a predetermined value. Since the pulse output is controlled based on the comparison output by comparing the data, the reference pulse can be divided into any number of pulses at any duty ratio within the frequency range of the multiplied pulse.

In addition, since PLL synchronization is performed every cycle of the reference pulse, the accuracy of the reference encoder is reliably reflected, and errors in the multiplied pulses are not accumulated.Furthermore, there are problems specific to analog signal processing methods. It has a remarkable effect of achieving the purpose of the invention.

[Brief explanation of drawings]

Figure 1 shows the PLL used in the pulse splitting device of this invention.
A block diagram showing the configuration of the multiplier, FIG. 2 is a time chart showing the operation of the PLL multiplier shown in FIG. 1, and FIG. 3 is a PLL multiplier shown in FIG.
A block diagram showing an example in which an asynchronous detection circuit is added to the LL multiplier, Fig. 4 is an electric circuit diagram showing a specific circuit configuration example of Fig. 3, and Fig. 5 shows the operation of the BCD counter in Fig. 4. 6 is a time chart showing the operation timing of the asynchronous detection circuit when it is synchronized, FIG. 7 is a time chart showing the operation timing of the asynchronous detection circuit when it is asynchronous, and FIG. 8 is a pulse division diagram of the present invention. A block diagram showing an example of the configuration of the device, FIG. 9 is an explanatory diagram showing the operation of the eighth register in FIG. 8, FIG. 10 is a perspective view showing the configuration of the energy beam drawing device, and FIG. 11 is a reference pulse diagram. FIG. 12 is a waveform explanatory diagram to explain the delay in response of the energy beam to the blanking signal. FIGS. 13 and 14 are the rising angle and falling angle of the blanking signal. FIG. 5...Encoder 6...PLL multiplier section 1
9...Counter 23.24...Comparator 3
7...Flip-flop 1β) Explanatory drawings (1) (2) (3) (4) [10 Fig. Enel 100° Do-bJaJbuL's Mi 1 Mr. 2 Ho (Po+Yu Fig. s11) 91 minutes without drawings, Akira reply `` Inu-no Otsug Zheng Fang Shuttle〉 to rabbit day-
Figure 14

Claims (1)

[Scope of Claims] An incremental encoder driven at a constant speed, and a PLL system that uses a pulse outputted by the encoder as a reference pulse and synchronizes one period with a PLL to multiply the reference pulse.
A LL multiplier, a counter that counts the multiplied pulses by this PLL multiplier, and a comparison between setting data regarding one period length of the output pulse and each timing of rising and falling pulses and the count output of the counter. A pulse dividing device comprising the above comparator and a pulse generator that generates an output pulse by controlling the rise and fall of an output pulse based on the output of the comparator.