JPH03120961A - Digital video signal processing unit - Google Patents

Abstract

PURPOSE:To generate an accurate control pulse even when a horizontal synchronizing signal pulse (HS) with different timewise position from that of a video signal is inputted by utilizing a microcomputer controlling each processing block through a serial bus. CONSTITUTION:A value representing a time difference between a digital video signal processed by 1st and 2nd video signal processing circuits 10,12 and an HS separated by a synchronizing signal separate circuit 14 is transferred from a microcomputer 17 to a decoder circuit 15 and a counter circuit 16 through a serial bus. Thus, even when how much delay time exists in an input signal, the decoder circuit 15 always sends a control pulse correctly to a video signal processing circuit 12. Then even when the timing between the video signal and the synchronizing signal is not coincident, the time difference is corrected by using the microcomputer 17 and the control pulse is generated always to an accurate position.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device for digitally processing signals of a video tape recorder (hereinafter referred to as VTR).

Background of the Invention In recent years, digital signal processing technology has been widely adopted for VTR video signal processing, and in particular, A/D is used in the middle of analog video signal processing to realize multi-screens and parent-child screens.
The mainstream configuration is to provide a converter and a D/A converter and connect a digital signal processing circuit with a gate array or the like.

FIG. 5 is a block diagram showing the configuration of a conventional analog video signal processing device. The operation will be explained below with reference to the drawings.

In FIG. 5, 50 and 56 are video signal processing circuits that input analog signals, 55 are video signal processing circuits that receive digital signals, and for simplicity, the video signal processing circuit 50 is a circuit that demodulates color signals. , video signal processing circuit 56
The following description will be made assuming that 5 is a circuit that modulates a color signal, and the video signal processing circuit 55 is a circuit that realizes special effects such as multi-screen.

Among the analog video signals applied to the input 5a, the luminance signal is also applied to the synchronization signal separation circuit 52, where a horizontal synchronization signal pulse (hereinafter referred to as H8) is generated. The timing control circuit 51 generates a control pulse such as a burst gate based on the rising edge of H8, and passes it to the video signal processing circuit 50.

On the other hand, the color signal is input to the video signal processing circuit 50, where it is demodulated into two color difference signals based on each control pulse from the timing control circuit 51.

The two demodulated color difference signals are converted into digital data by the A/D converter 53, processed by the video signal processing circuit 55 using H8 as a reference signal, and converted into analog data by the D/A converter 54. After the video signal processing circuit 56
sent to.

For example, when recording on a tape, the video signal processing circuit 56 performs quadrature two-phase modulation on the color difference signal to produce a low frequency converted color signal. It is necessary to send it to the processing circuit 56.

At this time, the reference HS is newly given from the video signal processing circuit 55 as a signal corrected for the delay amount of the color signal delayed by this circuit.

Problems to be Solved by the Invention However, in the conventional configuration described above, it is necessary to output H8 for the video signal after D/A conversion to a predetermined position, so the video signal and H8 are input at different temporal positions. , it is necessary to install a delay circuit in front of the timing control circuit 57 to correct the time difference, and if the above configuration is entirely replaced with digital signal processing, a delay circuit that is even larger in scale than an analog circuit is required. It had the problem of becoming

The present invention solves the above conventional problems, and focuses on the fact that since all signal processing is done digitally, the reference signal for timing control can be the rising edge of the HS.
To provide a video signal processing device capable of generating accurate control pulses even if H8 at a different temporal position from the video signal is input by using a microcomputer that controls each processing block via a serial bus. The purpose is to

Means for Solving the Problems To achieve this object, the video signal processing device of the present invention includes a first video signal processing circuit that processes a digital video signal, and a synchronization signal that separates a synchronization signal from the digital video signal. a first signal processing block comprising a separation circuit and a timing control circuit that generates a timing pulse for controlling the first video signal processing circuit with a horizontal synchronization signal pulse that is an output of the synchronization signal separation circuit; 1st
a second video signal processing circuit that processes the output of the video signal processing circuit based on the horizontal synchronization signal pulse that is the output of the synchronization signal separation circuit; and a second video signal processing circuit that processes the output of the second video signal processing circuit. a counter circuit that receives the horizontal synchronizing signal pulse and counts a predetermined number of times; and a pulse that decodes the output of the counter circuit and controls the third video signal processing circuit. a second signal processing block comprising a decoder circuit that generates;
Said 1st. The third video signal processing circuit is constituted by a microcomputer that connects the decoder circuit and the counter circuit with a serial bus.

Effects The present invention has the above-described configuration. By transferring the value representing the time difference between the digital video signal processed by the second video signal processing circuit and the H8 separated by the synchronization signal separation circuit from the microcontroller to the decoder circuit and counter circuit via the serial bus, the input No matter how much signal delay time there is, the decoder circuit can always send the correct control pulse to the third video signal processing circuit.

Embodiments Hereinafter, digital video signal processing apparatuses according to embodiments of the present invention will be described with reference to the drawings, mainly taking color signal processing as a specific example.

FIG. 1 is a block diagram showing the configuration of a digital video signal processing device of the present invention.

When a digital video signal having the timing of the luminance signal 411 and color signal 42 shown in FIG. 4 is input to the input 1a, the video signal processing circuit 10 synchronously detects the color signal and demodulates it into two color difference signals. At that time, based on the burst signal,
In order to perform processing such as PC (automatic phase control) and ACC (automatic gain control), burst gate pulses at various timings are required. In order to generate these control signals, the synchronization signal separation circuit 14 generates a horizontal synchronization signal pulse H843 from the luminance signal 41, and the timing control circuit 13 generates the above-mentioned burst gate pulse using this pulse as a reference.

The digital video signal processed by the first signal processing block 1 is subjected to processing for realizing special effects in the video signal processing circuit 11, and the delay time of each of the luminance signal 44 and color signal 45 in FIG. Video signals with different values are input to the video signal processing circuit 12 of the second signal processing block 2.

On the other hand, since the horizontal synchronizing signal pulse is input at the timing shown in H843, it is earlier than H846, which is the original reference pulse obtained from the luminance signal 44, by the time ND, and the counter circuit 16 corrects the time N11. It works like this.

As shown in FIG. 2, the counter circuit 16 is connected to a bus decoder 20. A differentiation circuit 21 consisting of a D flip-flop 24 and an AND gate 25. It is composed of an N-1 detection circuit 22 and an N-ary counter 23.

The bus decoder 20 is a circuit that decodes serial values of addresses and data sent from the microcomputer 17 via the serial bus, and outputs them as parallel data. Address information identifies multiple bus decoders that exist in an LSI circuit. When the address assigned to each bus decoder matches the address sent via the serial bus, the data sent after the address information The information can be received by a bus decoder.

When correcting the time ND, serial data N - N n is sent to the input 2a, and after being parallel-converted by the bus decoder 20, this value is converted into N-ary at the timing of the rising edge of H8 detected by the differentiating circuit 21. counter 23
is set as the initial value and counting begins. and,
When counting up to N-1, the N-1 detection circuit 22 is activated, the output of the N-ary counter 23 is reset, and counting starts from zero.

In other words, when the output of the N-ary counter 23 is reset, the brightness signal 44 and H84B are in a relationship, so that the correct count value is always sent to the decoder circuit 15 with respect to the brightness signal, regardless of the timing with H8. Become.

As shown in FIG. 3, the decoder circuit 15 is divided into a luminance signal decoder section 3 and a chrominance signal decoder section 4, and counter output data input from the input terminal 3a is applied to each decoder section.

In the luminance signal decoder section 3, since the timings of the luminance signal and H8 always match as described above, the Y1 detection circuit 35. detects the fixed decoded values Yll Y21 Y31... Y2 detection circuit 38. Y*detection circuit 3
7. . . . can be realized using only a gate circuit, and with this, a predetermined pulse having l clock width can be obtained. Furthermore, when a pulse with a width of several clocks is required, a set/reset flip-flop (hereinafter referred to as an RS flip-flop) 34, which is set by the output of the Y2 detection circuit 36 and reset by the output of the Y3 detection circuit 37, can be used. good.

In the chrominance signal decoder section 4, as shown in FIG. 4, the chrominance signal is delayed by a time Nc with respect to the luminance signal;
Since the O value changes depending on the video signal processing circuit 11, a fixed decode value cannot be set. Therefore, the original decoded value plus the value for the time Ne is used as correction data, which is transferred on the serial bus, converted into parallel data by the bus decoders 30, 31, and 32, and then sent to the coincidence detection circuit 33. A match is made with the counter output data. This circuit can be realized, for example, by a subtracter, and outputs a one-clock width pulse when the calculation result is zero, indicating a match.

And output 3b+ 3c+ 3d+ 3el"
'The pulse T Yl+ T Y2.
T C1, T C2, . . . are sent to the video signal processing circuit 12.

In this circuit, the above-mentioned TCl is used, for example, as a control pulse for the 90° rotation specified in the VH8 standard during recording, and as a gate pulse for reducing the burst signal by 6 dB during playback.

A signal such as Te3 is used.

Note that when the timings of the luminance signal and the color signal always match, the color signal decoder section 4 has the same configuration as the luminance signal decoder section 3, so that the coincidence detection part can be simplified.

Effects of the Invention As described above, the present invention uses a microcomputer to correct the time difference even if the timings of the video signal and the synchronization signal do not match, and can always generate control pulses at accurate positions. This has great practical effects, such as allowing extremely flexible LSI development since circuit design can be done without being aware of the signal processing circuit that already exists.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a device in an embodiment of the present invention, FIG. 2 is a circuit block diagram showing a specific configuration of a counter circuit, and FIG. 3 is a circuit block diagram showing a specific configuration of a decoder circuit. 4 is a waveform diagram showing the timing relationship between a luminance signal, one color signal, and a synchronization signal, and FIG. 5 is a block diagram showing the configuration of a conventional device. 10... Video signal processing circuit, 13... Timing control circuit, 14... Synchronization signal separation circuit, 1
5... Decoder circuit, 16... Counter circuit,
17... Microcomputer, 20... Bus decoder, 21... Differentiation circuit, 22... N-1 detection circuit, 23... N-ary counter, 33... Coincidence detection circuit.

Claims (1)

[Scope of Claims] (1) A first video signal processing circuit that processes a digital video signal, a synchronization signal separation circuit that separates a synchronization signal from the digital video signal, and a horizontal signal that is the output of the synchronization signal separation circuit. a first signal processing block comprising a timing control circuit that generates a timing pulse for controlling the first video signal processing circuit with a synchronization signal pulse; and a first signal processing block that separates the output of the first video signal processing circuit from the synchronization signal. a second video signal processing circuit that processes based on the horizontal synchronization signal pulse that is the output of the circuit; a third video signal processing circuit that processes the output of the second video signal processing circuit; and the horizontal synchronization signal. A second signal processing device comprising a counter circuit that receives a pulse as input and counts a predetermined number of times, and a decoder circuit that decodes the output of the counter circuit and generates a pulse for controlling the third video signal processing circuit. A digital video signal processing device comprising: a block; and a microcomputer that connects the first and third video signal processing circuits, the decoder circuit, and the counter circuit with a serial bus. (2) The digital video signal processing device according to claim 1, wherein the first, second, and third video signal processing circuits are circuits that perform processing such as modulation and demodulation on the digitized luminance signal and color signal. (3) The digital video signal processing device according to claim 1, wherein the synchronization signal separation circuit is a circuit that separates the synchronization signal from the input luminance signal and generates a horizontal synchronization signal pulse. (4) The digital video signal processing device according to claim 1, wherein the counter circuit is a circuit that starts counting from a counter start value given from the serial bus at the rising edge of the horizontal synchronizing signal pulse. (5) The digital video signal processing device according to claim 1, wherein the microcomputer is a circuit that asynchronously sends out addresses and data assigned to each control block on a serial bus.